coreboot-gerrit August 2018

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Change in coreboot[master]: security/vboot: Split fwid.region build target
by Raul Rangel (Code Review) 07 Aug '18

07 Aug '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/27884 ) Change subject: security/vboot: Split fwid.region build target ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27884/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27884/1//COMMIT_MSG@11 PS1, Line 11: objects are not invalidated when bumping the fwid. > I don't believe this, actually. […] You assessment is correct, the target will only get created once and never touched again. This is the current behavior. When .config or Kconfig change we also need to blow away the $(obj) dir as well. The coreboot ebuild currently passes along the VBOOT_FWID_VERSION via .config. https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/… This means we need to blow away essentially everything because the config.h changes on every build. By modifying the coreboot ebuild to write out fwid.version and not update the .config then the .config will remain constant when only making source changes. By modifying the ebuild to only re-run make oldconfig if the new.config != old.config then the config.h timestamp will not change either. I'll get the patches for the ebuild uploaded soon. I need to clean them up. -- To view, visit https://review.coreboot.org/27884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0 Gerrit-Change-Number: 27884 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 14:18:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/cannonlake_rvp/devicetree.cb: Remove misleading comments
by Nico Huber (Code Review) 07 Aug '18

07 Aug '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/27927 ) Change subject: mb/intel/cannonlake_rvp/devicetree.cb: Remove misleading comments ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/27927/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27927/1//COMMIT_MSG@7 PS1, Line 7: .cb no suffix needed https://review.coreboot.org/#/c/27927/1//COMMIT_MSG@7 PS1, Line 7: misleading comments they are not supposed to be comments. maybe rather `Remove spurious CPP directives`. https://review.coreboot.org/#/c/27927/1//COMMIT_MSG@9 PS1, Line 9: The devicetree is not run through a C pre-processor, so remove it. Hmmmm, I guess the extra chip entries do matter for I2C. Because that bus isn't probed... I guess the drivers add spurious ACPI code currently. That should be fixed if it's the case. -- To view, visit https://review.coreboot.org/27927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Gerrit-Change-Number: 27927 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 07 Aug 2018 14:12:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/cannonlake_rvp/devicetree.cb: Remove misleading comments
by Arthur Heymans (Code Review) 07 Aug '18

07 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27927 Change subject: mb/intel/cannonlake_rvp/devicetree.cb: Remove misleading comments ...................................................................... mb/intel/cannonlake_rvp/devicetree.cb: Remove misleading comments The devicetree is not run through a C pre-processor, so remove it. Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/27927/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 4c62800..6f1b6eb 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -95,7 +95,6 @@ device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 on - #if IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) chip drivers/i2c/max98373 register "vmon_slot_no" = "4" register "imon_slot_no" = "5" @@ -112,7 +111,6 @@ register "name" = ""MAXL"" device i2c 32 on end end - #elif IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT) chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)" register "btn_cfg" = "50" @@ -130,7 +128,6 @@ register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end - #endif end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 @@ -167,14 +164,12 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - #if IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT) device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" register "sdmode_delay" = "5" device generic 0 on end end - end # Intel HDA #endif device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI -- To view, visit https://review.coreboot.org/27927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8 Gerrit-Change-Number: 27927 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: amd/stoneyridge: Dump MCA registers
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27926 ) Change subject: amd/stoneyridge: Dump MCA registers ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27926/1/src/soc/amd/stoneyridge/cpu.c File src/soc/amd/stoneyridge/cpu.c: https://review.coreboot.org/#/c/27926/1/src/soc/amd/stoneyridge/cpu.c@120 PS1, Line 120: static const char *mca_bank_name[] = { static const char * array should probably be static const char * const -- To view, visit https://review.coreboot.org/27926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02 Gerrit-Change-Number: 27926 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 14:03:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/amd: Correct number of MCA banks cleared
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27923 ) Change subject: cpu/amd: Correct number of MCA banks cleared ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family12/model_12… File src/cpu/amd/agesa/family12/model_12_init.c: https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family12/model_12… PS1, Line 62: for (i = 0; i < num_banks; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family14/model_14… File src/cpu/amd/agesa/family14/model_14_init.c: https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family14/model_14… PS1, Line 85: for (i = 0; i < num_banks; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family15tn/model_… File src/cpu/amd/agesa/family15tn/model_15_init.c: https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family15tn/model_… PS1, Line 80: for (i = 0; i < num_banks; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family16kb/model_… File src/cpu/amd/agesa/family16kb/model_16_init.c: https://review.coreboot.org/#/c/27923/1/src/cpu/amd/agesa/family16kb/model_… PS1, Line 78: for (i = 0; i < num_banks; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/27923/1/src/cpu/amd/family_10h-family_15h/m… File src/cpu/amd/family_10h-family_15h/model_10xxx_init.c: https://review.coreboot.org/#/c/27923/1/src/cpu/amd/family_10h-family_15h/m… PS1, Line 119: for (i = 0; i < num_banks; i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Gerrit-Change-Number: 27923 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 14:01:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Dump MCA registers
by Marshall Dawson (Code Review) 07 Aug '18

07 Aug '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27926 Change subject: amd/stoneyridge: Dump MCA registers ...................................................................... amd/stoneyridge: Dump MCA registers Add a function to provide a rudimentary dump of the Machine Check Architecture registers. These values survive a warm reset. Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 47 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/27926/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 52b1c9c..2d58f39 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -117,22 +117,65 @@ set_warm_reset_flag(); } -static void model_15_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); +static const char *mca_bank_name[] = { + "Load-store unit", + "Instruction fetch unit", + "Combined unit", + "Reserved", + "Northbridge", + "Execution unit", + "Floating point unit" +}; +static void check_mca(void) +{ int i; msr_t msr; int num_banks; - /* zero the machine check error status registers */ msr = rdmsr(MCG_CAP); num_banks = msr.lo & MCA_BANKS_MASK; + + if (is_warm_reset()) { + for (i = 0 ; i < num_banks ; i++) { + if (i == 3) /* Reserved in Family 15h */ + continue; + + msr = rdmsr(MC0_STATUS + (i * 4)); + if (msr.hi || msr.lo) { + int core = cpuid_ebx(1) >> 24; + + printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", + core, i, mca_bank_name[i]); + + printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_ADDR + (i * 4)); + printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_MISC + (i * 4)); + printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL + (i * 4)); + printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", + i, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL_MASK + i); + printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", + i, msr.hi, msr.lo); + } + } + } + + /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; for (i = 0 ; i < num_banks ; i++) wrmsr(MC0_STATUS + (i * 4), msr); +} +static void model_15_init(struct device *dev) +{ + check_mca(); setup_lapic(); } -- To view, visit https://review.coreboot.org/27926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02 Gerrit-Change-Number: 27926 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com>

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Change in coreboot[master]: amd/fam15: Add MCA bank register definitions
by Marshall Dawson (Code Review) 07 Aug '18

07 Aug '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27925 Change subject: amd/fam15: Add MCA bank register definitions ...................................................................... amd/fam15: Add MCA bank register definitions Define the additional registers used for each Machine Check Architecture bank. Change-Id: I962f23662789a3b974f4946555f67fcfc6147df8 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/cpu/amd/amdfam15.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27925/1 diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 3095dd1..1441c05 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -18,7 +18,11 @@ #define MCG_CAP 0x00000179 # define MCA_BANKS_MASK 0xff +#define MC0_CTL 0x00000400 #define MC0_STATUS 0x00000401 +#define MC0_ADDR 0x00000402 +#define MC0_MISC 0x00000403 +#define MC0_CTL_MASK 0xC0010044 #define MSR_SMM_BASE 0xC0010111 #define MSR_TSEG_BASE 0xC0010112 #define MSR_SMM_MASK 0xC0010113 -- To view, visit https://review.coreboot.org/27925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I962f23662789a3b974f4946555f67fcfc6147df8 Gerrit-Change-Number: 27925 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com>

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Change in coreboot[master]: cpu/amd: Correct number of MCA banks cleared
by Marshall Dawson (Code Review) 07 Aug '18

07 Aug '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27923 Change subject: cpu/amd: Correct number of MCA banks cleared ...................................................................... cpu/amd: Correct number of MCA banks cleared Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/amd/agesa/family12/model_12_init.c M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/include/cpu/amd/amdfam15.h M src/include/cpu/amd/amdfam16.h M src/soc/amd/stoneyridge/cpu.c 11 files changed, 46 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27923/1 diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index afdfb3b..d38a8f3 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -27,6 +27,8 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam12.h> +#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401 static void model_12_init(struct device *dev) @@ -35,6 +37,7 @@ u8 i; msr_t msr; + int i num_banks; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -52,9 +55,11 @@ disable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 5; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); } diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 257f81f..fc4227a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -28,12 +28,15 @@ #include <arch/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h> +#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401 static void model_14_init(struct device *dev) { u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -75,9 +78,11 @@ x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); } diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 1e0375f..d579a5a 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -35,6 +35,7 @@ u8 i; msr_t msr; + int num_banks; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) @@ -72,9 +73,11 @@ x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); } diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 9909793..0c584f7 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -34,6 +34,7 @@ u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -70,9 +71,11 @@ x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); } diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 61eb813..acc65e2 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -32,6 +32,8 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/msr.h> +#define MCG_CAP 0x179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x401 static inline uint8_t is_gt_rev_d(void) @@ -62,6 +64,7 @@ { u8 i; msr_t msr; + int num_banks; struct node_core_id id; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -109,9 +112,11 @@ disable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 5; i++) { + for (i = 0; i < num_banks; i++) { wrmsr(MC0_STATUS + (i * 4), msr); } diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 592ca4f..0269a1e 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -35,6 +35,7 @@ u8 i; msr_t msr; + int num_banks; int msrno; unsigned int cpu_idx; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) @@ -69,9 +70,11 @@ x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 24c2aea..424a6c0 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -51,6 +51,7 @@ u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -81,12 +82,13 @@ x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); - /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index b9e0185..160d6d8 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -34,6 +34,7 @@ u8 i; msr_t msr; + int num_banks; int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; @@ -66,12 +67,13 @@ x86_enable_cache(); /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) + for (i = 0; i < num_banks; i++) wrmsr(MC0_STATUS + (i * 4), msr); - /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index c28ec13..3095dd1 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -16,6 +16,8 @@ #ifndef CPU_AMD_FAM15_H #define CPU_AMD_FAM15_H +#define MCG_CAP 0x00000179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x00000401 #define MSR_SMM_BASE 0xC0010111 #define MSR_TSEG_BASE 0xC0010112 diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h index 8d8be83..8b7503d 100644 --- a/src/include/cpu/amd/amdfam16.h +++ b/src/include/cpu/amd/amdfam16.h @@ -16,6 +16,8 @@ #ifndef CPU_AMD_FAM16_H #define CPU_AMD_FAM16_H +#define MCG_CAP 0x00000179 +# define MCA_BANKS_MASK 0xff #define MC0_STATUS 0x00000401 #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6289174..7fff120 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -121,11 +121,14 @@ int i; msr_t msr; + int num_banks; /* zero the machine check error status registers */ + msr = rdmsr(MCG_CAP); + num_banks = msr.lo & MCA_BANKS_MASK; msr.lo = 0; msr.hi = 0; - for (i = 0 ; i < 6 ; i++) + for (i = 0 ; i < num_banks ; i++) wrmsr(MC0_STATUS + (i * 4), msr); setup_lapic(); -- To view, visit https://review.coreboot.org/27923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Gerrit-Change-Number: 27923 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add warm reset detection
by Marshall Dawson (Code Review) 07 Aug '18

07 Aug '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27924 Change subject: amd/stoneyridge: Add warm reset detection ...................................................................... amd/stoneyridge: Add warm reset detection Extend the existing reset handling features in Stoney Ridge to plan for, and recognize, warm resets. The ColdRstDet bit is always zero on a cold reset, and is intended as a mechanism for the BIOS to determine the type of a reset that occurred. Set ColdRstDet=1 after all cores have been initialized, so that any subsequent reset may be identified as warm/cold. A later patch will check the value during mp_init. Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/reset.c 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27924/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 7fff120..52b1c9c 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -113,6 +113,8 @@ /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + set_warm_reset_flag(); } static void model_15_init(struct device *dev) diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 666be10..56ae363 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -30,6 +30,7 @@ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ #define HT_INIT_CONTROL 0x6c # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10)) +# define HTIC_COLD_RST_DET BIT(4) /* NB IOAPIC registers */ #define NB_IOAPIC_INDEX 0xf8 @@ -116,5 +117,7 @@ void nb_ioapic_write(unsigned int index, uint32_t value); void *get_ap_entry_ptr(void); void set_ap_entry_ptr(void *entry); +void set_warm_reset_flag(void); +int is_warm_reset(void); #endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index a133a88..738ec59 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -21,6 +21,21 @@ #include <device/pci_ops.h> #include <soc/southbridge.h> +void set_warm_reset_flag(void) +{ + u32 htic; + htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); + htic |= HTIC_COLD_RST_DET; + pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); +} + +int is_warm_reset(void) +{ + u32 htic; + htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); + return !!(htic & HTIC_COLD_RST_DET); +} + /* Clear bits 5, 9 & 10, used to signal the reset type */ static void clear_bios_reset(void) { @@ -42,6 +57,7 @@ void do_soft_reset(void) { + set_warm_reset_flag(); clear_bios_reset(); /* Assert reset signals only. */ -- To view, visit https://review.coreboot.org/27924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e Gerrit-Change-Number: 27924 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com>

1 0

Change in coreboot[master]: cpu/amd: Rename MCA status register
by Marshall Dawson (Code Review) 07 Aug '18

07 Aug '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/27922 Change subject: cpu/amd: Rename MCA status register ...................................................................... cpu/amd: Rename MCA status register Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its MC0_STATUS address. Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/amd/agesa/family12/model_12_init.c M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/include/cpu/amd/amdfam15.h M src/include/cpu/amd/amdfam16.h M src/soc/amd/stoneyridge/cpu.c 11 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/27922/1 diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index b4757c8..afdfb3b 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -27,7 +27,7 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam12.h> -#define MCI_STATUS 0x401 +#define MC0_STATUS 0x401 static void model_12_init(struct device *dev) { @@ -55,7 +55,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 5; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); } enable_cache(); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 1271a4e..257f81f 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -28,7 +28,7 @@ #include <arch/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h> -#define MCI_STATUS 0x401 +#define MC0_STATUS 0x401 static void model_14_init(struct device *dev) { @@ -78,7 +78,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); } /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 32dcd7b..1e0375f 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -75,7 +75,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); } /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 73d91e7..9909793 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -73,7 +73,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); } /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 562a267..61eb813 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -32,7 +32,7 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/msr.h> -#define MCI_STATUS 0x401 +#define MC0_STATUS 0x401 static inline uint8_t is_gt_rev_d(void) { @@ -112,7 +112,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 5; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); } enable_cache(); diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 212d705..592ca4f 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -72,7 +72,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 941c48f..24c2aea 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -84,7 +84,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 747cb2e..b9e0185 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -69,7 +69,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < 6; i++) - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); /* Enable the local CPU APICs */ diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 008d5da..c28ec13 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -16,7 +16,7 @@ #ifndef CPU_AMD_FAM15_H #define CPU_AMD_FAM15_H -#define MCI_STATUS 0x00000401 +#define MC0_STATUS 0x00000401 #define MSR_SMM_BASE 0xC0010111 #define MSR_TSEG_BASE 0xC0010112 #define MSR_SMM_MASK 0xC0010113 diff --git a/src/include/cpu/amd/amdfam16.h b/src/include/cpu/amd/amdfam16.h index 861e518..8d8be83 100644 --- a/src/include/cpu/amd/amdfam16.h +++ b/src/include/cpu/amd/amdfam16.h @@ -16,7 +16,7 @@ #ifndef CPU_AMD_FAM16_H #define CPU_AMD_FAM16_H -#define MCI_STATUS 0x00000401 +#define MC0_STATUS 0x00000401 #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 4dd371c..6289174 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -126,7 +126,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0 ; i < 6 ; i++) - wrmsr(MCI_STATUS + (i * 4), msr); + wrmsr(MC0_STATUS + (i * 4), msr); setup_lapic(); } -- To view, visit https://review.coreboot.org/27922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0 Gerrit-Change-Number: 27922 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit August 2018