coreboot-gerrit August 2018

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Change in coreboot[master]: rk3288: Dig up two more KB of SRAM from under the couch cushions
by Julius Werner (Code Review) 07 Aug '18

07 Aug '18

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/27950 to review the following change. Change subject: rk3288: Dig up two more KB of SRAM from under the couch cushions ...................................................................... rk3288: Dig up two more KB of SRAM from under the couch cushions RK3288 has always been notoriously low on SRAM, to the point where its boards have less than 100 bytes left in both their bootblock/verstage sections. This becomes a problem every time we try to add a tiny amount of code to common coreboot interfaces that are included in them. This patch manages to add another KB to each, one from the CBMEM console (which now might get cut off a bit, but that's life) and one by moving the TTB_SUBTABLES to PMUSRAM. PMUSRAM is a weird world where write accesses must always be exactly 4 bytes long or they hang the CPU, so we mostly ignore it... but thankfully, page table entries are exactly 4 bytes long and that's the only thing we write to this region, so it works out in this case. Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/rockchip/rk3288/include/soc/memlayout.ld 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27950/1 diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index daff503..fc3758b 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -30,11 +30,10 @@ SRAM_START(0xFF700000) TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 19K - 4) - PRERAM_CBMEM_CONSOLE(0xFF708C00, 4K) + BOOTBLOCK(0xFF704004, 20K - 4) + PRERAM_CBMEM_CONSOLE(0xFF709000, 3K) VBOOT2_WORK(0xFF709C00, 12K) - OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 40K) - TTB_SUBTABLES(0xFF716C00, 1K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K) PRERAM_CBFS_CACHE(0xFF717000, 1K) TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) @@ -43,6 +42,7 @@ /* 4K of special SRAM in PMU power domain. * Careful: only supports 32-bit wide write accesses! */ SYMBOL(pmu_sram, 0xFF720000) + TTB_SUBTABLES(0xFF720800, 1K) WATCHDOG_TOMBSTONE(0xFF720FFC, 4) SYMBOL(epmu_sram, 0xFF721000) } -- To view, visit https://review.coreboot.org/27950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f Gerrit-Change-Number: 27950 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: src/device/pci_rom.c: Remove double initialization
by Richard Spiegel (Code Review) 07 Aug '18

07 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27949 Change subject: src/device/pci_rom.c: Remove double initialization ...................................................................... src/device/pci_rom.c: Remove double initialization In procedure pci_rom_probe(), variable vendev is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a71aa1aea2047ab2d98e09d1d6610de552b6cb4 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/device/pci_rom.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27949/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 35d3d69..517fb33 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -41,7 +41,7 @@ rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); u32 vendev = (dev->vendor << 16) | dev->device; - u32 mapped_vendev = vendev; + u32 mapped_vendev; mapped_vendev = map_oprom_vendev(vendev); -- To view, visit https://review.coreboot.org/27949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8a71aa1aea2047ab2d98e09d1d6610de552b6cb4 Gerrit-Change-Number: 27949 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: arch/x86/exception.c: Remove double initialization
by Martin Roth (Code Review) 07 Aug '18

07 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27948 ) Change subject: arch/x86/exception.c: Remove double initialization ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Gerrit-Change-Number: 27948 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 07 Aug 2018 21:37:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/exception.c: Remove double initialization
by Richard Spiegel (Code Review) 07 Aug '18

07 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27948 Change subject: arch/x86/exception.c: Remove double initialization ...................................................................... arch/x86/exception.c: Remove double initialization In procedure exception_init(), structure pointer gates is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/arch/x86/exception.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27948/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f668ffc..201e835 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -622,7 +622,7 @@ { int i; uint16_t segment; - struct intr_gate *gates = car_get_var_ptr(idt); + struct intr_gate *gates; segment = get_cs(); gates = car_get_var_ptr(idt); -- To view, visit https://review.coreboot.org/27948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Gerrit-Change-Number: 27948 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: cpu/amd: Correct number of MCA banks cleared
by Marshall Dawson (Code Review) 07 Aug '18

07 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27923 to look at the new patch set (#3). Change subject: cpu/amd: Correct number of MCA banks cleared ...................................................................... cpu/amd: Correct number of MCA banks cleared Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/amd/agesa/family12/model_12_init.c M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/include/cpu/amd/amdfam15.h M src/include/cpu/amd/amdfam16.h M src/northbridge/amd/amdmct/amddefs.h M src/soc/amd/stoneyridge/cpu.c 12 files changed, 45 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27923/3 -- To view, visit https://review.coreboot.org/27923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Gerrit-Change-Number: 27923 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/bincfg: don't use sym_table shared variable
by Denis 'GNUtoo' Carikli (Code Review) 07 Aug '18

07 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27810 to look at the new patch set (#2). Change subject: util/bincfg: don't use sym_table shared variable ...................................................................... util/bincfg: don't use sym_table shared variable Change-Id: I652a8da75498f871a53eb7509f6145c4842e3373 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- M util/bincfg/bincfg.h M util/bincfg/bincfg.y 2 files changed, 82 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27810/2 -- To view, visit https://review.coreboot.org/27810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I652a8da75498f871a53eb7509f6145c4842e3373 Gerrit-Change-Number: 27810 Gerrit-PatchSet: 2 Gerrit-Owner: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arm64: Turn architectural register accessors into inline functions
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27881 ) Change subject: arm64: Turn architectural register accessors into inline functions ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27881/3/src/arch/arm64/include/armv8/arch/l… File src/arch/arm64/include/armv8/arch/lib_helpers.h: https://review.coreboot.org/#/c/27881/3/src/arch/arm64/include/armv8/arch/l… PS3, Line 162: #define MAKE_REGISTER_ACCESSORS_EL123(reg) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/27881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63 Gerrit-Change-Number: 27881 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 21:07:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arm64: Remove set_cntfrq() function
by Julius Werner (Code Review) 07 Aug '18

07 Aug '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/27947 Change subject: arm64: Remove set_cntfrq() function ...................................................................... arm64: Remove set_cntfrq() function CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of others that are all accessed through the raw_(read|write)_${register}() family of functions. There's no reason why this register in particular should have an inconsistent accessor, so replace all instances of set_cntfrq() with raw_write_cntfrq_el0() and get rid of it. Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/armv8/lib/Makefile.inc D src/arch/arm64/armv8/lib/clock.c D src/arch/arm64/include/arch/clock.h M src/soc/cavium/cn81xx/timer.c M src/soc/nvidia/tegra210/ramstage.c 5 files changed, 5 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27947/1 diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index bfc87c3..8fc44de 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -15,7 +15,7 @@ ## ################################################################################ -lib_access = pstate.c sysctrl.c cache.c tlb.c clock.c +lib_access = pstate.c sysctrl.c cache.c tlb.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) decompressor-y += $(lib_access) diff --git a/src/arch/arm64/armv8/lib/clock.c b/src/arch/arm64/armv8/lib/clock.c deleted file mode 100644 index f15adf4..0000000 --- a/src/arch/arm64/armv8/lib/clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * clock.c: Functions for accessing clock and timer related registers - * Reference: ARM Architecture Reference Manual, ARMv8-A edition - */ - -#include <stdint.h> - -#include <arch/clock.h> - -void set_cntfrq(uint32_t freq) -{ - __asm__ __volatile__("msr cntfrq_el0, %0" :: "r"((uint64_t)freq)); -} diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h deleted file mode 100644 index 77d09d8..0000000 --- a/src/arch/arm64/include/arch/clock.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARM_CLOCK_H_ -#define __ARM_CLOCK_H_ - -#include <types.h> - -void set_cntfrq(uint32_t); - -#endif /* __ARM_CLOCK_H_ */ diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index b1c2285..f2a870a 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -17,6 +17,7 @@ */ #include <arch/io.h> +#include <arch/lib_helpers.h> #include <console/console.h> #include <inttypes.h> #include <soc/clock.h> @@ -25,7 +26,6 @@ #include <timer.h> #include <soc/addressmap.h> #include <assert.h> -#include <arch/clock.h> /* Global System Timers Unit (GTI) registers */ struct cn81xx_timer { @@ -131,7 +131,7 @@ void soc_timer_init(void) { - set_cntfrq(tickrate); + raw_write_cntfrq_el0(tickrate); } /** diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 18fdded..86fae67 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#include <arch/clock.h> #include <arch/cpu.h> +#include <arch/lib_helpers.h> #include <arch/stages.h> #include <gic.h> #include <soc/addressmap.h> @@ -26,7 +26,7 @@ { uint32_t freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. - set_cntfrq(freq); + raw_write_cntfrq_el0(freq); } static void mselect_enable_wrap(void) -- To view, visit https://review.coreboot.org/27947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Gerrit-Change-Number: 27947 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: mb/biostar/am1ml: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/27934 ) Change subject: mb/biostar/am1ml: Use common pnp_{enter,exit} functions ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/27934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I73b8811767da1b0356cffb6a26553400b2f10841 Gerrit-Change-Number: 27934 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/biostar/am1ml: Use common pnp_{enter, exit} functions
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27934 to look at the new patch set (#4). Change subject: mb/biostar/am1ml: Use common pnp_{enter,exit} functions ...................................................................... mb/biostar/am1ml: Use common pnp_{enter,exit} functions Change-Id: I73b8811767da1b0356cffb6a26553400b2f10841 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/biostar/am1ml/romstage.c M src/superio/ite/common/ite.h 2 files changed, 29 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/27934/4 -- To view, visit https://review.coreboot.org/27934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I73b8811767da1b0356cffb6a26553400b2f10841 Gerrit-Change-Number: 27934 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2018