coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size
by Arthur Heymans (Code Review) 07 Aug '18

07 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27870 ) Change subject: cpu/intel/smm: Make sure SMRR base is aligned to SMRR size ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27870/2/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27870/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 180: BIOS_WARNING > warning or error? looking at the description of both, it feels like BIOS_WARNING is better since it is expected to still work if SMRR is not set. Not sure to what extend TSEG is accessible accessible with SMRR being set, so it is a security issue at most. -- To view, visit https://review.coreboot.org/27870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48f55cdac5f4b16b9a8d7a8ef3a84918e756e315 Gerrit-Change-Number: 27870 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 13:25:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Update gpio table for Coffeelake U RVP
by Arthur Heymans (Code Review) 07 Aug '18

07 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27907 ) Change subject: mb/intel/coffeelake_rvp: Update gpio table for Coffeelake U RVP ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/27907/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/27907/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 20: CONFIG_BOARD_INTEL_COFFEELAKE_RVPU what about RVP11? https://review.coreboot.org/#/c/27907/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 292: __attribute__((weak)) please don't do this. -- To view, visit https://review.coreboot.org/27907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d Gerrit-Change-Number: 27907 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 07 Aug 2018 12:54:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP
by Arthur Heymans (Code Review) 07 Aug '18

07 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27904 ) Change subject: mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP ...................................................................... Patch Set 1: (7 comments) https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/Kconfig: https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 14: select UART_DEBUG please add select INTEL_GMA_HAVE_VBT and add the respective data.vbt files in the variant dirs. https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 66: config ME_BIN_PATH : string : depends on HAVE_ME_BIN : default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.bin" : : config EC_BIN_PATH : string : depends on HAVE_EC_BIN : default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" This should be put somewhere else. Could you reuse southbridge/intel/common/firmware/Kconfig for this? https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/dsdt.asl: https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 41: shift this and the #endif left https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/smihandler.c: https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 27: case 0x99: : printk(BIOS_DEBUG, "Sample\n"); : smm_get_gnvs()->smif = 0; : break; Remove? https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb: https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 98: #if IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) Would be cleaner to shift this left IMO. https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 171: device pci 1f.3 on I think you'll also want this in the devicetree on an #else path for the preprocessor condition. https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/gpio.h: https://review.coreboot.org/#/c/27904/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 1: /* all these gpio.h files seem quite superfluous. Are they really needed? -- To view, visit https://review.coreboot.org/27904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7 Gerrit-Change-Number: 27904 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 07 Aug 2018 12:24:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U
by Arthur Heymans (Code Review) 07 Aug '18

07 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27905 ) Change subject: mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27905/1/src/mainboard/intel/coffeelake_rvp/… File src/mainboard/intel/coffeelake_rvp/Kconfig: https://review.coreboot.org/#/c/27905/1/src/mainboard/intel/coffeelake_rvp/… PS1, Line 6: BOARD_ROMSIZE_KB_32768 make sure the default for "config FMDFILE" points to the new 32M fmd file. (e.g. https://review.coreboot.org/#/c/coreboot/+/25084/15/src/mainboard/opencellu…) -- To view, visit https://review.coreboot.org/27905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc Gerrit-Change-Number: 27905 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 07 Aug 2018 11:54:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/mainboard: Fix typo
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27912 ) Change subject: src/mainboard: Fix typo ...................................................................... Patch Set 2: (32 comments) https://review.coreboot.org/#/c/27912/2/src/mainboard/advansus/a785e-i/reso… File src/mainboard/advansus/a785e-i/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/advansus/a785e-i/reso… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/bimini_fam10/reso… File src/mainboard/amd/bimini_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/bimini_fam10/reso… PS2, Line 123: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/mahogany_fam10/re… File src/mainboard/amd/mahogany_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/mahogany_fam10/re… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/south_station/mai… File src/mainboard/amd/south_station/mainboard.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/south_station/mai… PS2, Line 21: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/tilapia_fam10/res… File src/mainboard/amd/tilapia_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/tilapia_fam10/res… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/torpedo/gpio.h File src/mainboard/amd/torpedo/gpio.h: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/torpedo/gpio.h@301 PS2, Line 301: #define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/torpedo/gpio.h@302 PS2, Line 302: #define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/union_station/mai… File src/mainboard/amd/union_station/mainboard.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/amd/union_station/mai… PS2, Line 20: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kcma-d8/resource… File src/mainboard/asus/kcma-d8/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kcma-d8/resource… PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kcma-d8/resource… PS2, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kfsn4-dre/resour… File src/mainboard/asus/kfsn4-dre/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kfsn4-dre/resour… PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kgpe-d16/resourc… File src/mainboard/asus/kgpe-d16/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kgpe-d16/resourc… PS2, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/kgpe-d16/resourc… PS2, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/m4a78-em/resourc… File src/mainboard/asus/m4a78-em/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/m4a78-em/resourc… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/m4a785-m/resourc… File src/mainboard/asus/m4a785-m/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/m4a785-m/resourc… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/m5a88-v/resource… File src/mainboard/asus/m5a88-v/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/asus/m5a88-v/resource… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/avalue/eax-785e/resou… File src/mainboard/avalue/eax-785e/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/avalue/eax-785e/resou… PS2, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/gigabyte/ma785gm/reso… File src/mainboard/gigabyte/ma785gm/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/gigabyte/ma785gm/reso… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/gigabyte/ma785gmt/res… File src/mainboard/gigabyte/ma785gmt/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/gigabyte/ma785gmt/res… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/gigabyte/ma78gm/resou… File src/mainboard/gigabyte/ma78gm/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/gigabyte/ma78gm/resou… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/iei/kino-780am2-fam10… File src/mainboard/iei/kino-780am2-fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/iei/kino-780am2-fam10… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/intel/glkrvp/variants… File src/mainboard/intel/glkrvp/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/intel/glkrvp/variants… PS2, Line 57: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Output/ISH_GPIO_3*/ line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/jetway/pa78vm5/resour… File src/mainboard/jetway/pa78vm5/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/jetway/pa78vm5/resour… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/msi/ms9652_fam10/reso… File src/mainboard/msi/ms9652_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/msi/ms9652_fam10/reso… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/siemens/mc_tcu3/ptn34… File src/mainboard/siemens/mc_tcu3/ptn3460.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 117: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 143: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 171: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/supermicro/h8dmr_fam1… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/supermicro/h8qme_fam1… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/supermicro/h8scm_fam1… File src/mainboard/supermicro/h8scm_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/supermicro/h8scm_fam1… PS2, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/2/src/mainboard/tyan/s2912_fam10/reso… File src/mainboard/tyan/s2912_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/2/src/mainboard/tyan/s2912_fam10/reso… PS2, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters -- To view, visit https://review.coreboot.org/27912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Gerrit-Change-Number: 27912 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 10:55:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/mainboard: Fix typo
by Elyes HAOUAS (Code Review) 07 Aug '18

07 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27912 to look at the new patch set (#2). Change subject: src/mainboard: Fix typo ...................................................................... src/mainboard: Fix typo Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/resourcemap.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/bimini_fam10/resourcemap.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/resourcemap.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/tilapia_fam10/resourcemap.c M src/mainboard/amd/torpedo/gpio.h M src/mainboard/amd/torpedo/platform_cfg.h M src/mainboard/amd/union_station/mainboard.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kfsn4-dre/resourcemap.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/resourcemap.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/resourcemap.c M src/mainboard/asus/m5a88-v/resourcemap.c M src/mainboard/avalue/eax-785e/resourcemap.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/gigabyte/ma785gm/resourcemap.c M src/mainboard/gigabyte/ma785gmt/resourcemap.c M src/mainboard/gigabyte/ma78gm/resourcemap.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/urara/urara_boardid.h M src/mainboard/iei/kino-780am2-fam10/resourcemap.c M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/resourcemap.c M src/mainboard/msi/ms9652_fam10/resourcemap.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/pcengines/apu2/mptable.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.h M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c M src/mainboard/supermicro/h8qme_fam10/resourcemap.c M src/mainboard/supermicro/h8scm_fam10/resourcemap.c M src/mainboard/tyan/s2912_fam10/resourcemap.c 51 files changed, 62 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27912/2 -- To view, visit https://review.coreboot.org/27912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Gerrit-Change-Number: 27912 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/arch/arm/armv7: Fix typo
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27920 ) Change subject: src/arch/arm/armv7: Fix typo ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27920/1/src/commonlib/include/commonlib/tim… File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/#/c/27920/1/src/commonlib/include/commonlib/tim… PS1, Line 243: { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgment of raminit"}, line over 80 characters -- To view, visit https://review.coreboot.org/27920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5838fdef41a2d84c3ec0ba4d9b2de5058530a2b9 Gerrit-Change-Number: 27920 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 10:28:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/northbridge: Fix typo
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27911 ) Change subject: src/northbridge: Fix typo ...................................................................... Patch Set 1: (7 comments) https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam… File src/northbridge/amd/amdfam10/amdfam10.h: https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam… PS1, Line 371: for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs line over 80 characters https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam… PS1, Line 372: for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 line over 80 characters https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdfam10/amdfam… PS1, Line 373: F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 line over 80 characters https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ffeat.h File src/northbridge/amd/amdht/h3ffeat.h: https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ffeat.h… PS1, Line 160: /* The number of coherent links coming off of each node (i.e. the 'Degree' of the node) */ line over 80 characters https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c: https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdht/h3ncmn.c@… PS1, Line 1119: * InitComplete = 1,Link initialization is complete line over 80 characters https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/mct_ddr3… PS1, Line 849: /* Restore DRAM Address/Timing Control Register */ line over 80 characters https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/wrappers… File src/northbridge/amd/amdmct/wrappers/mcti_d.c: https://review.coreboot.org/#/c/27911/1/src/northbridge/amd/amdmct/wrappers… PS1, Line 172: //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ line over 80 characters -- To view, visit https://review.coreboot.org/27911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I00094028036f33892362b935899e1bceef1da625 Gerrit-Change-Number: 27911 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 10:27:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/mainboard: Fix typo
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27912 ) Change subject: src/mainboard: Fix typo ...................................................................... Patch Set 1: (31 comments) https://review.coreboot.org/#/c/27912/1/src/mainboard/advansus/a785e-i/reso… File src/mainboard/advansus/a785e-i/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/advansus/a785e-i/reso… PS1, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/bimini_fam10/reso… File src/mainboard/amd/bimini_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/bimini_fam10/reso… PS1, Line 123: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/mahogany_fam10/re… File src/mainboard/amd/mahogany_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/mahogany_fam10/re… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/south_station/mai… File src/mainboard/amd/south_station/mainboard.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/south_station/mai… PS1, Line 21: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/tilapia_fam10/res… File src/mainboard/amd/tilapia_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/tilapia_fam10/res… PS1, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/torpedo/gpio.h File src/mainboard/amd/torpedo/gpio.h: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/torpedo/gpio.h@301 PS1, Line 301: #define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/torpedo/gpio.h@302 PS1, Line 302: #define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/union_station/mai… File src/mainboard/amd/union_station/mainboard.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/amd/union_station/mai… PS1, Line 20: #include "SBPLATFORM.h" /* Platform Specific Definitions */ please, no space before tabs https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kcma-d8/resource… File src/mainboard/asus/kcma-d8/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kcma-d8/resource… PS1, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kcma-d8/resource… PS1, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kfsn4-dre/resour… File src/mainboard/asus/kfsn4-dre/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kfsn4-dre/resour… PS1, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kgpe-d16/resourc… File src/mainboard/asus/kgpe-d16/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kgpe-d16/resourc… PS1, Line 127: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/kgpe-d16/resourc… PS1, Line 382: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/m4a78-em/resourc… File src/mainboard/asus/m4a78-em/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/m4a78-em/resourc… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/m4a785-m/resourc… File src/mainboard/asus/m4a785-m/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/m4a785-m/resourc… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/m5a88-v/resource… File src/mainboard/asus/m5a88-v/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/asus/m5a88-v/resource… PS1, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/avalue/eax-785e/resou… File src/mainboard/avalue/eax-785e/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/avalue/eax-785e/resou… PS1, Line 122: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/gigabyte/ma785gm/reso… File src/mainboard/gigabyte/ma785gm/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/gigabyte/ma785gm/reso… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/gigabyte/ma785gmt/res… File src/mainboard/gigabyte/ma785gmt/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/gigabyte/ma785gmt/res… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/gigabyte/ma78gm/resou… File src/mainboard/gigabyte/ma78gm/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/gigabyte/ma78gm/resou… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/iei/kino-780am2-fam10… File src/mainboard/iei/kino-780am2-fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/iei/kino-780am2-fam10… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/jetway/pa78vm5/resour… File src/mainboard/jetway/pa78vm5/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/jetway/pa78vm5/resour… PS1, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/msi/ms9652_fam10/reso… File src/mainboard/msi/ms9652_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/msi/ms9652_fam10/reso… PS1, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/siemens/mc_tcu3/ptn34… File src/mainboard/siemens/mc_tcu3/ptn3460.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/siemens/mc_tcu3/ptn34… PS1, Line 117: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/siemens/mc_tcu3/ptn34… PS1, Line 143: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5, line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/siemens/mc_tcu3/ptn34… PS1, Line 171: status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4, line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/supermicro/h8dmr_fam1… PS1, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/supermicro/h8qme_fam1… PS1, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/supermicro/h8scm_fam1… File src/mainboard/supermicro/h8scm_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/supermicro/h8scm_fam1… PS1, Line 124: * This field defines the upp address bits of a 40-bit address that line over 80 characters https://review.coreboot.org/#/c/27912/1/src/mainboard/tyan/s2912_fam10/reso… File src/mainboard/tyan/s2912_fam10/resourcemap.c: https://review.coreboot.org/#/c/27912/1/src/mainboard/tyan/s2912_fam10/reso… PS1, Line 125: * This field defines the upp address bits of a 40-bit address that line over 80 characters -- To view, visit https://review.coreboot.org/27912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Gerrit-Change-Number: 27912 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 10:27:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src/superio: Fix typo
by build bot (Jenkins) (Code Review) 07 Aug '18

07 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27875 ) Change subject: src/superio: Fix typo ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27875/3/src/superio/smsc/sio1036/sio1036_ea… File src/superio/smsc/sio1036/sio1036_early_init.c: https://review.coreboot.org/#/c/27875/3/src/superio/smsc/sio1036/sio1036_ea… PS3, Line 76: pnp_write_config (dev, 0x0A, 0x00 | IR_OUTPUT_MUX); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/27875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Gerrit-Change-Number: 27875 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Aug 2018 10:27:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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