coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/octopus: Use correct chip for CNVi device
by Furquan Shaikh (Code Review) 09 Aug '18

09 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27968 Change subject: mb/google/octopus: Use correct chip for CNVi device ...................................................................... mb/google/octopus: Use correct chip for CNVi device This change uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows up in ACPI node 2. It is possible to pass any parameters from devicetree to wifi driver for SSDT generation. BUG=b:112371978 Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27968/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index b7c7ad2..1a6dac9 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -112,7 +112,9 @@ device pci 00.2 off end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Iunit - device pci 0c.0 on end # - CNVi + chip drivers/intel/wifi + device pci 0c.0 on end # - CNVi + end device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - Fast SPI -- To view, visit https://review.coreboot.org/27968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0 Gerrit-Change-Number: 27968 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: lib: Add blob_provider
by Philipp Deppenwiese (Code Review) 09 Aug '18

09 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/24992 ) Change subject: lib: Add blob_provider ...................................................................... Patch Set 15: Done, should now be cleaner -- To view, visit https://review.coreboot.org/24992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30abc5be5d47a4c697c0b94babb068b0f0ae4794 Gerrit-Change-Number: 24992 Gerrit-PatchSet: 15 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Aug 2018 01:43:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: lib: Add blob_provider functionality
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24992 ) Change subject: lib: Add blob_provider functionality ...................................................................... Patch Set 11: (30 comments) https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h File src/include/blob_provider.h: https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@32 PS11, Line 32: ID_ACPI_SLIC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@33 PS11, Line 33: ID_ACPI_DSDT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@34 PS11, Line 34: ID_ACPI_SSDT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@35 PS11, Line 35: ID_MICROCODE, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@36 PS11, Line 36: ID_MICROCODE_RMU, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@37 PS11, Line 37: ID_MRC_CACHE, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@38 PS11, Line 38: ID_VGA_VBT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@39 PS11, Line 39: ID_NVRAM_CMOS_LAYOUT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@40 PS11, Line 40: ID_NVRAM_CMOS_DEFAULT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@41 PS11, Line 41: ID_NVRAM_VPD, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@42 PS11, Line 42: ID_SPD, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@43 PS11, Line 43: ID_MAC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@44 PS11, Line 44: ID_AMD_S3NV, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@45 PS11, Line 45: ID_MRC_CACHE_RW_REGION, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@46 PS11, Line 46: ID_NVRAM_VPD_RO_REGION, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@47 PS11, Line 47: ID_AMD_AGESA, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@48 PS11, Line 48: ID_AMD_AGESA_PRE_MEM, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@49 PS11, Line 49: ID_AMD_AGESA_POST_MEM, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@50 PS11, Line 50: ID_AMD_PSP, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@51 PS11, Line 51: ID_INTEL_MRC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@52 PS11, Line 52: ID_INTEL_FSP_S, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@53 PS11, Line 53: ID_INTEL_FSP_M, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@54 PS11, Line 54: ID_INTEL_MMA, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@55 PS11, Line 55: ID_NVIDIA_MTC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@56 PS11, Line 56: ID_QUALCOMM_CDT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@57 PS11, Line 57: ID_QUALCOMM_DDR, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@58 PS11, Line 58: ID_QUALCOMM_TZ, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/include/blob_provider.h@59 PS11, Line 59: ID_QUALCOMM_RPM, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/11/src/lib/blob_provider.c File src/lib/blob_provider.c: https://review.coreboot.org/#/c/24992/11/src/lib/blob_provider.c@71 PS11, Line 71: if (lookup_rdev(locator, &data) < 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/24992/11/src/lib/blob_provider.c@84 PS11, Line 84: if (lookup_rdev(locator, data) < 0) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/24992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30abc5be5d47a4c697c0b94babb068b0f0ae4794 Gerrit-Change-Number: 24992 Gerrit-PatchSet: 11 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Aug 2018 01:26:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: lib: Add blob_provider functionality
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24992 ) Change subject: lib: Add blob_provider functionality ...................................................................... Patch Set 10: (30 comments) https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h File src/include/blob_provider.h: https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@32 PS10, Line 32: ID_ACPI_SLIC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@33 PS10, Line 33: ID_ACPI_DSDT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@34 PS10, Line 34: ID_ACPI_SSDT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@35 PS10, Line 35: ID_MICROCODE, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@36 PS10, Line 36: ID_MICROCODE_RMU, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@37 PS10, Line 37: ID_MRC_CACHE, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@38 PS10, Line 38: ID_VGA_VBT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@39 PS10, Line 39: ID_NVRAM_CMOS_LAYOUT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@40 PS10, Line 40: ID_NVRAM_CMOS_DEFAULT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@41 PS10, Line 41: ID_NVRAM_VPD, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@42 PS10, Line 42: ID_SPD, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@43 PS10, Line 43: ID_MAC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@44 PS10, Line 44: ID_AMD_S3NV, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@45 PS10, Line 45: ID_MRC_CACHE_RW_REGION, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@46 PS10, Line 46: ID_NVRAM_VPD_RO_REGION, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@47 PS10, Line 47: ID_AMD_AGESA, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@48 PS10, Line 48: ID_AMD_AGESA_PRE_MEM, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@49 PS10, Line 49: ID_AMD_AGESA_POST_MEM, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@50 PS10, Line 50: ID_AMD_PSP, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@51 PS10, Line 51: ID_INTEL_MRC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@52 PS10, Line 52: ID_INTEL_FSP_S, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@53 PS10, Line 53: ID_INTEL_FSP_M, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@54 PS10, Line 54: ID_INTEL_MMA, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@55 PS10, Line 55: ID_NVIDIA_MTC, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@56 PS10, Line 56: ID_QUALCOMM_CDT, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@57 PS10, Line 57: ID_QUALCOMM_DDR, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@58 PS10, Line 58: ID_QUALCOMM_TZ, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/include/blob_provider.h@59 PS10, Line 59: ID_QUALCOMM_RPM, please, no spaces at the start of a line https://review.coreboot.org/#/c/24992/10/src/lib/blob_provider.c File src/lib/blob_provider.c: https://review.coreboot.org/#/c/24992/10/src/lib/blob_provider.c@71 PS10, Line 71: if (lookup_rdev(locator, &data) < 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/24992/10/src/lib/blob_provider.c@84 PS10, Line 84: if (lookup_rdev(locator, data) < 0) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/24992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30abc5be5d47a4c697c0b94babb068b0f0ae4794 Gerrit-Change-Number: 24992 Gerrit-PatchSet: 10 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Aug 2018 01:21:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: security/tpm: Fix coding style and uninitialized variable
by Philipp Deppenwiese (Code Review) 09 Aug '18

09 Aug '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/22734 ) Change subject: security/tpm: Fix coding style and uninitialized variable ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/22734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ifa93c91aab97c663df66dfdc4d1afb3a43736adb Gerrit-Change-Number: 22734 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/tpm: Implement hashing function in TSS
by Philipp Deppenwiese (Code Review) 09 Aug '18

09 Aug '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/22735 ) Change subject: security/tpm: Implement hashing function in TSS ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/22735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ib84513e8cbfe1ef11f495b873de0331178915c59 Gerrit-Change-Number: 22735 Gerrit-PatchSet: 26 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Enable GbE support
by Lijian Zhao (Code Review) 08 Aug '18

08 Aug '18

Hello Pratikkumar V Prajapati, Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27848 to look at the new patch set (#6). Change subject: mb/intel/coffeelake_rvp: Enable GbE support ...................................................................... mb/intel/coffeelake_rvp: Enable GbE support Enable Gigabit Ethernet network controller on whiskey lake rvp platform, add NVM bin file as well. Also include a cosmetic changes, SMBUS on function 4 but not function 3. BUG=N/A TEST=Build and boot up into chromeos on whiskey lake rvp platform, and check eth0 can get IP address assigned, Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb A src/soc/intel/cannonlake/acpi/pch_glan.asl M src/soc/intel/cannonlake/acpi/southbridge.asl 4 files changed, 40 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27848/6 -- To view, visit https://review.coreboot.org/27848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Gerrit-Change-Number: 27848 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus: Enable SAR config for Intel 9560 module
by John Zhao (Code Review) 08 Aug '18

08 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27966 to look at the new patch set (#2). Change subject: mb/google/octopus: Enable SAR config for Intel 9560 module ...................................................................... mb/google/octopus: Enable SAR config for Intel 9560 module Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key. coreboot reads the VPD and creates the ACPI table as per the WGDS spec. BUG=b:112288077 TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry. Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27966/2 -- To view, visit https://review.coreboot.org/27966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4 Gerrit-Change-Number: 27966 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Enable GbE support
by Lijian Zhao (Code Review) 08 Aug '18

08 Aug '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/27848 ) Change subject: mb/intel/coffeelake_rvp: Enable GbE support ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/27848/4/src/soc/intel/cannonlake/acpi/pch_g… File src/soc/intel/cannonlake/acpi/pch_glan.asl: https://review.coreboot.org/#/c/27848/4/src/soc/intel/cannonlake/acpi/pch_g… PS4, Line 18: // Intel Gigabit Ethernet Controller 0:1f.6 > /* comment */ ? Done https://review.coreboot.org/#/c/27848/4/src/soc/intel/cannonlake/acpi/south… File src/soc/intel/cannonlake/acpi/southbridge.asl: https://review.coreboot.org/#/c/27848/4/src/soc/intel/cannonlake/acpi/south… PS4, Line 4: * Copyright (C) 2017 Intel Corp. > 2017-2018 Done -- To view, visit https://review.coreboot.org/27848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Gerrit-Change-Number: 27848 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 08 Aug 2018 23:54:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: security/tpm: Report tpm_unmarshal_response warning
by Philipp Deppenwiese (Code Review) 08 Aug '18

08 Aug '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27931 ) Change subject: security/tpm: Report tpm_unmarshal_response warning ...................................................................... security/tpm: Report tpm_unmarshal_response warning In procedure tpm_unmarshal_response(), variable "rc" is used early to decide if it should return NULL. Later however, the code proceeds to its end even if one subroutine reports error. If "rc" is not 0, report that there was a partial error in the procedure. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7575bc75104fd97f138224aa57561e68f6548e58 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Reviewed-on: https://review.coreboot.org/27931 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved Marshall Dawson: Looks good to me, but someone else must approve diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 86f2231..94bfbcf 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -554,6 +554,9 @@ command, ibuf_remaining(ib)); return NULL; } + if (rc) + printk(BIOS_WARNING, "Warning: %s had one or more failures.\n", + __func__); /* The entire message have been parsed. */ return tpm2_resp; -- To view, visit https://review.coreboot.org/27931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I7575bc75104fd97f138224aa57561e68f6548e58 Gerrit-Change-Number: 27931 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit August 2018