coreboot-gerrit August 2018

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 3: (5 comments) https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@176 PS3, Line 176: int regnum = ((insn >> match->reg_shift) & match->reg_mask) + match->reg_addition; line over 80 characters https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@184 PS3, Line 184: buff.b[i] = mprv_read_u8((uint8_t *)(tf->badvaddr + i)); line over 80 characters https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@237 PS3, Line 237: /* writing to memory by bytes prevents misaligned memory access */ line over 80 characters https://review.coreboot.org/#/c/27972/3/src/arch/riscv/misaligend.c@239 PS3, Line 239: mprv_write_u8((uint8_t *)(tf->badvaddr + i), buff.b[i]); line over 80 characters https://review.coreboot.org/#/c/27972/3/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c: https://review.coreboot.org/#/c/27972/3/src/arch/riscv/trap_handler.c@191 PS3, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'? -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 08:24:48 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek: Map SRAM as secure and cached memory
by Tristan Hsieh (Code Review) 09 Aug '18

09 Aug '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27974 Change subject: mediatek: Map SRAM as secure and cached memory ...................................................................... mediatek: Map SRAM as secure and cached memory This patch changes the mapping of SRAM from non-secure to secure. Without this patch, mmu_config_range() can not work when MMU is enabled. The new config is still in non-secure cache since TTB section is allocated in SRAM which is mapped as non-secure. BUG=b:80501386 TEST=Boots correctly on Kukui Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/mmu_operations.h M src/soc/mediatek/common/mmu_operations.c 2 files changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27974/1 diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h index b081690..79c3ea0 100644 --- a/src/soc/mediatek/common/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -19,10 +19,11 @@ #include <arch/mmu.h> enum { - DEV_MEM = MA_DEV | MA_S | MA_RW, - CACHED_MEM = MA_MEM | MA_NS | MA_RW, - SECURE_MEM = MA_MEM | MA_S | MA_RW, - UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, + DEV_MEM = MA_DEV | MA_S | MA_RW, + SECURE_CACHED_MEM = MA_MEM | MA_S | MA_RW, + SECURE_UNCACHED_MEM = MA_MEM | MA_S | MA_RW | MA_MEM_NC, + NONSECURE_CACHED_MEM = MA_MEM | MA_NS | MA_RW, + NONSECURE_UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, }; extern unsigned char _sram_l2c[]; diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index b991084..78a1a44 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -26,16 +26,17 @@ mmu_init(); /* Set 0x0 to the end of 2GB dram address as device memory */ - mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); + mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM); /* SRAM is cached */ - mmu_config_range(_sram, _sram_size, CACHED_MEM); + mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM); /* L2C SRAM is cached */ - mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM); + mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM); /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ - mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + mmu_config_range(_dma_coherent, _dma_coherent_size, + SECURE_UNCACHED_MEM); mmu_enable(); } @@ -43,7 +44,7 @@ void mtk_mmu_after_dram(void) { /* Map DRAM as cached now that it's up and running */ - mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); + mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM); mtk_soc_after_dram(); } -- To view, visit https://review.coreboot.org/27974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6 Gerrit-Change-Number: 27974 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by Xiang Wang (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27972 to look at the new patch set (#3). Change subject: riscv: update misaligned memory access exception handling ...................................................................... riscv: update misaligned memory access exception handling Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. fix DEFINE_MPRV_READ to support that reading the page which is executable-only (R=0 X=1). Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/fp_asm.S M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/vm.h A src/arch/riscv/misaligend.c M src/arch/riscv/trap_handler.c 6 files changed, 613 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/3 -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by Xiang Wang (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27972 to look at the new patch set (#2). Change subject: riscv: update misaligned memory access exception handling ...................................................................... riscv: update misaligned memory access exception handling Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. fix DEFINE_MPRV_READ to support that reading the page which is executable-only (R=0 X=1). Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/fp_asm.S M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/vm.h A src/arch/riscv/misaligend.c M src/arch/riscv/trap_handler.c 6 files changed, 617 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/2 -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@176 PS1, Line 176: int regnum = ((insn >> match->reg_shift) & match->reg_mask) + \ Avoid unnecessary line continuations https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@185 PS1, Line 185: buff.b[i] = mprv_read_u8((uint8_t *) \ Avoid unnecessary line continuations https://review.coreboot.org/#/c/27972/1/src/arch/riscv/misaligend.c@242 PS1, Line 242: mprv_write_u8((uint8_t *)(tf->badvaddr + i), \ Avoid unnecessary line continuations https://review.coreboot.org/#/c/27972/1/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c: https://review.coreboot.org/#/c/27972/1/src/arch/riscv/trap_handler.c@191 PS1, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'? -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 08:21:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: google/kukui: Initialize cbmem to be mepty in romstage
by Tristan Hsieh (Code Review) 09 Aug '18

09 Aug '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27973 Change subject: google/kukui: Initialize cbmem to be mepty in romstage ...................................................................... google/kukui: Initialize cbmem to be mepty in romstage After memory init, cbmem_initialize_empty() should be called in romstage. BUG=b:80501386 TEST=Boots correctly on Kukui Change-Id: I3953104adb7b42079f37a7a0ae38bf64ae1a6074 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27973/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 342a0ba..da2ac2d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -14,6 +14,7 @@ */ #include <arch/exception.h> +#include <cbmem.h> #include <console/console.h> #include <program_loading.h> #include <soc/mmu_operations.h> @@ -29,5 +30,7 @@ mtk_mmu_after_dram(); + cbmem_initialize_empty(); + run_ramstage(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index bd0e54f..8fece79 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -20,7 +20,7 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c verstage-y += ../common/wdt.c -romstage-y += emi.c +romstage-y += ../common/cbmem.c emi.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c -- To view, visit https://review.coreboot.org/27973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3953104adb7b42079f37a7a0ae38bf64ae1a6074 Gerrit-Change-Number: 27973 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by Xiang Wang (Code Review) 09 Aug '18

09 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27972 Change subject: riscv: update misaligned memory access exception handling ...................................................................... riscv: update misaligned memory access exception handling Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to s-mode. fix DEFINE_MPRV_READ to support that reading the page which is executable-only (R=0 X=1). Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/fp_asm.S M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/vm.h A src/arch/riscv/misaligend.c M src/arch/riscv/trap_handler.c 6 files changed, 617 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 85bec43..86ed8b5 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -46,6 +46,8 @@ bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += fp_asm.S +bootblock-y += misaligend.c bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c diff --git a/src/arch/riscv/fp_asm.S b/src/arch/riscv/fp_asm.S new file mode 100644 index 0000000..92546b4 --- /dev/null +++ b/src/arch/riscv/fp_asm.S @@ -0,0 +1,341 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if __riscv_flen >= 32 + + .text + +/* void read_f32(int regnum, uint32_t* v) */ + .align 1 + .globl read_f32 +read_f32: + la a2, .Lr32_t + andi a0, a0, 31 + slli a0, a0, 2 + add a0, a0, a2 + lw a0, 0(a0) + add a0, a0, a2 + jr a0 + .align 2 +.Lr32_t: + .word .Lr32_f0 - .Lr32_t + .word .Lr32_f1 - .Lr32_t + .word .Lr32_f2 - .Lr32_t + .word .Lr32_f3 - .Lr32_t + .word .Lr32_f4 - .Lr32_t + .word .Lr32_f5 - .Lr32_t + .word .Lr32_f6 - .Lr32_t + .word .Lr32_f7 - .Lr32_t + .word .Lr32_f8 - .Lr32_t + .word .Lr32_f9 - .Lr32_t + .word .Lr32_f10 - .Lr32_t + .word .Lr32_f11 - .Lr32_t + .word .Lr32_f12 - .Lr32_t + .word .Lr32_f13 - .Lr32_t + .word .Lr32_f14 - .Lr32_t + .word .Lr32_f15 - .Lr32_t + .word .Lr32_f16 - .Lr32_t + .word .Lr32_f17 - .Lr32_t + .word .Lr32_f18 - .Lr32_t + .word .Lr32_f19 - .Lr32_t + .word .Lr32_f20 - .Lr32_t + .word .Lr32_f21 - .Lr32_t + .word .Lr32_f22 - .Lr32_t + .word .Lr32_f23 - .Lr32_t + .word .Lr32_f24 - .Lr32_t + .word .Lr32_f25 - .Lr32_t + .word .Lr32_f26 - .Lr32_t + .word .Lr32_f27 - .Lr32_t + .word .Lr32_f28 - .Lr32_t + .word .Lr32_f29 - .Lr32_t + .word .Lr32_f30 - .Lr32_t + .word .Lr32_f31 - .Lr32_t +#define read32(which) .Lr32_##which: fsw which, 0(a1); ret + read32(f0) + read32(f1) + read32(f2) + read32(f3) + read32(f4) + read32(f5) + read32(f6) + read32(f7) + read32(f8) + read32(f9) + read32(f10) + read32(f11) + read32(f12) + read32(f13) + read32(f14) + read32(f15) + read32(f16) + read32(f17) + read32(f18) + read32(f19) + read32(f20) + read32(f21) + read32(f22) + read32(f23) + read32(f24) + read32(f25) + read32(f26) + read32(f27) + read32(f28) + read32(f29) + read32(f30) + read32(f31) + +/* void write_f32(int regnum, uint32_t* v) */ + .align 1 + .globl write_f32 +write_f32: + la a2, .Lw32_t + andi a0, a0, 31 + slli a0, a0, 2 + add a0, a0, a2 + lw a0, 0(a0) + add a0, a0, a2 + jr a0 + .align 2 +.Lw32_t: + .word .Lw32_f0 - .Lw32_t + .word .Lw32_f1 - .Lw32_t + .word .Lw32_f2 - .Lw32_t + .word .Lw32_f3 - .Lw32_t + .word .Lw32_f4 - .Lw32_t + .word .Lw32_f5 - .Lw32_t + .word .Lw32_f6 - .Lw32_t + .word .Lw32_f7 - .Lw32_t + .word .Lw32_f8 - .Lw32_t + .word .Lw32_f9 - .Lw32_t + .word .Lw32_f10 - .Lw32_t + .word .Lw32_f11 - .Lw32_t + .word .Lw32_f12 - .Lw32_t + .word .Lw32_f13 - .Lw32_t + .word .Lw32_f14 - .Lw32_t + .word .Lw32_f15 - .Lw32_t + .word .Lw32_f16 - .Lw32_t + .word .Lw32_f17 - .Lw32_t + .word .Lw32_f18 - .Lw32_t + .word .Lw32_f19 - .Lw32_t + .word .Lw32_f20 - .Lw32_t + .word .Lw32_f21 - .Lw32_t + .word .Lw32_f22 - .Lw32_t + .word .Lw32_f23 - .Lw32_t + .word .Lw32_f24 - .Lw32_t + .word .Lw32_f25 - .Lw32_t + .word .Lw32_f26 - .Lw32_t + .word .Lw32_f27 - .Lw32_t + .word .Lw32_f28 - .Lw32_t + .word .Lw32_f29 - .Lw32_t + .word .Lw32_f30 - .Lw32_t + .word .Lw32_f31 - .Lw32_t +#define write32(which) .Lw32_##which: flw which, 0(a1); ret + write32(f0) + write32(f1) + write32(f2) + write32(f3) + write32(f4) + write32(f5) + write32(f6) + write32(f7) + write32(f8) + write32(f9) + write32(f10) + write32(f11) + write32(f12) + write32(f13) + write32(f14) + write32(f15) + write32(f16) + write32(f17) + write32(f18) + write32(f19) + write32(f20) + write32(f21) + write32(f22) + write32(f23) + write32(f24) + write32(f25) + write32(f26) + write32(f27) + write32(f28) + write32(f29) + write32(f30) + write32(f31) +#endif + +#if __riscv_flen >= 64 + + .text + +/* void read_f64(int regnum, uint64_t* v) */ + .align 1 + .globl read_f64 +read_f64: + la a2, .Lr64_t + andi a0, a0, 31 + slli a0, a0, 2 + add a0, a0, a2 + lw a0, 0(a0) + add a0, a0, a2 + jr a0 + .align 2 +.Lr64_t: + .word .Lr64_f0 - .Lr64_t + .word .Lr64_f1 - .Lr64_t + .word .Lr64_f2 - .Lr64_t + .word .Lr64_f3 - .Lr64_t + .word .Lr64_f4 - .Lr64_t + .word .Lr64_f5 - .Lr64_t + .word .Lr64_f6 - .Lr64_t + .word .Lr64_f7 - .Lr64_t + .word .Lr64_f8 - .Lr64_t + .word .Lr64_f9 - .Lr64_t + .word .Lr64_f10 - .Lr64_t + .word .Lr64_f11 - .Lr64_t + .word .Lr64_f12 - .Lr64_t + .word .Lr64_f13 - .Lr64_t + .word .Lr64_f14 - .Lr64_t + .word .Lr64_f15 - .Lr64_t + .word .Lr64_f16 - .Lr64_t + .word .Lr64_f17 - .Lr64_t + .word .Lr64_f18 - .Lr64_t + .word .Lr64_f19 - .Lr64_t + .word .Lr64_f20 - .Lr64_t + .word .Lr64_f21 - .Lr64_t + .word .Lr64_f22 - .Lr64_t + .word .Lr64_f23 - .Lr64_t + .word .Lr64_f24 - .Lr64_t + .word .Lr64_f25 - .Lr64_t + .word .Lr64_f26 - .Lr64_t + .word .Lr64_f27 - .Lr64_t + .word .Lr64_f28 - .Lr64_t + .word .Lr64_f29 - .Lr64_t + .word .Lr64_f30 - .Lr64_t + .word .Lr64_f31 - .Lr64_t +#define read64(which) .Lr64_##which: fsd which, 0(a1); ret + read64(f0) + read64(f1) + read64(f2) + read64(f3) + read64(f4) + read64(f5) + read64(f6) + read64(f7) + read64(f8) + read64(f9) + read64(f10) + read64(f11) + read64(f12) + read64(f13) + read64(f14) + read64(f15) + read64(f16) + read64(f17) + read64(f18) + read64(f19) + read64(f20) + read64(f21) + read64(f22) + read64(f23) + read64(f24) + read64(f25) + read64(f26) + read64(f27) + read64(f28) + read64(f29) + read64(f30) + read64(f31) + +/* void write_f64(int regnum, uint64_t* v) */ + .align 1 + .globl write_f64 +write_f64: + la a2, .Lw64_t + andi a0, a0, 31 + slli a0, a0, 2 + add a0, a0, a2 + lw a0, 0(a0) + add a0, a0, a2 + jr a0 + .align 2 +.Lw64_t: + .word .Lw64_f0 - .Lw64_t + .word .Lw64_f1 - .Lw64_t + .word .Lw64_f2 - .Lw64_t + .word .Lw64_f3 - .Lw64_t + .word .Lw64_f4 - .Lw64_t + .word .Lw64_f5 - .Lw64_t + .word .Lw64_f6 - .Lw64_t + .word .Lw64_f7 - .Lw64_t + .word .Lw64_f8 - .Lw64_t + .word .Lw64_f9 - .Lw64_t + .word .Lw64_f10 - .Lw64_t + .word .Lw64_f11 - .Lw64_t + .word .Lw64_f12 - .Lw64_t + .word .Lw64_f13 - .Lw64_t + .word .Lw64_f14 - .Lw64_t + .word .Lw64_f15 - .Lw64_t + .word .Lw64_f16 - .Lw64_t + .word .Lw64_f17 - .Lw64_t + .word .Lw64_f18 - .Lw64_t + .word .Lw64_f19 - .Lw64_t + .word .Lw64_f20 - .Lw64_t + .word .Lw64_f21 - .Lw64_t + .word .Lw64_f22 - .Lw64_t + .word .Lw64_f23 - .Lw64_t + .word .Lw64_f24 - .Lw64_t + .word .Lw64_f25 - .Lw64_t + .word .Lw64_f26 - .Lw64_t + .word .Lw64_f27 - .Lw64_t + .word .Lw64_f28 - .Lw64_t + .word .Lw64_f29 - .Lw64_t + .word .Lw64_f30 - .Lw64_t + .word .Lw64_f31 - .Lw64_t +#define write64(which) .Lw64_##which: fld which, 0(a1); ret + write64(f0) + write64(f1) + write64(f2) + write64(f3) + write64(f4) + write64(f5) + write64(f6) + write64(f7) + write64(f8) + write64(f9) + write64(f10) + write64(f11) + write64(f12) + write64(f13) + write64(f14) + write64(f15) + write64(f16) + write64(f17) + write64(f18) + write64(f19) + write64(f20) + write64(f21) + write64(f22) + write64(f23) + write64(f24) + write64(f25) + write64(f26) + write64(f27) + write64(f28) + write64(f29) + write64(f30) + write64(f31) + +#endif diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index fc57b3b..6fbbdf0 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -32,8 +32,7 @@ #include <stdint.h> -typedef struct -{ +typedef struct { uintptr_t gpr[32]; uintptr_t status; uintptr_t epc; @@ -53,9 +52,9 @@ { } -void trap_handler(trapframe* tf); -void handle_supervisor_call(trapframe* tf); -void handle_misaligned_load(trapframe *tf); -void handle_misaligned_store(trapframe *tf); +void redirect_trap(void); +void trap_handler(trapframe *tf); +void handle_supervisor_call(trapframe *tf); +void handle_misaligned(trapframe *tf); #endif diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index a30d6bb..2925977 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -42,7 +42,7 @@ static inline type name(type *p); \ static inline type name(type *p) \ { \ - size_t mprv = MSTATUS_MPRV; \ + size_t mprv = MSTATUS_MPRV | MSTATUS_MXR; \ type value; \ asm ( \ "csrs mstatus, %1\n" \ diff --git a/src/arch/riscv/misaligend.c b/src/arch/riscv/misaligend.c new file mode 100644 index 0000000..a282a05 --- /dev/null +++ b/src/arch/riscv/misaligend.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdint.h> +#include <vm.h> +#include <arch/exception.h> + +/* this function define in src/arch/riscv/fp_asm.S */ +#if __riscv_flen >= 32 +extern void read_f32(int regnum, uint32_t *v); +extern void write_f32(int regnum, uint32_t *v); +#endif + +#if __riscv_flen >= 64 +extern void read_f64(int regnum, uint64_t *v); +extern void write_f64(int regnum, uint64_t *v); +#endif + + +union endian_buff { + uint8_t b[8]; + uint16_t h[4]; + uint32_t w[2]; + uint64_t d[1]; + uintptr_t v; +}; + +struct memory_instruction_info { + uintptr_t opcode; + uintptr_t mask; + int reg_shift; + int reg_mask; + int reg_addition; + int is_fp; + int is_load; + int width; + int sign_extend; +}; + +static struct memory_instruction_info insn_info[] = { +#if __riscv_xlen == 128 + { 0x00002000, 0x0000e003, 2, 7, 8, 0, 1, 16, 1}, // C.LQ +#else + { 0x00002000, 0x0000e003, 2, 7, 8, 1, 1, 8, 0}, // C.FLD +#endif + { 0x00004000, 0x0000e003, 2, 7, 8, 0, 1, 4, 1}, // C.LW +#if __riscv_xlen == 32 + { 0x00006000, 0x0000e003, 2, 7, 8, 1, 1, 4, 0}, // C.FLW +#else + { 0x00006000, 0x0000e003, 2, 7, 8, 0, 1, 8, 1}, // C.LD +#endif + +#if __riscv_xlen == 128 + { 0x0000a000, 0x0000e003, 2, 7, 8, 0, 0, 16, 0}, // C.SQ +#else + { 0x0000a000, 0x0000e003, 2, 7, 8, 1, 0, 8, 0}, // C.FSD +#endif + { 0x0000c000, 0x0000e003, 2, 7, 8, 0, 0, 4, 0}, // C.SW +#if __riscv_xlen == 32 + { 0x0000e000, 0x0000e003, 2, 7, 8, 1, 0, 4, 0}, // C.FSW +#else + { 0x0000e000, 0x0000e003, 2, 7, 8, 0, 0, 8, 0}, // C.SD +#endif + +#if __riscv_xlen == 128 + { 0x00002002, 0x0000e003, 7, 15, 0, 0, 1, 16, 1}, // C.LQSP +#else + { 0x00002002, 0x0000e003, 7, 15, 0, 1, 1, 8, 0}, // C.FLDSP +#endif + { 0x00004002, 0x0000e003, 7, 15, 0, 0, 1, 4, 1}, // C.LWSP +#if __riscv_xlen == 32 + { 0x00006002, 0x0000e003, 7, 15, 0, 1, 1, 4, 0}, // C.FLWSP +#else + { 0x00006002, 0x0000e003, 7, 15, 0, 0, 1, 8, 1}, // C.LDSP +#endif + +#if __riscv_xlen == 128 + { 0x0000a002, 0x0000e003, 2, 15, 0, 0, 0, 16, 0}, // C.SQSP +#else + { 0x0000a002, 0x0000e003, 2, 15, 0, 1, 0, 8, 0}, // C.FSDSP +#endif + { 0x0000c002, 0x0000e003, 2, 15, 0, 0, 0, 4, 0}, // C.SWSP +#if __riscv_xlen == 32 + { 0x0000e002, 0x0000e003, 2, 15, 0, 1, 0, 4, 0}, // C.FSWSP +#else + { 0x0000e002, 0x0000e003, 2, 15, 0, 0, 0, 8, 0}, // C.SDSP +#endif + + { 0x00000003, 0x0000707f, 7, 15, 0, 0, 1, 1, 1}, // LB + { 0x00001003, 0x0000707f, 7, 15, 0, 0, 1, 2, 1}, // LH + { 0x00002003, 0x0000707f, 7, 15, 0, 0, 1, 4, 1}, // LW +#if __riscv_xlen > 32 + { 0x00003003, 0x0000707f, 7, 15, 0, 0, 1, 8, 1}, // LD +#endif + { 0x00004003, 0x0000707f, 7, 15, 0, 0, 1, 1, 0}, // LBU + { 0x00005003, 0x0000707f, 7, 15, 0, 0, 1, 2, 0}, // LHU + { 0x00006003, 0x0000707f, 7, 15, 0, 0, 1, 4, 0}, // LWU + + { 0x00000023, 0x0000707f, 20, 15, 0, 0, 0, 1, 0}, // SB + { 0x00001023, 0x0000707f, 20, 15, 0, 0, 0, 2, 0}, // SH + { 0x00002023, 0x0000707f, 20, 15, 0, 0, 0, 4, 0}, // SW +#if __riscv_xlen > 32 + { 0x00003023, 0x0000707f, 20, 15, 0, 0, 0, 8, 0}, // SD +#endif + +#if __riscv_flen >= 32 + { 0x00002007, 0x0000707f, 7, 15, 0, 1, 1, 4, 0}, // FLW + { 0x00003007, 0x0000707f, 7, 15, 0, 1, 1, 8, 0}, // FLD +#endif + +#if __riscv_flen >= 64 + { 0x00002027, 0x0000707f, 20, 15, 0, 1, 0, 4, 0}, // FSW + { 0x00003027, 0x0000707f, 20, 15, 0, 1, 0, 8, 0}, // FSD +#endif + { 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +static struct memory_instruction_info *match_instruction(uintptr_t insn) +{ + struct memory_instruction_info *p; + for (p = insn_info; p->opcode; p++) + if ((insn & p->mask) == p->opcode) + return p; + return NULL; +} + + +static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn) +{ + uint16_t t = mprv_read_u16((uint16_t *)vaddr); + if (EXTRACT_FIELD(t, 0x3) != 3) { + *insn = t; + return 0; + } + return -1; +} + +static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn) +{ + uint32_t t = mprv_read_u32((uint32_t *)vaddr); + if ((EXTRACT_FIELD(t, 0x3) == 3) && (EXTRACT_FIELD(t, 0x1c) != 0x7)) { + *insn = t; + return 0; + } + return -1; +} + + +void handle_misaligned(trapframe *tf) +{ + uintptr_t insn = 0; + union endian_buff buff; + + /* try to fetch 16/32 bits instruction */ + if (fetch_16bit_instruction(tf->epc, &insn)) + if (fetch_32bit_instruction(tf->epc, &insn)) + redirect_trap(); + + /* matching instruction */ + struct memory_instruction_info *match = match_instruction(insn); + + if (match) { + int regnum = ((insn >> match->reg_shift) & match->reg_mask) + \ + match->reg_addition; + buff.v = 0; + if (match->is_load) { + /* load operate */ + + /* reading from memory by bytes prevents misaligned + * memory access */ + for (int i = 0; i < match->width; i++) + buff.b[i] = mprv_read_u8((uint8_t *) \ + (tf->badvaddr + i)); + + /* sign extend for signed integer loading */ + if (match->sign_extend) + if (buff.v >> (8 * match->width - 1)) + buff.v |= -1 << (8 * match->width); + + /* write to register */ + if (match->is_fp) { + do { +#if __riscv_flen >= 32 + /* single-precision floating-point */ + if (match->width == 4) { + write_f32(regnum, buff.w); + break; + } +#endif +#if __riscv_flen >= 64 + /* double-precision floating-point */ + if (match->width == 8) { + write_f64(regnum, buff.d); + break; + } +#endif + redirect_trap(); + } while (0); + } else { + tf->gpr[regnum] = buff.v; + } + } else { + /* store operate */ + + /* reading from register */ + if (match->is_fp) { + do { +#if __riscv_flen >= 32 + if (match->width == 4) { + read_f32(regnum, buff.w); + break; + } +#endif +#if __riscv_flen >= 64 + if (match->width == 8) { + read_f64(regnum, buff.d); + break; + } +#endif + redirect_trap(); + } while (0); + } else { + buff.v = tf->gpr[regnum]; + } + + /* writing to memory by bytes prevents misaligned\ + * memory access */ + for (int i = 0; i < match->width; i++) + mprv_write_u8((uint8_t *)(tf->badvaddr + i), \ + buff.b[i]); + } + } else { + redirect_trap(); + } +} + + + + + diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 7b35c2e..6888c8d 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -167,11 +167,11 @@ break; case CAUSE_MISALIGNED_LOAD: print_trap_information(tf); - handle_misaligned_load(tf); + handle_misaligned(tf); return; case CAUSE_MISALIGNED_STORE: print_trap_information(tf); - handle_misaligned_store(tf); + handle_misaligned(tf); return; default: printk(BIOS_EMERG, "================================\n"); @@ -184,62 +184,19 @@ die("Can't recover from trap. Halting.\n"); } -static uint32_t fetch_instruction(uintptr_t vaddr) { - printk(BIOS_SPEW, "fetching instruction at 0x%016zx\n", (size_t)vaddr); - return mprv_read_u32((uint32_t *) vaddr); + +void redirect_trap(void) +{ + write_csr(sbadaddr, read_csr(mbadaddr)); + write_csr(sepc, read_csr(mepc)); + write_csr(scause, read_csr(mcause)); + write_csr(mepc, read_csr(stvec)); + + uintptr_t status = read_csr(mstatus); + uintptr_t mpp = EXTRACT_FIELD(status, 0x1800); + status = INSERT_FIELD(status, 0x1800, 1); + status = INSERT_FIELD(status, 0x100, mpp & 1); + write_csr(mstatus, status); } -void handle_misaligned_load(trapframe *tf) { - printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); - uintptr_t faultingInstructionAddr = tf->epc; - insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr); - printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); - insn_t widthMask = 0x7000; - insn_t memWidth = (faultingInstruction & widthMask) >> 12; - insn_t destMask = 0xF80; - insn_t destRegister = (faultingInstruction & destMask) >> 7; - printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8); - if (memWidth == 3) { - // load double, handle the issue - void* badAddress = (void*) tf->badvaddr; - uint64_t value = 0; - for (int i = 0; i < 8; i++) { - value <<= 8; - value += mprv_read_u8(badAddress+i); - } - tf->gpr[destRegister] = value; - } else { - // panic, this should not have happened - die("Code should not reach this path, misaligned on a non-64 bit store/load\n"); - } - // return to where we came from - write_csr(mepc, read_csr(mepc) + 4); -} - -void handle_misaligned_store(trapframe *tf) { - printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf); - uintptr_t faultingInstructionAddr = tf->epc; - insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr); - printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction); - insn_t widthMask = 0x7000; - insn_t memWidth = (faultingInstruction & widthMask) >> 12; - insn_t srcMask = 0x1F00000; - insn_t srcRegister = (faultingInstruction & srcMask) >> 20; - printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8); - if (memWidth == 3) { - // store double, handle the issue - void* badAddress = (void*) tf->badvaddr; - uint64_t value = tf->gpr[srcRegister]; - for (int i = 0; i < 8; i++) { - mprv_write_u8(badAddress+i, value); - value >>= 8; - } - } else { - // panic, this should not have happened - die("Code should not reach this path, misaligned on a non-64 bit store/load\n"); - } - - // return to where we came from - write_csr(mepc, read_csr(mepc) + 4); -} -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DRAM resource in ramstage
by Tristan Hsieh (Code Review) 09 Aug '18

09 Aug '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27971 Change subject: mediatek/mt8183: Add DRAM resource in ramstage ...................................................................... mediatek/mt8183: Add DRAM resource in ramstage Add DRAM resource in ramstage to load payload. BUG=b:80501386 TEST=Boots correctly on Kukui Change-Id: Ie793b403bbbdb3c231dfa2caef29dcbb596b1a61 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/soc.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27971/1 diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b8348a1..b51e7d4 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -14,7 +14,15 @@ */ #include <device/device.h> +#include <soc/emi.h> #include <soc/mmu_operations.h> +#include <symbols.h> + + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} static void soc_init(struct device *dev) { @@ -22,6 +30,7 @@ } static struct device_operations soc_ops = { + .read_resources = soc_read_resources, .init = soc_init, }; -- To view, visit https://review.coreboot.org/27971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie793b403bbbdb3c231dfa2caef29dcbb596b1a61 Gerrit-Change-Number: 27971 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: fit: Handle decompression errors properly
by Patrick Rudolph (Code Review) 09 Aug '18

09 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27970 Change subject: fit: Handle decompression errors properly ...................................................................... fit: Handle decompression errors properly Set payload to NULL in case of decompression errors. Fixes booting a kernel that could be decompressed. Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/fit_payload.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27970/1 diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index ada22e8..9dbd878 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -163,6 +163,7 @@ if (config->ramdisk_node && extract(&initrd, config->ramdisk_node)) { printk(BIOS_ERR, "ERROR: Failed to extract initrd\n"); + prog_set_entry(payload, NULL, NULL); rdev_munmap(prog_rdev(payload), data); return; } @@ -171,6 +172,7 @@ if (extract(&kernel, config->kernel_node)) { printk(BIOS_ERR, "ERROR: Failed to extract kernel\n"); + prog_set_entry(payload, NULL, NULL); rdev_munmap(prog_rdev(payload), data); return; } -- To view, visit https://review.coreboot.org/27970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a Gerrit-Change-Number: 27970 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/google/octopus/variants/fleex: Setup DPTF table
by John Su (Code Review) 09 Aug '18

09 Aug '18

John Su has uploaded this change for review. ( https://review.coreboot.org/27969 Change subject: mb/google/octopus/variants/fleex: Setup DPTF table ...................................................................... mb/google/octopus/variants/fleex: Setup DPTF table Follow thermal table for first tunning. BUG=b:112274477 TEST=Match the result from DPTF UI. Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl 1 file changed, 71 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27969/1 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl index cc17d56..bbcdc70 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl @@ -13,4 +13,74 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 127 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 90 +#define DPTF_TSR0_CRITICAL 127 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 90 +#define DPTF_TSR1_CRITICAL 127 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 90 +#define DPTF_TSR2_CRITICAL 127 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 10, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 500, 10, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 500, 10, 0, 0, 0, 0 }, +#endif +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 500 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 500 /* StepSize */ + } +}) -- To view, visit https://review.coreboot.org/27969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244 Gerrit-Change-Number: 27969 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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coreboot-gerrit August 2018