coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

1 participants
1120 discussions

Change in coreboot[master]: [TESTONLY]nb/intel/i945: Only disable VGA decode on IGD
by Arthur Heymans (Code Review) 09 Aug '18

09 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27985 Change subject: [TESTONLY]nb/intel/i945: Only disable VGA decode on IGD ...................................................................... [TESTONLY]nb/intel/i945: Only disable VGA decode on IGD Could be some targets don't have enough pci_mmio_size... Change-Id: I4f1e1ab349b3e4bcb4d49da4b6d091e57243ee8f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/gma.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/27985/1 diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 83dc42e..2e6cebf 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -729,13 +729,7 @@ struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); pci_write_config16(dev, GCFC, 0xa00); - pci_write_config16(dev_host, GGC, (1 << 1)); - - unsigned int reg32 = pci_read_config32(dev_host, DEVEN); - reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); - pci_write_config32(dev_host, DEVEN, reg32); - - dev->enabled = 0; + pci_or_config16(dev, GGC, 1 << 1); } static void gma_func1_init(struct device *dev) -- To view, visit https://review.coreboot.org/27985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4f1e1ab349b3e4bcb4d49da4b6d091e57243ee8f Gerrit-Change-Number: 27985 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27984 ) Change subject: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27984/2/src/northbridge/intel/sandybridge/g… File src/northbridge/intel/sandybridge/gma.c: https://review.coreboot.org/#/c/27984/2/src/northbridge/intel/sandybridge/g… PS2, Line 648: struct northbridge_intel_sandybridge_config *conf = dev->chip_info; line over 80 characters -- To view, visit https://review.coreboot.org/27984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Gerrit-Change-Number: 27984 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 09:43:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled
by Arthur Heymans (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27984 to look at the new patch set (#2). Change subject: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled ...................................................................... [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled writes to VGA MEM and IO by NGI are invalid if the IGD is not decoding them. Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c 6 files changed, 81 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27984/2 -- To view, visit https://review.coreboot.org/27984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Gerrit-Change-Number: 27984 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27984 ) Change subject: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27984/1/src/northbridge/intel/sandybridge/g… File src/northbridge/intel/sandybridge/gma.c: https://review.coreboot.org/#/c/27984/1/src/northbridge/intel/sandybridge/g… PS1, Line 648: struct northbridge_intel_sandybridge_config *conf = dev->chip_info; line over 80 characters -- To view, visit https://review.coreboot.org/27984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Gerrit-Change-Number: 27984 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 09:34:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled
by Arthur Heymans (Code Review) 09 Aug '18

09 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27984 Change subject: [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled ...................................................................... [WIP]nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled writes to VGA MEM and IO by NGI are invalid if the IGD is not decoding them. Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c 6 files changed, 81 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27984/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 606170c..1316fad 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -771,11 +771,18 @@ /* Post VBIOS init */ gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - gma_ngi(dev, &edid_lvds); - } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - int lightup_ok; - gma_gfxinit(&lightup_ok); + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; + + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + } else { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + gma_ngi(dev, &edid_lvds); + } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + } } intel_gma_restore_opregion(); diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 8ffdce8..8f60da4 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -468,10 +468,17 @@ /* Pre panel init */ gma_setup_panel(dev); + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); - gma_gfxinit(&lightup_ok); - gfx_set_init_done(1); + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + } else { + printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); + gma_gfxinit(&lightup_ok); + gfx_set_init_done(1); + } } if (! lightup_ok) { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 6c3d6ae..83dc42e 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -700,12 +700,20 @@ pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - if (acpi_is_wakeup_s3()) + if (acpi_is_wakeup_s3()) { printk(BIOS_INFO, "Skipping native VGA initialization when resuming from ACPI S3.\n"); - else - gma_ngi(dev); + } else { + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + } else { + gma_ngi(dev); + } + } } else { /* PCI Init, will run VBIOS */ pci_dev_init(dev); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 8cf4d22..02100e9 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -275,6 +275,8 @@ struct resource *pio_res; struct northbridge_intel_pineview_config *conf = dev->chip_info; + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; + /* Find base addresses */ mmio_res = find_resource(dev, 0x10); gtt_res = find_resource(dev, 0x1c); @@ -282,11 +284,17 @@ physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { - printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", - mmio_res->base); - intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0), - res2mmio(gtt_res, 0, 0), - physbase, pio_res->base); + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + } else { + printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", + mmio_res->base); + intel_gma_init(conf, dev, + res2mmio(mmio_res, 0, 0), + res2mmio(gtt_res, 0, 0), + physbase, pio_res->base); + } } /* Linux relies on VBT for panel info. */ diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 73546ce..042c2a9 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -631,29 +631,38 @@ /* Post VBIOS init */ gma_pm_init_post_vbios(dev); + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; + /* Running graphics init on S3 breaks Linux drm driver. */ if (!acpi_is_wakeup_s3() && (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT))) { - /* This should probably run before post VBIOS init. */ - printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u8 *mmiobase; - u32 iobase, physbase, graphics_base; - struct northbridge_intel_sandybridge_config *conf = dev->chip_info; - iobase = dev->resource_list[2].base; - mmiobase = res2mmio(&dev->resource_list[0], 0, 0); - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[1].base; - - int lightup_ok; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - gma_gfxinit(&lightup_ok); + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); } else { - lightup_ok = i915lightup_sandy(&conf->gfx, physbase, - iobase, mmiobase, graphics_base); + /* This should probably run before post VBIOS init. */ + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); + u8 *mmiobase; + u32 iobase, physbase, graphics_base; + struct northbridge_intel_sandybridge_config *conf = dev->chip_info; + iobase = dev->resource_list[2].base; + mmiobase = res2mmio(&dev->resource_list[0], 0, 0); + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + graphics_base = dev->resource_list[1].base; + + int lightup_ok; + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + gma_gfxinit(&lightup_ok); + } else { + lightup_ok = i915lightup_sandy(&conf->gfx, + physbase, + iobase, mmiobase, + graphics_base); + } + if (lightup_ok) + gfx_set_init_done(1); } - if (lightup_ok) - gfx_set_init_done(1); } gma_enable_swsci(); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 2d2feee..d0c40b1 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -60,7 +60,7 @@ static void gma_func0_init(struct device *dev) { - u16 reg16, ggc; + u16 reg16; u32 reg32; /* IGD needs to be Bus Master */ @@ -74,11 +74,16 @@ reg16 |= 0xbc; pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16); - ggc = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); + int vga_disable = pci_read_config16(dev, D0F0_GGC); if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - int lightup_ok; - gma_gfxinit(&lightup_ok); + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + } else { + int lightup_ok; + gma_gfxinit(&lightup_ok); + } } else { pci_dev_init(dev); } -- To view, visit https://review.coreboot.org/27984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Gerrit-Change-Number: 27984 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/27972/6/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c: https://review.coreboot.org/#/c/27972/6/src/arch/riscv/trap_handler.c@191 PS6, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'? -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 6 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 08:47:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: riscv: update misaligned memory access exception handling
by Xiang Wang (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27972 to look at the new patch set (#6). Change subject: riscv: update misaligned memory access exception handling ...................................................................... riscv: update misaligned memory access exception handling Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. fix DEFINE_MPRV_READ to support that reading the page which is executable-only (R=0 X=1). Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/fp_asm.S M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/vm.h A src/arch/riscv/misaligend.c M src/arch/riscv/trap_handler.c 6 files changed, 619 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/6 -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 6 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/27972/5/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/5/src/arch/riscv/misaligend.c@242 PS5, Line 242: * memory access */ code indent should use tabs where possible https://review.coreboot.org/#/c/27972/5/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c: https://review.coreboot.org/#/c/27972/5/src/arch/riscv/trap_handler.c@191 PS5, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'? -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 08:45:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: riscv: update misaligned memory access exception handling
by Xiang Wang (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27972 to look at the new patch set (#5). Change subject: riscv: update misaligned memory access exception handling ...................................................................... riscv: update misaligned memory access exception handling Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. fix DEFINE_MPRV_READ to support that reading the page which is executable-only (R=0 X=1). Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/fp_asm.S M src/arch/riscv/include/arch/exception.h M src/arch/riscv/include/vm.h A src/arch/riscv/misaligend.c M src/arch/riscv/trap_handler.c 6 files changed, 619 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27972/5 -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 5 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: google/kukui: Initialize cbmem to be empty in romstage
by Tristan Hsieh (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27973 to look at the new patch set (#2). Change subject: google/kukui: Initialize cbmem to be empty in romstage ...................................................................... google/kukui: Initialize cbmem to be empty in romstage After memory init, cbmem_initialize_empty() should be called in romstage. BUG=b:80501386 TEST=Boots correctly on Kukui Change-Id: I3953104adb7b42079f37a7a0ae38bf64ae1a6074 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27973/2 -- To view, visit https://review.coreboot.org/27973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3953104adb7b42079f37a7a0ae38bf64ae1a6074 Gerrit-Change-Number: 27973 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2018