coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: update PL2 based on CPU sku
by Lijian Zhao (Code Review) 10 Aug '18

10 Aug '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/27997 ) Change subject: mb/google/poppy/variant/nocturne: update PL2 based on CPU sku ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27997/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/mainboard.c: https://review.coreboot.org/#/c/27997/1/src/mainboard/google/poppy/variants… PS1, Line 23: define PL2_AML 18 : #define PL2_KBL 15 Better to add comment about 18 Watt and 15 Watt, or just change get_pl2 to get_pl2_in_watts for easier understanding -- To view, visit https://review.coreboot.org/27997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973 Gerrit-Change-Number: 27997 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Fri, 10 Aug 2018 00:27:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: update PL2 based on CPU sku
by Nick Vaccaro (Code Review) 09 Aug '18

09 Aug '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/27997 Change subject: mb/google/poppy/variant/nocturne: update PL2 based on CPU sku ...................................................................... mb/google/poppy/variant/nocturne: update PL2 based on CPU sku This patch adds a function to overwrite PL2 setting based on CPU sku. From doc #594883, PL2 is 18W for AML-Y. BUG=b:110890675 BRANCH=None TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/Makefile.inc A src/mainboard/google/poppy/variants/nocturne/mainboard.c 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27997/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc index b78b7a3..c17a49c 100644 --- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc @@ -19,3 +19,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c new file mode 100644 index 0000000..07a4e66 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +#define PL2_AML 18 +#define PL2_KBL 15 + +static uint32_t get_pl2(void) +{ + uint16_t id; + id = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); + /* Assume we only have KLB-Y and AML-Y SKUs */ + if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM) + return PL2_KBL; + + return PL2_AML; +} + +/* Override dev tree settings per board */ +void variant_devtree_update(void) +{ + struct device *root = SA_DEV_ROOT; + config_t *cfg = root->chip_info; + + /* Update PL2 based on CPU */ + cfg->tdp_pl2_override = get_pl2(); +} -- To view, visit https://review.coreboot.org/27997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973 Gerrit-Change-Number: 27997 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove icc_max overrides
by Nick Vaccaro (Code Review) 09 Aug '18

09 Aug '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/27996 Change subject: mb/google/poppy/variants/nocturne: remove icc_max overrides ...................................................................... mb/google/poppy/variants/nocturne: remove icc_max overrides Remove icc_max overrides to allow SoC code to set proper icc_max based on CPU SKU. BUG=b:78122599 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash to nocturne, boot to kernel and verify device doesn't hang after a few minutes. Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27996/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 9d9c5ae..2c074e9 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -87,7 +87,7 @@ #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 4A | 28A | 24A | 24A | + #| IccMax | Set by SoC code per CPU SKU | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 14.9 | 4 | 5.7 | 4.57 | #| DcLoadline | 14.2 | 4 | 4.2 | 4.3 | @@ -101,7 +101,6 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(4), .voltage_limit = 1520, .ac_loadline = 1490, .dc_loadline = 1420, @@ -116,7 +115,6 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(28), .voltage_limit = 1520, .ac_loadline = 400, .dc_loadline = 400, @@ -131,7 +129,6 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, .ac_loadline = 570, .dc_loadline = 420, @@ -146,7 +143,6 @@ .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, .ac_loadline = 457, .dc_loadline = 430, -- To view, visit https://review.coreboot.org/27996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582 Gerrit-Change-Number: 27996 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: drivers/i2c/tpm/cr50.c: Check if TPM was read
by Richard Spiegel (Code Review) 09 Aug '18

09 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27995 Change subject: drivers/i2c/tpm/cr50.c: Check if TPM was read ...................................................................... drivers/i2c/tpm/cr50.c: Check if TPM was read Under some conditions, cr50_i2c_read() can return without actually reading the TPM, which will leave access uninitialized. Set an initial value for access, and if TPM fails to respond in time check if at least TPM was read. This way avoids printing an uninitialized value. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I5ec7a99396db32971dc8485b77158d735ab1d788 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/drivers/i2c/tpm/cr50.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27995/1 diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 3c2f5bd..036be42 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -181,7 +181,7 @@ static int process_reset(struct tpm_chip *chip) { struct stopwatch sw; - uint8_t access; + uint8_t access = 0xff; /* * Locality is released by TPM reset. @@ -214,9 +214,12 @@ return 0; } while (!stopwatch_expired(&sw)); - printk(BIOS_ERR, - "TPM failed to reset after %ld ms, status: %#x\n", - stopwatch_duration_msecs(&sw), access); + if (access == 0xff) + printk(BIOS_ERR, "Failed to read TPM\n"); + else + printk(BIOS_ERR, + "TPM failed to reset after %ld ms, status: %#x\n", + stopwatch_duration_msecs(&sw), access); return -1; } -- To view, visit https://review.coreboot.org/27995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5ec7a99396db32971dc8485b77158d735ab1d788 Gerrit-Change-Number: 27995 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/octopus: Do not configure IOStandby for WLAN_PE_RST
by Furquan Shaikh (Code Review) 09 Aug '18

09 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27994 Change subject: mb/google/octopus: Do not configure IOStandby for WLAN_PE_RST ...................................................................... mb/google/octopus: Do not configure IOStandby for WLAN_PE_RST PERST signal is asserted/deasserted by ACPI routines during suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in failure to resume from suspend state with wake-over-WLAN. This change removes the IOStandby configuration for WLAN_PE_RST. BUG=b:112371978 Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bip/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/27994/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 3dee892..64cfe4d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -226,7 +226,7 @@ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RXDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ @@ -310,7 +310,7 @@ /* Enable power to wifi early in bootblock and de-assert PERST#. */ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index f976e15..d929284 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -225,7 +225,7 @@ PAD_NC(GPIO_161, DN_20K),/* AVS_I2S1_MCLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ @@ -303,7 +303,7 @@ /* Enable power to wifi early in bootblock and de-assert PERST#. */ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak -- To view, visit https://review.coreboot.org/27994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1 Gerrit-Change-Number: 27994 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake: Get rid of cnvi.asl
by Furquan Shaikh (Code Review) 09 Aug '18

09 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27992 Change subject: soc/intel/apollolake: Get rid of cnvi.asl ...................................................................... soc/intel/apollolake: Get rid of cnvi.asl There is no need to add a special cnvi.asl file for the CNVi device. This can be handled by drivers/intel/wifi just like a PCIe WiFi device. This change gets rid of the cnvi.asl file and its usage in southbridge.asl file. BUG=b:112371978 Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/soc/intel/apollolake/acpi/cnvi.asl M src/soc/intel/apollolake/acpi/southbridge.asl 2 files changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/27992/1 diff --git a/src/soc/intel/apollolake/acpi/cnvi.asl b/src/soc/intel/apollolake/acpi/cnvi.asl deleted file mode 100644 index a4d255d..0000000 --- a/src/soc/intel/apollolake/acpi/cnvi.asl +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* CNVi Controller 0:C.0 */ -Device (CNVI) { - Name(_ADR, 0x000C0000) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 }) - - Method (_STA, 0) - { - Return (0xF) - } -} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 9f14db4..799778b 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -47,10 +47,4 @@ /* SGX */ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> - -/* CNVi */ -#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) -#include "cnvi.asl" -#endif - #endif -- To view, visit https://review.coreboot.org/27992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229 Gerrit-Change-Number: 27992 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/octopus: Configure WiFi wake as NC when using CNVi
by Furquan Shaikh (Code Review) 09 Aug '18

09 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27993 Change subject: mb/google/octopus: Configure WiFi wake as NC when using CNVi ...................................................................... mb/google/octopus: Configure WiFi wake as NC when using CNVi When CNVi is being used, external wake using GPIO_119 is not required. This change configures GPIO_119 as PAD_NC if CNVi is taken out of reset. BUG=b:112371978 Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/mainboard.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/27993/1 diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 61baa33..61d254e 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -50,6 +50,15 @@ return false; } +static void disable_wifi_wake(void) +{ + static const struct pad_config wifi_wake_gpio[] = { + PAD_NC(GPIO_119, UP_20K), + }; + + gpio_configure_pads(wifi_wake_gpio, ARRAY_SIZE(wifi_wake_gpio)); +} + static void mainboard_init(void *chip_info) { int boardid; @@ -66,6 +75,9 @@ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + if (!is_cnvi_held_in_reset()) + disable_wifi_wake(); + mainboard_ec_init(); } -- To view, visit https://review.coreboot.org/27993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce Gerrit-Change-Number: 27993 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: minnowmax: allow both 1333 and 1066 MHz memory SKUs
by build bot (Jenkins) (Code Review) 09 Aug '18

09 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27989 ) Change subject: minnowmax: allow both 1333 and 1066 MHz memory SKUs ...................................................................... Patch Set 2: (8 comments) https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… File src/mainboard/intel/minnowmax/romstage.c: https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 61: .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 65: .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 66: .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 69: .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 80: .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 84: .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 85: .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */ line over 80 characters https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romst… PS2, Line 88: .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ line over 80 characters -- To view, visit https://review.coreboot.org/27989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e57dd419b443dfa742c8812cec87274af557728 Gerrit-Change-Number: 27989 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 21:30:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: minnowmax: allow both 1333 and 1066 MHz memory SKUs
by Michał Żygowski (Code Review) 09 Aug '18

09 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27989 to look at the new patch set (#2). Change subject: minnowmax: allow both 1333 and 1066 MHz memory SKUs ...................................................................... minnowmax: allow both 1333 and 1066 MHz memory SKUs The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. Use frequency as a proxy to determine SKU. The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the E3827 and E3845 are 1750MHz and 1910MHz, respectively. This will allow to boot quad-core Minnowboard Turbot especially. Change-Id: I5e57dd419b443dfa742c8812cec87274af557728 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/intel/minnowmax/romstage.c 1 file changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27989/2 -- To view, visit https://review.coreboot.org/27989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5e57dd419b443dfa742c8812cec87274af557728 Gerrit-Change-Number: 27989 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/vboot/Makefile: Use shell cat instead of make file command
by Philipp Deppenwiese (Code Review) 09 Aug '18

09 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27990 ) Change subject: security/vboot/Makefile: Use shell cat instead of make file command ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e32a521ad3e6759853f0cde2e4c4db6e564d3be Gerrit-Change-Number: 27990 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Aug 2018 19:53:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit August 2018