coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/octopus: Disable unused I2C2 in devicetree
by Furquan Shaikh (Code Review) 10 Aug '18

10 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28016 Change subject: mb/google/octopus: Disable unused I2C2 in devicetree ...................................................................... mb/google/octopus: Disable unused I2C2 in devicetree I2C2 is unused on all octopus variants. This change disables it in devicetree. BUG=b:112458032 Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/28016/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index b7c7ad2..01fd05f 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -144,7 +144,7 @@ device pci 15.1 on end # - XDCI device pci 16.0 on end # - I2C 0 device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 + device pci 16.2 off end # - I2C 2 device pci 16.3 on end # - I2C 3 device pci 17.0 on end # - I2C 4 device pci 17.1 on end # - I2C 5 -- To view, visit https://review.coreboot.org/28016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc Gerrit-Change-Number: 28016 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1
by Furquan Shaikh (Code Review) 10 Aug '18

10 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28015 Change subject: mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1 ...................................................................... mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1 This change updates GPIO configuration for fleex boards with id >= 1 This follows the same model as phaser: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. d. Disable unused I2C devices in devicetree. BUG=b:112458032 TEST=No errors observed on boot-up on fleex. Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/octopus/variants/fleex/Makefile.inc A src/mainboard/google/octopus/variants/fleex/gpio.c A src/mainboard/google/octopus/variants/fleex/variant.c 3 files changed, 232 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/28015/1 diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc new file mode 100644 index 0000000..d54ed40 --- /dev/null +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c new file mode 100644 index 0000000..ac68569 --- /dev/null +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +static const struct pad_config default_override_table[] = { + + PAD_NC(GPIO_50, UP_20K), + PAD_NC(GPIO_51, UP_20K), + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + + /* CAM_SOC_EC_SYNC */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + DISPUPD), + + PAD_NC(GPIO_138, DN_20K), + PAD_NC(GPIO_139, DN_20K), + PAD_NC(GPIO_140, UP_20K), + PAD_NC(GPIO_143, UP_20K), + PAD_NC(GPIO_144, UP_20K), + PAD_NC(GPIO_145, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, UP_20K), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO(GPIO_178, 0, DEEP), + + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config bid0_override_table[] = { + PAD_NC(GPIO_50, UP_20K), + PAD_NC(GPIO_51, UP_20K), + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_138, DN_20K), + PAD_NC(GPIO_139, DN_20K), + PAD_NC(GPIO_140, UP_20K), + PAD_NC(GPIO_143, UP_20K), + PAD_NC(GPIO_144, UP_20K), + PAD_NC(GPIO_145, UP_20K), + PAD_NC(GPIO_161, UP_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + + switch (board_id()) { + case 0: + case UNDEFINED_STRAPPING_ID: + c = bid0_override_table; + *num = ARRAY_SIZE(bid0_override_table); + break; + default: + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + /* PCH_WP_OD */ + PAD_CFG_GPI(GPIO_190, NONE, DEEP), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + DISPUPD), + /* H1_SLAVE_SPI_CLK_R */ + PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_CS_L_R */ + PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MISO */ + PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), + + /* WLAN_PE_RST */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), + + /* + * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * pull-up for proper operation. Since there is no external pull present + * on this platform, configure an internal weak pull-up. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, + ENPU), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + /* + * This is a hack to configure EN_PP3300_WLAN based on board id. Once + * board id 0 is deprecated, we can get rid of this. + */ + uint32_t bid = board_id(); + + if (bid == UNDEFINED_STRAPPING_ID || bid < 1) + gpio_output(GPIO_178, 1); + else + gpio_output(GPIO_178, 0); + + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c new file mode 100644 index 0000000..9f587ae --- /dev/null +++ b/src/mainboard/google/octopus/variants/fleex/variant.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> +#include <drivers/i2c/generic/chip.h> +#include <drivers/i2c/hid/chip.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <string.h> + +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_hid_ops; + +static void update_touchscreen_gpio(void) +{ + uint32_t bid; + struct device *touchscreen_i2c_host; + struct device *child; + const struct bus *children_bus; + static const struct acpi_gpio new_enable_gpio = + ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146); + + bid = board_id(); + + /* Nothing to update. */ + if (bid == UNDEFINED_STRAPPING_ID || bid < 1) + return; + + touchscreen_i2c_host = dev_find_slot(0, PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + children_bus = touchscreen_i2c_host->link_list; + child = NULL; + + /* Find all children on bus to update touchscreen enable gpio. */ + while ((child = dev_bus_each_child(children_bus, child)) != NULL) { + struct drivers_i2c_generic_config *cfg; + + /* No configration to change. */ + if (child->chip_info == NULL) + continue; + + if (child->chip_ops == &drivers_i2c_generic_ops) + cfg = child->chip_info; + else if (child->chip_ops == &drivers_i2c_hid_ops) { + struct drivers_i2c_hid_config *hid_cfg; + hid_cfg = child->chip_info; + cfg = &hid_cfg->generic; + } else + continue; + + /* Update the enable gpio. */ + memcpy(&cfg->enable_gpio, &new_enable_gpio, + sizeof(new_enable_gpio)); + } +} + +static void disable_unused_devs(void) +{ + struct device *dev; + /* + * Even though I2C0 is unused, it cannot be disabled since it is PCI + * function 0 (16.0). + */ + unsigned int devfn[] = { PCH_DEVFN_I2C1 }; + size_t i; + + for (i = 0; i < ARRAY_SIZE(devfn); i++) { + dev = dev_find_slot(0, devfn[i]); + dev->enabled = 0; + } +} + +void variant_update_devtree(struct device *dev) +{ + update_touchscreen_gpio(); + disable_unused_devs(); +} -- To view, visit https://review.coreboot.org/28015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce Gerrit-Change-Number: 28015 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware paths
by Arthur Heymans (Code Review) 10 Aug '18

10 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28012 Change subject: mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware paths ...................................................................... mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware paths The paths defined in southbridge/intel/common/firmware/Kconfig should work just fine. Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/cannonlake_rvp/Kconfig 1 file changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/28012/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 3104331..028d493 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -41,11 +41,6 @@ string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config IFD_BIN_PATH - string - depends on HAVE_IFD_BIN - default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.bin" - config INCLUDE_SND_MAX98357_DA7219_NHLT bool "Include blobs for audio with MAX98357_DA7219" select DRIVERS_GENERIC_MAX98357A @@ -62,16 +57,6 @@ select NHLT_DMIC_2CH_16B select NHLT_MAX98373 -config ME_BIN_PATH - string - depends on HAVE_ME_BIN - default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.bin" - -config EC_BIN_PATH - string - depends on HAVE_EC_BIN - default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" - config DIMM_SPD_SIZE int default 512 -- To view, visit https://review.coreboot.org/28012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405 Gerrit-Change-Number: 28012 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/intel/broadwell/Kconfig: Clean up redefined config options
by Arthur Heymans (Code Review) 10 Aug '18

10 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28011 Change subject: soc/intel/broadwell/Kconfig: Clean up redefined config options ...................................................................... soc/intel/broadwell/Kconfig: Clean up redefined config options All broadwell board set HAVE_IFD_BIN to default n, overloading the option in soc, therefore just use the defaults in sb/intel/common/firmware. Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/jecht/Kconfig M src/mainboard/intel/wtm2/Kconfig M src/mainboard/purism/librem_bdw/Kconfig M src/soc/intel/broadwell/Kconfig 5 files changed, 0 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/28011/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 92dd9e4..ea0e01f 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -74,12 +74,4 @@ string default "pci8086,0406.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index e980205..0720375 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -55,12 +55,4 @@ string default "pci8086,0406.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 45a8666..25ffac3 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -35,12 +35,4 @@ string default "pci8086,0166.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif # BOARD_INTEL_WTM2 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 726fb4a..fd78087 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -37,14 +37,6 @@ config PCIEXP_AER def_bool n -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - config MAINBOARD_DIR string default purism/librem_bdw diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 1b1085a..32148c4 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -207,12 +207,6 @@ endif # HAVE_REFCODE_BLOB -config HAVE_ME_BIN - def_bool y - -config BUILD_WITH_FAKE_IFD - def_bool !HAVE_IFD_BIN - config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/broadwell/bootblock/timestamp.inc" -- To view, visit https://review.coreboot.org/28011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349 Gerrit-Change-Number: 28011 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/intel/braswell/Kconfig: Clean up redefined config options
by Arthur Heymans (Code Review) 10 Aug '18

10 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28010 Change subject: soc/intel/braswell/Kconfig: Clean up redefined config options ...................................................................... soc/intel/braswell/Kconfig: Clean up redefined config options HAVE_IFD_BIN and the likes are redefined in southbridge/intel/common/Kconfig which presents options under the 'Intel Firmware' section which gets sourced later than the 'southbridge' section therefore overriding this anyway. FAKE_IFD depends on out tree flashrom patches for which there are better alternatives available now, so don't build with FAKE_IFD by default. Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig 1 file changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/28010/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 23e5990..607d78c 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -120,15 +120,6 @@ configure the pads and enable it. This serial port can be used for the debug console. -config HAVE_IFD_BIN - def_bool n - -config BUILD_WITH_FAKE_IFD - def_bool !HAVE_IFD_BIN - -config HAVE_ME_BIN - def_bool n - config IED_REGION_SIZE hex default 0x400000 -- To view, visit https://review.coreboot.org/28010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834 Gerrit-Change-Number: 28010 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/lynxpoint: Don't build with FAKE_IFD by default
by Arthur Heymans (Code Review) 10 Aug '18

10 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28009 Change subject: sb/intel/lynxpoint: Don't build with FAKE_IFD by default ...................................................................... sb/intel/lynxpoint: Don't build with FAKE_IFD by default FAKE_IFD depends on out tree flashrom patches for which there are better alternatives available now, so don't build with FAKE_IFD by default. Change-Id: I21bc5bdc8b733fbfdb1b2a4fbcb572c76701074a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/lynxpoint/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/28009/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 4e5527a..ee870fc 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -57,10 +57,6 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. -config BUILD_WITH_FAKE_IFD - bool - default y if !HAVE_IFD_BIN - config ME_MBP_CLEAR_LATE bool "Defer wait for ME MBP Cleared" default y -- To view, visit https://review.coreboot.org/28009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I21bc5bdc8b733fbfdb1b2a4fbcb572c76701074a Gerrit-Change-Number: 28009 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/google/rambi: Don't set defaults for HAVE_IFD_BIN
by Arthur Heymans (Code Review) 10 Aug '18

10 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28008 Change subject: mb/google/rambi: Don't set defaults for HAVE_IFD_BIN ...................................................................... mb/google/rambi: Don't set defaults for HAVE_IFD_BIN There is no need set the default HAVE_IFD_BIN explicitly to n. Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/28008/1 diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 440276d..725d69d 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -109,12 +109,4 @@ string default "pci8086,0f31.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif # BOARD_GOOGLE_BASEBOARD_RAMBI -- To view, visit https://review.coreboot.org/28008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e Gerrit-Change-Number: 28008 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/lynxpoint/Kconfig: Clean up redefined config options
by Arthur Heymans (Code Review) 10 Aug '18

10 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28007 Change subject: sb/intel/lynxpoint/Kconfig: Clean up redefined config options ...................................................................... sb/intel/lynxpoint/Kconfig: Clean up redefined config options HAVE_IFD_BIN and the likes are redefined in southbridge/intel/common/Kconfig which presents options under the 'Intel Firmware' section which gets sourced later than the 'southbridge' section therefore overriding this anyway. Also all board using this target override HAVE_IFD_BIN to default n, so it is simpler to just use the defaults in southbridge/intel/common/firmware. Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/beltino/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 4 files changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/28007/1 diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 428db73..aaec9f7 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -65,12 +65,4 @@ string default "pci8086,0406.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index c43b713..6891c0b 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -73,12 +73,4 @@ string default "pci8086,0406.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 445dbcb..1fd07c2 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -37,12 +37,4 @@ string default "pci8086,0166.rom" -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - endif # BOARD_INTEL_BASKING_RIDGE diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 8d5cbbf..4e5527a 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -57,28 +57,10 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. -config HAVE_IFD_BIN - bool - default y - config BUILD_WITH_FAKE_IFD bool default y if !HAVE_IFD_BIN -config IFD_BIN_PATH - string - depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" - -config HAVE_ME_BIN - bool - default y - -config ME_BIN_PATH - string - depends on HAVE_ME_BIN - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" - config ME_MBP_CLEAR_LATE bool "Defer wait for ME MBP Cleared" default y -- To view, visit https://review.coreboot.org/28007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832 Gerrit-Change-Number: 28007 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/*/*/cmos.default: Decrease debug_level to 'Debug'
by Elyes HAOUAS (Code Review) 10 Aug '18

10 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28006 Change subject: mb/*/*/cmos.default: Decrease debug_level to 'Debug' ...................................................................... mb/*/*/cmos.default: Decrease debug_level to 'Debug' Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/cmos.default M src/mainboard/asrock/g41c-gs/cmos.default M src/mainboard/asus/am1i-a/cmos.default M src/mainboard/asus/kcma-d8/cmos.default M src/mainboard/asus/kfsn4-dre/cmos.default M src/mainboard/asus/kgpe-d16/cmos.default M src/mainboard/asus/m4a785t-m/cmos.default M src/mainboard/asus/maximus_iv_gene-z/cmos.default M src/mainboard/asus/p5gc-mx/cmos.default M src/mainboard/emulation/qemu-i440fx/cmos.default M src/mainboard/emulation/qemu-q35/cmos.default M src/mainboard/foxconn/g41s-k/cmos.default M src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default M src/mainboard/gigabyte/ga-g41m-es2l/cmos.default M src/mainboard/google/butterfly/cmos.default M src/mainboard/google/stout/cmos.default M src/mainboard/hp/2570p/cmos.default M src/mainboard/hp/2760p/cmos.default M src/mainboard/hp/8460p/cmos.default M src/mainboard/hp/8470p/cmos.default M src/mainboard/hp/8770w/cmos.default M src/mainboard/hp/compaq_8200_elite_sff/cmos.default M src/mainboard/hp/folio_9470m/cmos.default M src/mainboard/hp/pavilion_m6_1035dx/cmos.default M src/mainboard/hp/revolve_810_g1/cmos.default M src/mainboard/intel/d510mo/cmos.default M src/mainboard/intel/d945gclf/cmos.default M src/mainboard/intel/dg41wv/cmos.default M src/mainboard/intel/dg43gt/cmos.default M src/mainboard/intel/saddlebrook/cmos.default M src/mainboard/lenovo/l520/cmos.default M src/mainboard/lenovo/t400/cmos.default M src/mainboard/lenovo/t420/cmos.default M src/mainboard/lenovo/t420s/cmos.default M src/mainboard/lenovo/t430/cmos.default M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t530/cmos.default M src/mainboard/lenovo/t60/cmos.default M src/mainboard/lenovo/x131e/cmos.default M src/mainboard/lenovo/x1_carbon_gen1/cmos.default M src/mainboard/lenovo/x200/cmos.default M src/mainboard/lenovo/x201/cmos.default M src/mainboard/lenovo/x220/cmos.default M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x60/cmos.default M src/mainboard/lenovo/z61t/cmos.default M src/mainboard/packardbell/ms2290/cmos.default M src/mainboard/pcengines/alix1c/cmos.default M src/mainboard/pcengines/apu1/cmos.default M src/mainboard/sapphire/pureplatinumh61/cmos.default 51 files changed, 51 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28006/1 diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index dafd474..ad126ca 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/asrock/g41c-gs/cmos.default b/src/mainboard/asrock/g41c-gs/cmos.default index 1519fe1..8aa2238 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.default +++ b/src/mainboard/asrock/g41c-gs/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable gfx_uma_size=64M diff --git a/src/mainboard/asus/am1i-a/cmos.default b/src/mainboard/asus/am1i-a/cmos.default index dcacda6..53a5d35 100644 --- a/src/mainboard/asus/am1i-a/cmos.default +++ b/src/mainboard/asus/am1i-a/cmos.default @@ -1,4 +1,4 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug sata_mode=IDE sata_speed=6Gbps diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default index 5fa6a8d..28d1c58 100644 --- a/src/mainboard/asus/kcma-d8/cmos.default +++ b/src/mainboard/asus/kcma-d8/cmos.default @@ -1,4 +1,4 @@ -debug_level = Spew +debug_level=Debug multi_core = Enable slow_cpu = off compute_unit_siblings = Enable diff --git a/src/mainboard/asus/kfsn4-dre/cmos.default b/src/mainboard/asus/kfsn4-dre/cmos.default index f257088..022b783 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.default +++ b/src/mainboard/asus/kfsn4-dre/cmos.default @@ -1,4 +1,4 @@ -debug_level = Spew +debug_level=Debug multi_core = Enable slow_cpu = off hypertransport_speed_limit = Auto diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 3e7ed32..75226b1 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -1,4 +1,4 @@ -debug_level = Spew +debug_level=Debug multi_core = Enable slow_cpu = off compute_unit_siblings = Enable diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default index 4c2e807..bb2db49 100644 --- a/src/mainboard/asus/m4a785t-m/cmos.default +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -5,7 +5,7 @@ max_mem_clock=400Mhz multi_core=Enable power_on_after_fail=Disable -debug_level=Spew +debug_level=Debug slow_cpu=off nmi=Enable gart=Enable diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.default b/src/mainboard/asus/maximus_iv_gene-z/cmos.default index 9ddd107..d3812ab 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/cmos.default +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug gfx_uma_size=64M nmi=Enable power_on_after_fail=Disable diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default index d269afc..2cb37df 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.default +++ b/src/mainboard/asus/p5gc-mx/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.default b/src/mainboard/emulation/qemu-i440fx/cmos.default index 82e6fab..d34bc5a 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.default +++ b/src/mainboard/emulation/qemu-i440fx/cmos.default @@ -1,4 +1,4 @@ boot_option = Fallback power_on_after_fail = Enable -debug_level = Spew +debug_level=Debug ECC_memory = Disable diff --git a/src/mainboard/emulation/qemu-q35/cmos.default b/src/mainboard/emulation/qemu-q35/cmos.default index 82e6fab..d34bc5a 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.default +++ b/src/mainboard/emulation/qemu-q35/cmos.default @@ -1,4 +1,4 @@ boot_option = Fallback power_on_after_fail = Enable -debug_level = Spew +debug_level=Debug ECC_memory = Disable diff --git a/src/mainboard/foxconn/g41s-k/cmos.default b/src/mainboard/foxconn/g41s-k/cmos.default index 1519fe1..8aa2238 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.default +++ b/src/mainboard/foxconn/g41s-k/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable gfx_uma_size=64M diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default index d269afc..2cb37df 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default index 8d844bd..8372032 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Enable nmi=Enable gfx_uma_size=64M diff --git a/src/mainboard/google/butterfly/cmos.default b/src/mainboard/google/butterfly/cmos.default index d6789eb..ac98324 100644 --- a/src/mainboard/google/butterfly/cmos.default +++ b/src/mainboard/google/butterfly/cmos.default @@ -1,5 +1,5 @@ boot_option = Fallback -debug_level = Spew +debug_level=Debug nmi = Enable power_on_after_fail = Enable sata_mode = AHCI diff --git a/src/mainboard/google/stout/cmos.default b/src/mainboard/google/stout/cmos.default index d6789eb..ac98324 100644 --- a/src/mainboard/google/stout/cmos.default +++ b/src/mainboard/google/stout/cmos.default @@ -1,5 +1,5 @@ boot_option = Fallback -debug_level = Spew +debug_level=Debug nmi = Enable power_on_after_fail = Enable sata_mode = AHCI diff --git a/src/mainboard/hp/2570p/cmos.default b/src/mainboard/hp/2570p/cmos.default index fcbe0fb..ba33ddf 100644 --- a/src/mainboard/hp/2570p/cmos.default +++ b/src/mainboard/hp/2570p/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/hp/2760p/cmos.default b/src/mainboard/hp/2760p/cmos.default index fcbe0fb..ba33ddf 100644 --- a/src/mainboard/hp/2760p/cmos.default +++ b/src/mainboard/hp/2760p/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/hp/8460p/cmos.default b/src/mainboard/hp/8460p/cmos.default index fcbe0fb..ba33ddf 100644 --- a/src/mainboard/hp/8460p/cmos.default +++ b/src/mainboard/hp/8460p/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/hp/8470p/cmos.default b/src/mainboard/hp/8470p/cmos.default index fcbe0fb..ba33ddf 100644 --- a/src/mainboard/hp/8470p/cmos.default +++ b/src/mainboard/hp/8470p/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/hp/8770w/cmos.default b/src/mainboard/hp/8770w/cmos.default index ccdb7c8..ad822d5 100644 --- a/src/mainboard/hp/8770w/cmos.default +++ b/src/mainboard/hp/8770w/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable sata_mode=AHCI diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default index 1d88415..6d27a79 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Enable nmi=Enable sata_mode=AHCI diff --git a/src/mainboard/hp/folio_9470m/cmos.default b/src/mainboard/hp/folio_9470m/cmos.default index 7d4bb7b..455dc1cd 100644 --- a/src/mainboard/hp/folio_9470m/cmos.default +++ b/src/mainboard/hp/folio_9470m/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.default b/src/mainboard/hp/pavilion_m6_1035dx/cmos.default index 5031376..57286fd 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/cmos.default +++ b/src/mainboard/hp/pavilion_m6_1035dx/cmos.default @@ -1,4 +1,4 @@ boot_option = Fallback -debug_level = Spew +debug_level=Debug nmi = Disable power_on_after_fail = Disable diff --git a/src/mainboard/hp/revolve_810_g1/cmos.default b/src/mainboard/hp/revolve_810_g1/cmos.default index 7d4bb7b..455dc1cd 100644 --- a/src/mainboard/hp/revolve_810_g1/cmos.default +++ b/src/mainboard/hp/revolve_810_g1/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/intel/d510mo/cmos.default b/src/mainboard/intel/d510mo/cmos.default index 2b09000..41098be 100644 --- a/src/mainboard/intel/d510mo/cmos.default +++ b/src/mainboard/intel/d510mo/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable gfx_uma_size=8M diff --git a/src/mainboard/intel/d945gclf/cmos.default b/src/mainboard/intel/d945gclf/cmos.default index d269afc..2cb37df 100644 --- a/src/mainboard/intel/d945gclf/cmos.default +++ b/src/mainboard/intel/d945gclf/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/intel/dg41wv/cmos.default b/src/mainboard/intel/dg41wv/cmos.default index 1519fe1..8aa2238 100644 --- a/src/mainboard/intel/dg41wv/cmos.default +++ b/src/mainboard/intel/dg41wv/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable gfx_uma_size=64M diff --git a/src/mainboard/intel/dg43gt/cmos.default b/src/mainboard/intel/dg43gt/cmos.default index 0229e66..706f5dd 100644 --- a/src/mainboard/intel/dg43gt/cmos.default +++ b/src/mainboard/intel/dg43gt/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable sata_mode=AHCI diff --git a/src/mainboard/intel/saddlebrook/cmos.default b/src/mainboard/intel/saddlebrook/cmos.default index cd8bd47..3296093 100644 --- a/src/mainboard/intel/saddlebrook/cmos.default +++ b/src/mainboard/intel/saddlebrook/cmos.default @@ -1,4 +1,4 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default index 035fd94..979f132 100644 --- a/src/mainboard/lenovo/l520/cmos.default +++ b/src/mainboard/lenovo/l520/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 05c56d9..a326e31 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 3fae7c0..467f965 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 3fae7c0..467f965 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default index 60d9d5e..e65869b 100644 --- a/src/mainboard/lenovo/t430/cmos.default +++ b/src/mainboard/lenovo/t430/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default index 035fd94..979f132 100644 --- a/src/mainboard/lenovo/t430s/cmos.default +++ b/src/mainboard/lenovo/t430s/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 76852cf..6e61dae 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 76852cf..6e61dae 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default index 46a2831..d6479af 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/lenovo/x131e/cmos.default b/src/mainboard/lenovo/x131e/cmos.default index 616420a..b01978a 100644 --- a/src/mainboard/lenovo/x131e/cmos.default +++ b/src/mainboard/lenovo/x131e/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.default b/src/mainboard/lenovo/x1_carbon_gen1/cmos.default index 02f7c74..3044c6c 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.default +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default index a4555c2..bb43238 100644 --- a/src/mainboard/lenovo/x200/cmos.default +++ b/src/mainboard/lenovo/x200/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable volume=0x3 first_battery=Primary diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index df8e880..2cf484f 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default index 08c754b..42720a2 100644 --- a/src/mainboard/lenovo/x220/cmos.default +++ b/src/mainboard/lenovo/x220/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 035fd94..979f132 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable volume=0x3 diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 3a0c94c..f17d57c 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/lenovo/z61t/cmos.default b/src/mainboard/lenovo/z61t/cmos.default index 46a2831..d6479af 100644 --- a/src/mainboard/lenovo/z61t/cmos.default +++ b/src/mainboard/lenovo/z61t/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug hyper_threading=Enable nmi=Enable boot_devices='' diff --git a/src/mainboard/packardbell/ms2290/cmos.default b/src/mainboard/packardbell/ms2290/cmos.default index ccdb7c8..ad822d5 100644 --- a/src/mainboard/packardbell/ms2290/cmos.default +++ b/src/mainboard/packardbell/ms2290/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Disable nmi=Enable sata_mode=AHCI diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default index 6cbaa7c..da50263 100644 --- a/src/mainboard/pcengines/alix1c/cmos.default +++ b/src/mainboard/pcengines/alix1c/cmos.default @@ -1,4 +1,4 @@ boot_option=Fallback ECC_memory=Disable power_on_after_fail=Disable -debug_level=Spew +debug_level=Debug diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default index 57a2a8c..0906d5a 100644 --- a/src/mainboard/pcengines/apu1/cmos.default +++ b/src/mainboard/pcengines/apu1/cmos.default @@ -1,3 +1,3 @@ boot_option=Fallback multi_core=Enable -debug_level=Spew +debug_level=Debug diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.default b/src/mainboard/sapphire/pureplatinumh61/cmos.default index a313f68..579945d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.default +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.default @@ -1,5 +1,5 @@ boot_option=Fallback -debug_level=Spew +debug_level=Debug power_on_after_fail=Enable nmi=Enable volume=0x3 -- To view, visit https://review.coreboot.org/28006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198 Gerrit-Change-Number: 28006 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 10 Aug '18

10 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/27972/15/src/arch/riscv/trap_handler.c File src/arch/riscv/trap_handler.c: https://review.coreboot.org/#/c/27972/15/src/arch/riscv/trap_handler.c@191 PS15, Line 191: write_csr(sepc, read_csr(mepc)); 'sepc' may be misspelled - perhaps 'spec'? -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 15 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Fri, 10 Aug 2018 14:52:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018