coreboot-gerrit August 2018

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Change in coreboot[master]: update spell checker
by Xiang Wang (Code Review) 10 Aug '18

10 Aug '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/28005 ) Change subject: update spell checker ...................................................................... update spell checker RISC-V have a register named sepc. But spell checker think sepc is a misspelling. So fix. Change-Id: I7b092d6f04e28fba36095c607bc59346fb5c605d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M util/lint/spelling.txt 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28005/2 -- To view, visit https://review.coreboot.org/28005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7b092d6f04e28fba36095c607bc59346fb5c605d Gerrit-Change-Number: 28005 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: update spell checker
by Xiang Wang (Code Review) 10 Aug '18

10 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28005 Change subject: update spell checker ...................................................................... update spell checker RISC-V have a register named sepc. But spell checker think sepc is a misspelling. So fix. Change-Id: I7b092d6f04e28fba36095c607bc59346fb5c605d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M util/lint/spelling.txt 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28005/1 diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 400ef35..4b67069 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -993,7 +993,6 @@ sentivite||sensitive separatly||separately sepcify||specify -sepc||spec seperated||separated seperately||separately seperate||separate -- To view, visit https://review.coreboot.org/28005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7b092d6f04e28fba36095c607bc59346fb5c605d Gerrit-Change-Number: 28005 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: [HACK]cavium/cn81xx/soc: Don't advertise CAR area as usable
by Patrick Rudolph (Code Review) 10 Aug '18

10 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28003 Change subject: [HACK]cavium/cn81xx/soc: Don't advertise CAR area as usable ...................................................................... [HACK]cavium/cn81xx/soc: Don't advertise CAR area as usable It's broken. Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/soc.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/28003/1 diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 9dbbcbf..b575ca4 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -314,7 +314,8 @@ static void soc_read_resources(device_t dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB); + // HACK: Don't advertise bootblock romstage CAR region, it's broken... + ram_resource(dev, 0, 2 * KiB, sdram_size_mb() * KiB - 2 * KiB); } static void soc_init_atf(void) -- To view, visit https://review.coreboot.org/28003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b Gerrit-Change-Number: 28003 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: lib/fit: support booting initrd placed above 4GiB
by Patrick Rudolph (Code Review) 10 Aug '18

10 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28002 Change subject: lib/fit: support booting initrd placed above 4GiB ...................................................................... lib/fit: support booting initrd placed above 4GiB Store initrd offset as 64bit integer. Tested on Cavium CN81XX EVB: The initrd could be loaded when placed above 4GiB. Previously it failed to find the initrd. Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/device_tree.h M src/lib/device_tree.c M src/lib/fit.c 3 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28002/1 diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 7f725e4..4c1a37c 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -158,6 +158,7 @@ size_t size); void dt_add_string_prop(struct device_tree_node *node, const char *name, char *str); void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val); +void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val); void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes, int count, u32 addr_cells, u32 size_cells); int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path, diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 00b36fd..df6cb11 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -882,6 +882,22 @@ } /* + * Add a 64-bit integer property to a node, or update it if it already exists. + * + * @param node The device tree node to add to. + * @param name The name of the new property. + * @param val The integer to be stored in the property. + */ +void dt_add_u64_prop(struct device_tree_node *node, const char *name, u64 val) +{ + u64 *val_ptr = malloc(sizeof(val)); + if (!val_ptr) + return; + *val_ptr = htobe64(val); + dt_add_bin_prop(node, name, val_ptr, sizeof(*val_ptr)); +} + +/* * Add a 'reg' address list property to a node, or update it if it exists. * * @param node The device tree node to add to. diff --git a/src/lib/fit.c b/src/lib/fit.c index fe8a82e..68f5bed 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -212,12 +212,11 @@ struct device_tree_node *node; node = dt_find_node(tree->root, path, NULL, NULL, 1); - /* Warning: this assumes the ramdisk is currently located below 4GiB. */ - u32 start = (uintptr_t)ramdisk_addr; - u32 end = start + ramdisk_size; + u64 start = (uintptr_t)ramdisk_addr; + u64 end = start + ramdisk_size; - dt_add_u32_prop(node, "linux,initrd-start", start); - dt_add_u32_prop(node, "linux,initrd-end", end); + dt_add_u64_prop(node, "linux,initrd-start", start); + dt_add_u64_prop(node, "linux,initrd-end", end); } static void update_reserve_map(uint64_t start, uint64_t end, -- To view, visit https://review.coreboot.org/28002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab Gerrit-Change-Number: 28002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: intel/apollolake: Fix typo in dptf.asl
by Chris Zhou (Code Review) 10 Aug '18

10 Aug '18

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/28001 Change subject: intel/apollolake: Fix typo in dptf.asl ...................................................................... intel/apollolake: Fix typo in dptf.asl Fix define typo in dptf.asl BUG=none TEST=emerge-octopus coreboot PASS Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> --- M src/soc/intel/apollolake/acpi/dptf.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28001/1 diff --git a/src/soc/intel/apollolake/acpi/dptf.asl b/src/soc/intel/apollolake/acpi/dptf.asl index 743fa92..b9ba9c3 100644 --- a/src/soc/intel/apollolake/acpi/dptf.asl +++ b/src/soc/intel/apollolake/acpi/dptf.asl @@ -16,7 +16,7 @@ #define DPTF_CPU_DEVICE TCPU #ifndef DPTF_CPU_PASSIVE -#definie DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_PASSIVE 80 #endif #ifndef DPTF_CPU_CRITICAL -- To view, visit https://review.coreboot.org/28001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a Gerrit-Change-Number: 28001 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com>

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Change in coreboot[master]: util/bincfg: don't use sym_table shared variable
by Paul Kocialkowski (Code Review) 10 Aug '18

10 Aug '18

Paul Kocialkowski has posted comments on this change. ( https://review.coreboot.org/27810 ) Change subject: util/bincfg: don't use sym_table shared variable ...................................................................... Patch Set 2: The commit message doesn't explain the rationale behind the change. Also, maybe use a capital letter after the final ":". -- To view, visit https://review.coreboot.org/27810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I652a8da75498f871a53eb7509f6145c4842e3373 Gerrit-Change-Number: 27810 Gerrit-PatchSet: 2 Gerrit-Owner: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 10 Aug 2018 09:24:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: select TPM2 option
by Michał Żygowski (Code Review) 10 Aug '18

10 Aug '18

Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/28000 ) Change subject: src/mainboard/pcengines/apu2/Kconfig: select TPM2 option ...................................................................... src/mainboard/pcengines/apu2/Kconfig: select TPM2 option Apu2 boards use Infineon SLB9665 TT 2.0 module which is TPM2.0. Select TPM2 to properly initialize the TPM. SLB9665 TT 2.0 detection fixed in: https://review.coreboot.org/#/c/coreboot/+/21983/ Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28000/2 -- To view, visit https://review.coreboot.org/28000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Gerrit-Change-Number: 28000 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: select TPM2 option
by Michał Żygowski (Code Review) 10 Aug '18

10 Aug '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/28000 Change subject: src/mainboard/pcengines/apu2/Kconfig: select TPM2 option ...................................................................... src/mainboard/pcengines/apu2/Kconfig: select TPM2 option Apu2 boards use Infineon SLB9665 TT 2.0 module which is TPM2.0. Select TPM2 to properly initialize the TPM. SLB9665 TT 2.0 detection fixed in: https://review.coreboot.org/#/c/coreboot/+/21983/ Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28000/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index af14066..f87db52 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -32,7 +32,7 @@ select USE_BLOBS select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 + select MAINBOARD_HAS_TPM2 config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/28000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Gerrit-Change-Number: 28000 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 10 Aug '18

10 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/27972/12/src/arch/riscv/fp_asm.S File src/arch/riscv/fp_asm.S: https://review.coreboot.org/#/c/27972/12/src/arch/riscv/fp_asm.S@16 PS12, Line 16: #if defined(__riscv_flen) trailing whitespace -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 12 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Fri, 10 Aug 2018 08:42:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: update misaligned memory access exception handling
by build bot (Jenkins) (Code Review) 10 Aug '18

10 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 ) Change subject: riscv: update misaligned memory access exception handling ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/27972/10/src/arch/riscv/misaligend.c File src/arch/riscv/misaligend.c: https://review.coreboot.org/#/c/27972/10/src/arch/riscv/misaligend.c@251 PS10, Line 251: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/27972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Gerrit-Change-Number: 27972 Gerrit-PatchSet: 10 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich (1001188) Gerrit-Comment-Date: Fri, 10 Aug 2018 08:11:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018