coreboot-gerrit August 2018

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Change in coreboot[master]: eve: Add PL1 override to 7W
by Lucas Chen (Code Review) 14 Aug '18

14 Aug '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/28078 Change subject: eve: Add PL1 override to 7W ...................................................................... eve: Add PL1 override to 7W Base on thermal test result, Change PL1 from 4.5w to 7W. BRANCH=eve BUG=b:73133864 TEST=Verify the MSR PL1 limitation is set to 7W. Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/28078/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 16bfc47..ae69c45 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -240,6 +240,7 @@ register "speed_shift_enable" = "1" register "dptf_enable" = "1" + register "tdp_pl1_override" = "7" register "tdp_pl2_override" = "15" register "tcc_offset" = "10" -- To view, visit https://review.coreboot.org/28078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad Gerrit-Change-Number: 28078 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: eve: move DPTF DTRT table to the root scope
by Lucas Chen (Code Review) 14 Aug '18

14 Aug '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/28077 Change subject: eve: move DPTF DTRT table to the root scope ...................................................................... eve: move DPTF DTRT table to the root scope Non-cros DPTF policies require absolute name references in the _TRT method. However, coreboot compiles ASL code with name reference optimization enabled, which turns absolute name references to relative name references. That said, the \_SB prefix of the entries in DTRT will be removed. For example, \_SB.PCI0.B0D4 in DTRT will be optimized to PCI0.B0D4 since DTRT is under the \_SB scope. In order to keep the absolute name ref, the DTRT table is moved to the root scope. BRANCH=eve BUG=b:73133864 TEST=Install DPTF UI and check the nodes in passive policy are valid Change-Id: I6a4a5fd5da3a639c611bd4cb45d2cf6e9cba9397 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/eve/acpi/dptf.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl 2 files changed, 19 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28077/1 diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl index 7dd4249..3d840b4 100644 --- a/src/mainboard/google/eve/acpi/dptf.asl +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -48,28 +48,30 @@ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ }) -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, +Scope(\) { + Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Effect on Ambient */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + /* CPU Effect on Ambient */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - /* CPU Effect on Charger */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 }, + /* CPU Effect on Charger */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 }, - /* CPU Effect on DRAM */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + /* CPU Effect on DRAM */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, - /* CPU Effect on eMMC */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 }, + /* CPU Effect on eMMC */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 }, - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - /* Charger Throttle Effect on eMMC (TSR3) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, -}) + /* Charger Throttle Effect on eMMC (TSR3) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, + }) +} Name (MPPC, Package () { diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 61f982c..98e302c 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -73,7 +73,7 @@ Method (_TRT) { - Return (\_SB.DTRT) + Return (\DTRT) } #ifdef DPTF_ENABLE_FAN_CONTROL -- To view, visit https://review.coreboot.org/28077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6a4a5fd5da3a639c611bd4cb45d2cf6e9cba9397 Gerrit-Change-Number: 28077 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Wei Shun Chang <wei.shun.chang(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable
by Furquan Shaikh (Code Review) 14 Aug '18

14 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28076 ) Change subject: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Gerrit-Change-Number: 28076 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 07:01:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: sx9310 to 400kb
by Furquan Shaikh (Code Review) 14 Aug '18

14 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28075 ) Change subject: mb/google/poppy/variants/nocturne: sx9310 to 400kb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Gerrit-Change-Number: 28075 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 07:01:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Lijian Zhao (Code Review) 14 Aug '18

14 Aug '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28073 ) Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... Patch Set 1: > Patch Set 1: > > (1 comment) _PR3 will Returns a list of dependent power resources to enter state D3hot. In this case, that means the _OFF in power resource will be called when transit into to D3hot state. Also the following line copied from ACPI spec chapter 7.3 • If there exists an ACPI Object to set a device to D0 (either through _PSx or _PRx objects), then the corresponding object to set the device into a deeper Dx must also be declared, and vice versa. -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 06:57:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block/cpu: add function to init cppc_config
by Patrick Rudolph (Code Review) 14 Aug '18

14 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28068 ) Change subject: soc/intel/common/block/cpu: add function to init cppc_config ...................................................................... Patch Set 3: Why don't you put it into src/cpu/intel ? It looks like version 2 could be used on all Intel CPUs in tree. -- To view, visit https://review.coreboot.org/28068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Gerrit-Change-Number: 28068 Gerrit-PatchSet: 3 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 06:27:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Matt Delco has posted comments on this change. ( https://review.coreboot.org/28073 ) Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28073/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28073/1//COMMIT_MSG@9 PS1, Line 9: This means that we're : telling the OS that the cams need power in both D0 and D3 (and not the : intermediate states) > I don't think that's how OSPM to determine the power needed or not in D3 state. […] My understanding is that the _PR3 means the devices will have power in D3hot. Prior to this change the device would have power in D0 and D3hot, but not D1, D2, or D3cold. After this change only D0 will have power. All the cam devices I can find outside of coreboot have a _PR0 but not a _PR3. It seems more appropriate to remove the _PR3 than add a _PR2 (and probably also a "Name(_S0W, 4)" to make Windows think it's okay to transition the device to D3cold). -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 04:54:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28076 Change subject: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable ...................................................................... mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable This file contains two instances of "dptf_enable" = "1". This chanes removes the 2nd instance (it doesn't have an explicit comment like the 1st instance). The dptf devices still seem to be present even with this change, as expected. Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28076/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4fbd0ff..88af929 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -61,7 +61,6 @@ # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" - register "dptf_enable" = "1" register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" -- To view, visit https://review.coreboot.org/28076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Gerrit-Change-Number: 28076 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: sx9310 to 400kb
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28075 Change subject: mb/google/poppy/variants/nocturne: sx9310 to 400kb ...................................................................... mb/google/poppy/variants/nocturne: sx9310 to 400kb The spec of the sx9310 says the I2C interface can handle standard (100kb/s) and fast mode (400kb/s). The current setting is using fast plus (1000kb/s) so this change is reducing the speed to fast mode. I've been using the sensors with this change for a few weeks now, though I also don't recall seeing an issue prior to this change. Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28075/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2c074e9..4fbd0ff 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -298,7 +298,7 @@ chip drivers/i2c/sx9310 register "desc" = ""Right SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" - register "speed" = "I2C_SPEED_FAST_PLUS" + register "speed" = "I2C_SPEED_FAST" register "uid" = "0" register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" @@ -339,7 +339,7 @@ chip drivers/i2c/sx9310 register "desc" = ""Left SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" - register "speed" = "I2C_SPEED_FAST_PLUS" + register "speed" = "I2C_SPEED_FAST" register "uid" = "1" register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" -- To view, visit https://review.coreboot.org/28075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Gerrit-Change-Number: 28075 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: Revert "mb/google/poppy/variants/atlas: enable camera power and relea...
by Ping-chung Chen (Code Review) 14 Aug '18

14 Aug '18

Ping-chung Chen has posted comments on this change. ( https://review.coreboot.org/28072 ) Change subject: Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/28072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Gerrit-Change-Number: 28072 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 02:54:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit August 2018