Kane Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/28074 )
Change subject: soc/intel/skylake: Disable usb2 phy power gating.
......................................................................
soc/intel/skylake: Disable usb2 phy power gating.
Currently, we found the usb2 phy registers value are restored to soc
default after xhci PS3, PS0 are executed.
This will cause some usb 2.0 devices not detected after xhci resumes
from D3.
Before root cause, this patch temporarily disables the usb2 phy power
gating in xhci PS0 PS3 so that usb2phy registers won't be restored to
soc default.
BUG=b:110175562
TEST=check usb2 phy registers are not restore to soc default.
Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d
Signed-off-by: Kane Chen <kane.chen(a)intel.com>
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 0 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28074/2
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Gerrit-Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d
Gerrit-Change-Number: 28074
Gerrit-PatchSet: 2
Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>
Kane Chen has uploaded this change for review. ( https://review.coreboot.org/28074
Change subject: soc/intel/skylake: Disable usb2 phy power gating.
......................................................................
soc/intel/skylake: Disable usb2 phy power gating.
Currently, we found the usb2 phy registers value are restored to soc
default after xhci PS3, PS0 are executed.
This will cause some usb 2.0 devices not detected after xhci resumes
from D3.
Before root cause, this patch temporarily disables the usb2 phy power
gating in xhci PS0 PS3 so that usb2phy registers won't be restored to
soc default.
BUG=b:110175562
TEST=check usb2 phy registers are not gone.
Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d
Signed-off-by: Kane Chen <kane.chen(a)intel.com>
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 0 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28074/1
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 29367de..926f6ac 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -149,24 +149,6 @@
/* Disable USB2 PHY SUS Well Power Gating */
Store (Zero, ^UPSW)
-
- /*
- * Apply USB2 PHPY Power Gating workaround if needed.
- */
- If (^^PMC.UWAB) {
- /* Write to MTPMC to have PMC disable power gating */
- Store (1, ^^PMC.MPMC)
-
- /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
- Store (10, Local0)
- While (^^PMC.PMFS) {
- If (LNot (Local0)) {
- Break
- }
- Decrement (Local0)
- Sleep (10)
- }
- }
}
Method (_PS3, 0, Serialized)
@@ -202,26 +184,6 @@
Store (3, Local0)
Store (Local0, ^D0D3)
Store (^D0D3, Local0)
-
- /*
- * Apply USB2 PHPY Power Gating workaround if needed.
- * This code assumes XDCI is disabled, if it is enabled
- * then this must also check if it is in D3 state too.
- */
- If (^^PMC.UWAB) {
- /* Write to MTPMC to have PMC enable power gating */
- Store (3, ^^PMC.MPMC)
-
- /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */
- Store (10, Local0)
- While (^^PMC.PMFS) {
- If (LNot (Local0)) {
- Break
- }
- Decrement (Local0)
- Sleep (10)
- }
- }
}
/* Root Hub for Skylake-LP PCH */
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Gerrit-Change-Id: I3e4846aa9500930da964c2b10473dc98f021da8d
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Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>
Felix Held has posted comments on this change. ( https://review.coreboot.org/28064 )
Change subject: src: Remove duplicated 'include <device/device.h>'
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-Comment-Date: Tue, 14 Aug 2018 01:13:55 +0000
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28059 )
Change subject: soc/amd/stoneyridge: Add bootblock_fch_init
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/28059/2/src/soc/amd/stoneyridge/southbridge…
File src/soc/amd/stoneyridge/southbridge.c:
https://review.coreboot.org/#/c/28059/2/src/soc/amd/stoneyridge/southbridge…
PS2, Line 648: {}
Very nitty, but I think most of coreboot does functions' braces on their own lines, excepting inline and weak functions. Given that this is here solely for the purpose of filling it, I'm not sure that I care much.
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Gerrit-Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8
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Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
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Gerrit-Comment-Date: Tue, 14 Aug 2018 00:44:44 +0000
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Hello Tomasz Figa, caveh jalali, Ping-chung Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/28072
to look at the new patch set (#3).
Change subject: Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"
......................................................................
Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"
This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4.
Camera power is now handled by ACPI rules - no need to force the GPIOs
on by default.
BUG=b:80106316,b:111141128
Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
---
M src/mainboard/google/poppy/variants/atlas/gpio.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28072/3
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Gerrit-PatchSet: 3
Gerrit-Owner: Caveh Jalali <caveh(a)google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
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