coreboot-gerrit August 2018

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Change in coreboot[master]: vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove VENDORCODE_FULL_SUPPORT
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28091 Change subject: vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove VENDORCODE_FULL_SUPPORT ...................................................................... vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove VENDORCODE_FULL_SUPPORT Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Lib/amdlib.c 1 file changed, 0 insertions(+), 654 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/28091/1 diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c index 784ba46..7181d1d 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c @@ -61,18 +61,6 @@ IN AMD_CONFIG_PARAMS *StdHeader ); -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -VOID -STATIC -LibAmdGetDataFromPtr ( - IN ACCESS_WIDTH AccessWidth, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - OUT UINT32 *TemData, - OUT UINT32 *TempDataMask - ); -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - VOID IdsOutPort ( IN UINT32 Addr, @@ -277,123 +265,6 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -AMDLIB_OPTIMIZE -VOID -LibAmdReadCpuReg ( - IN UINT8 RegNum, - OUT UINT32 *Value - ) -{ - *Value = 0; - switch (RegNum){ - case CR4_REG: - *Value = __readcr4 (); - break; - case DR0_REG: - *Value = __readdr (0); - break; - case DR1_REG: - *Value = __readdr (1); - break; - case DR2_REG: - *Value = __readdr (2); - break; - case DR3_REG: - *Value = __readdr (3); - break; - case DR7_REG: - *Value = __readdr (7); - break; - default: - *Value = -1; - break; - } -} - -AMDLIB_OPTIMIZE -VOID -LibAmdWriteCpuReg ( - IN UINT8 RegNum, - IN UINT32 Value - ) -{ - switch (RegNum){ - case CR4_REG: - __writecr4 (Value); - break; - case DR0_REG: - __writedr (0, Value); - break; - case DR1_REG: - __writedr (1, Value); - break; - case DR2_REG: - __writedr (2, Value); - break; - case DR3_REG: - __writedr (3, Value); - break; - case DR7_REG: - __writedr (7, Value); - break; - default: - break; - } -} - -AMDLIB_OPTIMIZE -VOID -LibAmdWriteBackInvalidateCache ( - void - ) -{ - __wbinvd (); -} - -AMDLIB_OPTIMIZE -VOID -LibAmdHDTBreakPoint ( - void - ) -{ - __writemsr (0xC001100A, __readmsr (0xC001100A) | 1); - __debugbreak (); // do you really need icebp? If so, go back to asm code -} - -AMDLIB_OPTIMIZE -UINT8 -LibAmdBitScanForward ( - IN UINT32 value - ) -{ - UINTN Index; - for (Index = 0; Index < 32; Index++){ - if (value & (1 << Index)) break; - } - return (UINT8) Index; -} - -AMDLIB_OPTIMIZE -UINT8 -LibAmdBitScanReverse ( - IN UINT32 value -) -{ - uint8_t bit = 31; - do { - if (value & (1 << 31)) - return bit; - - value <<= 1; - bit--; - - } while (value != 0); - - return 0xFF; /* Error code indicating no bit found */ -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - AMDLIB_OPTIMIZE VOID LibAmdMsrRead ( @@ -419,93 +290,6 @@ __writemsr (MsrAddress, *Value); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -AMDLIB_OPTIMIZE -void LibAmdCpuidRead ( - IN UINT32 CpuidFcnAddress, - OUT CPUID_DATA* Value, - IN OUT AMD_CONFIG_PARAMS *ConfigPtr - ) -{ - __cpuid ((int *)Value, CpuidFcnAddress); -} - -AMDLIB_OPTIMIZE -UINT64 -ReadTSC ( - void - ) -{ - return __rdtsc (); -} - -AMDLIB_OPTIMIZE -VOID -LibAmdSimNowEnterDebugger ( - void - ) -{ - STATIC CONST UINT8 opcode [] = {0x60, // pushad - 0xBB, 0x02, 0x00, 0x00, 0x00, // mov ebx, 2 - 0xB8, 0x0B, 0xD0, 0xCC, 0xBA, // mov eax, 0xBACCD00B - 0x0F, 0xA2, // cpuid - 0x61, // popad - 0xC3 // ret - }; - ((VOID (*)(VOID)) (size_t) opcode) (); // call the function -} - -AMDLIB_OPTIMIZE -VOID -IdsOutPort ( - IN UINT32 Addr, - IN UINT32 Value, - IN UINT32 Flag - ) -{ - __outdword ((UINT16) Addr, Value); -} - -AMDLIB_OPTIMIZE -VOID -StopHere ( - void - ) -{ - VOLATILE UINTN x = 1; - while (x); -} - -AMDLIB_OPTIMIZE -VOID -LibAmdCLFlush ( - IN UINT64 Address, - IN UINT8 Count - ) -{ - UINT64 hwcrSave; - UINT8 *address32; - UINTN Index; - address32 = 0; - hwcrSave = SetFsBase (Address); - for (Index = 0; Index < Count; Index++){ - _mm_mfence (); - _mm_clflush_fs (&address32 [Index * 64]); - } - RestoreHwcr (hwcrSave); -} - - -AMDLIB_OPTIMIZE -VOID -LibAmdFinit( - void - ) -{ - /* TODO: finit */ - __asm__ volatile ("finit"); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ /*---------------------------------------------------------------------------------------*/ /** * Read IO port @@ -582,41 +366,6 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*---------------------------------------------------------------------------------------*/ -/** - * Poll IO register - * - * Poll register until (RegisterValue & DataMask) == Data - * - * @param[in] AccessWidth Access width - * @param[in] IoAddress IO address - * @param[in] Data Data to compare - * @param[in] DataMask And mask - * @param[in] Delay Poll for time in 100ns (not supported) - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdIoPoll ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN UINT64 Delay, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempData; - UINT32 TempMask; - UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - do { - LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL); - } while (TempData != (Value & TempMask)); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /*---------------------------------------------------------------------------------------*/ /** * Read memory/MMIO @@ -694,41 +443,6 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*---------------------------------------------------------------------------------------*/ -/** - * Poll Mmio - * - * Poll register until (RegisterValue & DataMask) == Data - * - * @param[in] AccessWidth Access width - * @param[in] MemAddress Memory address - * @param[in] Data Data to compare - * @param[in] DataMask AND mask - * @param[in] Delay Poll for time in 100ns (not supported) - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdMemPoll ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN UINT64 Delay, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempData = 0; - UINT32 TempMask = 0; - UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - do { - LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL); - } while (TempData != (Value & TempMask)); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /*---------------------------------------------------------------------------------------*/ /** * Read PCI config space @@ -835,41 +549,6 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*---------------------------------------------------------------------------------------*/ -/** - * Poll PCI config space register - * - * Poll register until (RegisterValue & DataMask) == Data - * - * @param[in] AccessWidth Access width - * @param[in] PciAddress Pci address - * @param[in] Data Data to compare - * @param[in] DataMask AND mask - * @param[in] Delay Poll for time in 100ns (not supported) - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdPciPoll ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN UINT64 Delay, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempData = 0; - UINT32 TempMask = 0; - UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - do { - LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL); - } while (TempData != (Value & TempMask)); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /*---------------------------------------------------------------------------------------*/ /** * Get MMIO base address for PCI accesses @@ -903,207 +582,6 @@ return MmioIsEnabled; } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*---------------------------------------------------------------------------------------*/ -/** - * Read field of PCI config register. - * - * - * - * @param[in] Address Pci address (register must be DWORD aligned) - * @param[in] Highbit High bit position of the field in DWORD - * @param[in] Lowbit Low bit position of the field in DWORD - * @param[out] Value Pointer to data - * @param[in] StdHeader Standard configuration header - */ -VOID -LibAmdPciReadBits ( - IN PCI_ADDR Address, - IN UINT8 Highbit, - IN UINT8 Lowbit, - OUT UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); - - LibAmdPciRead (AccessWidth32, Address, Value, NULL); - *Value >>= Lowbit; // Shift - - // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case - - if ((Highbit - Lowbit) != 31) { - *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Write field of PCI config register. - * - * - * - * @param[in] Address Pci address (register must be DWORD aligned) - * @param[in] Highbit High bit position of the field in DWORD - * @param[in] Lowbit Low bit position of the field in DWORD - * @param[in] Value Pointer to data - * @param[in] StdHeader Standard configuration header - */ -VOID -LibAmdPciWriteBits ( - IN PCI_ADDR Address, - IN UINT8 Highbit, - IN UINT8 Lowbit, - IN CONST UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Temp; - UINT32 Mask; - - ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); - - // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case - - if ((Highbit - Lowbit) != 31) { - Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); - } else { - Mask = (UINT32) 0xFFFFFFFF; - } - - LibAmdPciRead (AccessWidth32, Address, &Temp, NULL); - Temp &= ~(Mask << Lowbit); - Temp |= (*Value & Mask) << Lowbit; - LibAmdPciWrite (AccessWidth32, Address, &Temp, NULL); -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Locate next capability pointer - * - * Given a SBDFO this routine will find the next PCI capabilities list entry. - * if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is - * returned. - * To start a new search from the head of the list, specify a SBDFO with an offset of zero. - * - * @param[in,out] Address Pci address - * @param[in] StdHeader Standard configuration header - */ - -VOID -LibAmdPciFindNextCap ( - IN OUT PCI_ADDR *Address, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR Base; - UINT32 Offset; - UINT32 Temp; - PCI_ADDR TempAddress; - - ASSERT (Address != NULL); - ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO); - - Base.AddressValue = Address->AddressValue; - Offset = Base.Address.Register; - Base.Address.Register = 0; - - Address->AddressValue = (UINT32) ILLEGAL_SBDFO; - - // Verify that the SBDFO points to a valid PCI device SANITY CHECK - LibAmdPciRead (AccessWidth32, Base, &Temp, NULL); - if (Temp == 0xFFFFFFFF) { - ASSERT (FALSE); - return; // There is no device at this address - } - - // Verify that the device supports a capability list - TempAddress.AddressValue = Base.AddressValue + 0x04; - LibAmdPciReadBits (TempAddress, 20, 20, &Temp, NULL); - if (Temp == 0) { - return; // This PCI device does not support capability lists - } - - if (Offset != 0) { - // If we are continuing on an existing list - TempAddress.AddressValue = Base.AddressValue + Offset; - LibAmdPciReadBits (TempAddress, 15, 8, &Temp, NULL); - } else { - // We are starting on a new list - TempAddress.AddressValue = Base.AddressValue + 0x34; - LibAmdPciReadBits (TempAddress, 7, 0, &Temp, NULL); - } - - if (Temp == 0) { - return; // We have reached the end of the capabilities list - } - - // Error detection and recovery- The statement below protects against - // PCI devices with broken PCI capabilities lists. Detect a pointer - // that is not uint32 aligned, points into the first 64 reserved DWORDs - // or points back to itself. - if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) { - ASSERT (FALSE); - return; - } - - Address->AddressValue = Base.AddressValue + Temp; - return; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Set memory with value - * - * - * @param[in,out] Destination Pointer to memory range - * @param[in] Value Value to set memory with - * @param[in] FillLength Size of the memory range - * @param[in] StdHeader Standard configuration header (Optional) - */ -VOID -LibAmdMemFill ( - IN VOID *Destination, - IN UINT8 Value, - IN UINTN FillLength, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *Dest; - Dest = Destination; - while ((FillLength--) != 0) { - *Dest++ = Value; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Copy memory - * - * - * @param[in,out] Destination Pointer to destination buffer - * @param[in] Source Pointer to source buffer - * @param[in] CopyLength buffer length - * @param[in] StdHeader Standard configuration header (Optional) - */ -VOID -LibAmdMemCopy ( - IN VOID *Destination, - IN CONST VOID *Source, - IN UINTN CopyLength, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 *Dest; - CONST UINT8 *SourcePtr; - Dest = Destination; - SourcePtr = Source; - while ((CopyLength--) != 0) { - *Dest++ = *SourcePtr++; - } -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /*---------------------------------------------------------------------------------------*/ /** * Verify checksum of binary image (B1/B2/B3) @@ -1187,138 +665,6 @@ return NULL; } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the package type mask for the processor - * - * - * @param[in] StdHeader Standard configuration header (Optional) - */ - -// Returns the package type mask for the processor -UINT32 -LibAmdGetPackageType ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 ProcessorPackageType; - CPUID_DATA CpuId; - - LibAmdCpuidRead (0x80000001, &CpuId, NULL); - ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - return (UINT32) (1 << ProcessorPackageType); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the package type mask for the processor - * - * - * @param[in] AccessWidth Access width - * @param[in] Data data - * @param[in] DataMask data - * @param[out] TemData typecast data - * @param[out] TempDataMask typecast data - */ - -VOID -STATIC -LibAmdGetDataFromPtr ( - IN ACCESS_WIDTH AccessWidth, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - OUT UINT32 *TemData, - OUT UINT32 *TempDataMask - ) -{ - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - *TemData = (UINT32)*(UINT8 *) Data; - *TempDataMask = (UINT32)*(UINT8 *) DataMask; - break; - case AccessWidth16: - case AccessS3SaveWidth16: - *TemData = (UINT32)*(UINT16 *) Data; - *TempDataMask = (UINT32)*(UINT16 *) DataMask; - break; - case AccessWidth32: - case AccessS3SaveWidth32: - *TemData = *(UINT32 *) Data; - *TempDataMask = *(UINT32 *) DataMask; - break; - default: - IDS_ERROR_TRAP; - break; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the package type mask for the processor - * - * - * @param[in] AccessWidth Access width - * @retval Width in number of bytes - */ - -UINT8 -LibAmdAccessWidth ( - IN ACCESS_WIDTH AccessWidth - ) -{ - UINT8 Width; - - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - Width = 1; - break; - case AccessWidth16: - case AccessS3SaveWidth16: - Width = 2; - break; - case AccessWidth32: - case AccessS3SaveWidth32: - Width = 4; - break; - case AccessWidth64: - case AccessS3SaveWidth64: - Width = 8; - break; - default: - Width = 0; - IDS_ERROR_TRAP; - break; - } - return Width; -} - -AMDLIB_OPTIMIZE -VOID -CpuidRead ( - IN UINT32 CpuidFcnAddress, - OUT CPUID_DATA *Value - ) -{ - __cpuid ((int *)Value, CpuidFcnAddress); -} - -AMDLIB_OPTIMIZE -UINT8 -ReadNumberOfCpuCores( - void - ) -{ - CPUID_DATA Value; - CpuidRead (0x80000008, &Value); - return Value.ECX_Reg & 0xff; -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - BOOLEAN IdsErrorStop ( IN UINT32 FileCode -- To view, visit https://review.coreboot.org/28091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c Gerrit-Change-Number: 28091 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670F00/binaryPI/AGESA.c: Remove VENDORCODE_FULL_S...
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28090 Change subject: vendorcode/amd/pi/00670F00/binaryPI/AGESA.c: Remove VENDORCODE_FULL_SUPPORT ...................................................................... vendorcode/amd/pi/00670F00/binaryPI/AGESA.c: Remove VENDORCODE_FULL_SUPPORT Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Id91e76282509743070e34c02082d3f3f46a14059 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c 1 file changed, 0 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28090/1 diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index ea55343..c42df59 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -157,22 +157,6 @@ return Dispatcher(LateParams); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/********************************************************************** - * Interface call: AmdInitRecovery - **********************************************************************/ -AGESA_STATUS -AmdInitRecovery ( - IN OUT AMD_RECOVERY_PARAMS *RecoveryParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(RecoveryParams); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /********************************************************************** * Interface call: AmdInitResume **********************************************************************/ @@ -243,50 +227,6 @@ return Dispatcher(AmdApExeParams); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/********************************************************************** - * Interface service call: AmdGetApicId - **********************************************************************/ -AGESA_STATUS -AmdGetApicId ( - IN OUT AMD_APIC_PARAMS *AmdParamApic -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdParamApic); -} - -/********************************************************************** - * Interface service call: AmdGetPciAddress - **********************************************************************/ -AGESA_STATUS -AmdGetPciAddress ( - IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdParamGetPci); -} - -/********************************************************************** - * Interface service call: AmdIdentifyCore - **********************************************************************/ -AGESA_STATUS -AmdIdentifyCore ( - IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdParamIdentify); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /********************************************************************** * Interface service call: AmdReadEventLog **********************************************************************/ @@ -300,42 +240,3 @@ if (!Dispatcher) return AGESA_UNSUPPORTED; return Dispatcher(Event); } - -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/********************************************************************** - * Interface service call: AmdIdentifyDimm - **********************************************************************/ -AGESA_STATUS -AmdIdentifyDimm ( - IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdDimmIdentify); -} - -AGESA_STATUS -AmdIdsRunApTaskLate ( - IN AP_EXE_PARAMS *AmdApExeParams - ) -{ - AmdApExeParams->StdHeader.Func = -1; - return AGESA_UNSUPPORTED; -} - -/********************************************************************** - * Interface service call: AmdGet2DDataEye - **********************************************************************/ -AGESA_STATUS -AmdGet2DDataEye ( - IN OUT AMD_GET_DATAEYE *AmdGetDataEye - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdGetDataEye); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ -- To view, visit https://review.coreboot.org/28090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id91e76282509743070e34c02082d3f3f46a14059 Gerrit-Change-Number: 28090 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORT
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28089 Change subject: vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORT ...................................................................... vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORT Remove VENDORCODE_FULL_SUPPORT from file: vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c 1 file changed, 0 insertions(+), 375 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28089/1 diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c index 2989265..392dda6 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c @@ -223,115 +223,6 @@ return (FALSE); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/** - * Get specific PSP Entry information, this routine will auto detect the processor for loading - * correct PSP Directory - * - * - * - * @param[in] EntryType PSP DIR Entry Type - * @param[in,out] EntryAddress Address of the specific PSP Entry - * @param[in,out] EntrySize Size of the specific PSP Entry - */ - -BOOLEAN -PSPEntryInfo ( - IN PSP_DIRECTORY_ENTRY_TYPE EntryType, - IN OUT UINT64 *EntryAddress, - IN OUT UINT32 *EntrySize - ) -{ - PSP_DIRECTORY *PspDir; - UINTN i; - PROGRAM_ID ProgramId; - - PspDir = NULL; - if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) { - return FALSE; - } - - ProgramId = PspGetProgarmId (); - //Append BR Program ID - if ((ProgramId == BR_PROGRAM) && - ((EntryType == SMU_OFFCHIP_FW) || - (EntryType == SMU_OFF_CHIP_FW_2) || - (EntryType == AMD_SCS_BINARY))) { - EntryType |= (PSP_ENTRY_BR_PROGRAM_ID << 8); - } - - for (i = 0; i < PspDir->Header.TotalEntries; i++) { - if (PspDir->PspEntry[i].Type == EntryType) { - *EntryAddress = PspDir->PspEntry[i].Location; - *EntrySize = PspDir->PspEntry[i].Size; - return (TRUE); - } - } - - return (FALSE); -} - -BOOLEAN -PspSoftWareFuseInfo ( - IN OUT UINTN *FuseSpiAddress, - IN OUT UINT64 *FuseValue - ) -{ - PSP_DIRECTORY *PspDir; - UINTN i; - - PspDir = NULL; - if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) { - return FALSE; - } - - for (i = 0; i < PspDir->Header.TotalEntries; i++) { - if (PspDir->PspEntry[i].Type == AMD_SOFT_FUSE_CHAIN_01) { - *FuseSpiAddress = (UINT32) (UINTN) &PspDir->PspEntry[i].Location; - *FuseValue = PspDir->PspEntry[i].Location; - return (TRUE); - } - } - return (FALSE); -} - -static UINT32 Fletcher32 ( - IN OUT UINT16 *data, - IN UINTN words - ) -{ - UINT32 sum1; - UINT32 sum2; - UINTN tlen; - - sum1 = 0xffff; - sum2 = 0xffff; - - while (words) { - tlen = words >= 359 ? 359 : words; - words -= tlen; - do { - sum2 += sum1 += *data++; - } while (--tlen); - sum1 = (sum1 & 0xffff) + (sum1 >> 16); - sum2 = (sum2 & 0xffff) + (sum2 >> 16); - } - // Second reduction step to reduce sums to 16 bits - sum1 = (sum1 & 0xffff) + (sum1 >> 16); - sum2 = (sum2 & 0xffff) + (sum2 >> 16); - return sum2 << 16 | sum1; -} - -VOID -UpdataPspDirCheckSum ( - IN OUT PSP_DIRECTORY *PspDir - ) -{ - PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \ - (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /** Check if PSP device is present @@ -353,76 +244,6 @@ return (FALSE); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/** - Check PSP Platform Seucre Enable State - HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode) - will be applied if Psp Plaform Secure is enabled - - @retval BOOLEAN 0: PSP Platform Secure Disabled, 1: PSP Platform Secure Enabled - -**/ -BOOLEAN -CheckPspPlatformSecureEnable ( - VOID - ) -{ - UINT32 SecureFuseReg; - PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS); - SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA); - - if (SecureFuseReg &= PLATFORM_SECURE_BOOT_EN) { - return (TRUE); - } - return (FALSE); -} - -/** - Check PSP Recovery Flag - Target will set Recovery flag if some PSP entry point by PSP directory has been corrupted. - - @retval BOOLEAN 0: Recovery Flag is cleared, 1: Recovery Flag has been set - -**/ -BOOLEAN -CheckPspRecoveryFlag ( - VOID - ) -{ - MBOX_STATUS *MboxStatus; - - //Init PSP MMIO - PspBarInitEarly (); - - GetPspMboxStatus (&MboxStatus); - - return (BOOLEAN) (MboxStatus->Recovery); -} - -/** - Return the PspMbox MMIO location - - - @retval BOOLEAN FALSE: ERROR, TRUE: SUCCEED - -**/ -BOOLEAN -GetPspMboxStatus ( - IN OUT MBOX_STATUS **MboxStatus - ) -{ - UINT32 PspMmio; - - if (GetPspBar3Addr (&PspMmio) == FALSE) { - return (FALSE); - } - - *MboxStatus = (MBOX_STATUS *)( (UINTN)PspMmio + PSP_MAILBOX_BASE + PSP_MAILBOX_STATUS_OFFSET); // PSPMbox base is at offset CP2MSG_28 ie. offset 28*4 = 0x70 - - return (TRUE); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - BOOLEAN PspBarInitEarly () { @@ -458,33 +279,6 @@ return (TRUE); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/** - Return the PspMMIO MMIO location - - @param[in] PspMmio Pointer to Psp MMIO address - - @retval BOOLEAN 0: Error, 1 Success -**/ -BOOLEAN -GetPspBar1Addr ( - IN OUT UINT32 *PspMmio - ) -{ - if (CheckPspDevicePresent () == FALSE) { - return (FALSE); - } - - *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG); - - if ((*PspMmio) == 0xffffffff) { - return (FALSE); - } - - return (TRUE); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /** Return the PspMMIO MMIO location @@ -519,172 +313,3 @@ return (TRUE); } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/** - * Acquire the Mutex for access PSP,X86 co-accessed register - * Call this routine before access SMIx98 & SMIxA8 - * - */ -VOID -AcquirePspSmiRegMutex ( - VOID - ) -{ - UINT32 PspBarAddr; - UINT32 MutexReg0; - UINT32 MutexReg1; - - PspBarAddr = 0; - if (GetPspBar3Addr (&PspBarAddr)) { - MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET; - MutexReg1 = PspBarAddr + PSP_MUTEX_REG1_OFFSET; - *(volatile UINT32*)(UINTN)(MutexReg0) |= BIT0; - *(volatile UINT32*)(UINTN)(MutexReg1) |= BIT0; - //Wait till PSP FW release the mutex - while ((*(volatile UINT32*)(UINTN)(MutexReg0)& BIT1) && (*(volatile UINT32*)(UINTN)(MutexReg1) & BIT0)) { - ; - } - } -} -/** - * Release the Mutex for access PSP,X86 co-accessed register - * Call this routine after access SMIx98 & SMIxA8 - * - */ -VOID -ReleasePspSmiRegMutex ( - VOID - ) -{ - UINT32 PspBarAddr; - UINT32 MutexReg0; - - PspBarAddr = 0; - if (GetPspBar3Addr (&PspBarAddr)) { - MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET; - *(volatile UINT32*)(UINTN)(MutexReg0) &= ~BIT0; - } -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Returns the access width mask for the processor - * - * - * @param[in] AccessWidth Access width - * @retval Width in number of bytes - */ - - -UINT8 -static PspLibAccessWidth ( - IN ACCESS_WIDTH AccessWidth - ) -{ - UINT8 Width; - - switch (AccessWidth) { - case AccessWidth8: - case AccessS3SaveWidth8: - Width = 1; - break; - case AccessWidth16: - case AccessS3SaveWidth16: - Width = 2; - break; - case AccessWidth32: - case AccessS3SaveWidth32: - Width = 4; - break; - case AccessWidth64: - case AccessS3SaveWidth64: - Width = 8; - break; - default: - Width = 0; - } - return Width; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read GNB indirect registers - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[out] Value Pointer to value - */ -VOID -PspLibPciIndirectRead ( - IN PCI_ADDR Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - OUT VOID *Value - ) -{ - UINT32 IndexOffset; - - IndexOffset = PspLibAccessWidth (Width); - LibAmdPciWrite (Width, Address, &IndirectAddress, NULL); - Address.AddressValue += IndexOffset; - LibAmdPciRead (Width, Address, Value, NULL); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write GNB indirect registers - * - * - * - * @param[in] Address PCI address of indirect register - * @param[in] IndirectAddress Offset of indirect register - * @param[in] Width Width - * @param[in] Value Pointer to value - */ -VOID -PspLibPciIndirectWrite ( - IN PCI_ADDR Address, - IN UINT32 IndirectAddress, - IN ACCESS_WIDTH Width, - IN VOID *Value - ) -{ - UINT32 IndexOffset; - - IndexOffset = PspLibAccessWidth (Width); - LibAmdPciWrite (Width, Address, &IndirectAddress, NULL); - Address.AddressValue += IndexOffset; - LibAmdPciWrite (Width, Address, Value, NULL); -} - -BOOLEAN -IsS3Resume ( - ) -{ - UINT16 AcpiPm1CntBlk; - UINT16 SleepType; - UINT8 PmioAddr; - - AcpiPm1CntBlk = 0; - //Get AcpiPm1CntBlk address - //PMIO register can only allow 8bits access - PmioAddr = PMIO_REG62; - LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL); - LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, &AcpiPm1CntBlk, NULL); - - PmioAddr++; - LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL); - LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, ((UINT8 *) &AcpiPm1CntBlk) + 1, NULL); - - //Get Sleep type - LibAmdIoRead (AccessWidth16, AcpiPm1CntBlk, &SleepType, NULL); - SleepType = SleepType & 0x1C00; - SleepType = ((SleepType >> 10) & 7); - - return ((SleepType == 3) ? TRUE : FALSE); -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - -- To view, visit https://review.coreboot.org/28089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2 Gerrit-Change-Number: 28089 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SU...
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28088 Change subject: vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SUPPORT ...................................................................... vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SUPPORT Remove VENDORCODE_FULL_SUPPORT from files FchLib.c and FchPeLib.c. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c 2 files changed, 0 insertions(+), 915 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/28088/1 diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c index 2c2b688..01ae71e 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c @@ -77,535 +77,3 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/**< cimFchStall - Reserved */ -VOID -CimFchStall ( - IN UINT32 uSec, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 timerAddr; - UINT32 startTime; - UINT32 elapsedTime; - - LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); - if ( timerAddr == 0 ) { - uSec = uSec / 2; - while ( uSec != 0 ) { - LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader); - uSec--; - } - } else { - LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); - for ( ;; ) { - LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); - if ( elapsedTime < startTime ) { - elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; - } else { - elapsedTime = elapsedTime - startTime; - } - if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { - break; - } - } - } -} - -/**< FchReset - Reserved */ -VOID -FchPciReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 PciRstValue; - - PciRstValue = 0x06; - LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader); -} - -/**< outPort80 - Reserved */ -VOID -OutPort80 ( - IN UINT32 pcode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader); - return; -} - -/**< outPort1080 - Reserved */ -VOID -OutPort1080 ( - IN UINT32 pcode, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader); - return; -} - -/**< FchCopyMem - Reserved */ -VOID -FchCopyMem ( - IN VOID* pDest, - IN VOID* pSource, - IN UINTN Length - ) -{ - UINTN i; - UINT8 *Ptr; - UINT8 *Source; - Ptr = (UINT8*)pDest; - Source = (UINT8*)pSource; - for (i = 0; i < Length; i++) { - *Ptr = *Source; - Source++; - Ptr++; - } -} - -/** GetRomSigPtr - Reserved **/ -VOID* -GetRomSigPtr ( - IN UINTN *RomSigPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RomPtr; - UINT32 RomSig; - UINT16 MswAddr; - - *RomSigPtr = 0; - MswAddr = 0xFF00; - do { - RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO; - LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader); - if (RomSig == FCH_ROMSIG_SIGNATURE) { - *RomSigPtr = RomPtr; - break; - } - MswAddr >>= 1; - MswAddr |= BIT15; - } while (MswAddr != 0xFFF8); - return RomSigPtr; -} - -/** ReadXhci0Phy - Reserved **/ -VOID -ReadXhci0Phy ( - IN UINT32 Port, - IN UINT32 Address, - IN UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RegIndex; - UINT32 RegValue; - PCI_ADDR PciAddress; - - RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader); - - RegIndex = FCH_XHCI_IND60_REG04; - PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; - LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader); - PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - - (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF; -} - -/** ReadXhci1Phy - Reserved **/ -VOID -ReadXhci1Phy ( - IN UINT32 Port, - IN UINT32 Address, - IN UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RegIndex; - UINT32 RegValue; - PCI_ADDR PciAddress; - - RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader); - - RegIndex = FCH_XHCI_IND60_REG04; - PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; - LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader); - PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; - LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); - - (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF; -} - -/** AcLossControl - Reserved **/ -VOID -AcLossControl ( - IN UINT8 AcLossControlValue - ) -{ - AcLossControlValue &= 0x03; - AcLossControlValue |= BIT2; - RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue); -} - -/** RecordFchConfigPtr - Reserved **/ -VOID -RecordFchConfigPtr ( - IN UINT32 FchConfigPtr - ) -{ - RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) ); - RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) ); - RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) ); - RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) ); -} - -/** ReadAlink - Reserved **/ -UINT32 -ReadAlink ( - IN UINT32 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Data; - LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); - LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); - //Clear Index - Index = 0; - LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); - return Data; -} - -/** WriteAlink - Reserved **/ -VOID -WriteAlink ( - IN UINT32 Index, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); - LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); - //Clear Index - Index = 0; - LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); -} - -/** RwAlink - Reserved **/ -VOID -RwAlink ( - IN UINT32 Index, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 AccessType; - - AccessType = Index & 0xE0000000; - if (AccessType == (AXINDC << 29)) { - WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader); - Index = FCH_AX_DATAC_REG34 | AccessType; - } else if (AccessType == (AXINDP << 29)) { - WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader); - Index = FCH_AX_DATAP_REG3C | AccessType; - } - WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * @param[in] StdHeader - * - */ -VOID -ReadPmio ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - OpFlag = 1 << (OpFlag - 1); - for (i = 0; i < OpFlag; i++) { - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); - Address++; - LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * @param[in] StdHeader - * - */ -VOID -WritePmio ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - OpFlag = 1 << (OpFlag - 1); - for (i = 0; i < OpFlag; i++) { - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); - Address++; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * RwPmio - Read/Write PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] AndMask - Data And Mask 32 bits - * @param[in] OrMask - Data OR Mask 32 bits - * @param[in] StdHeader - * - */ -VOID -RwPmio ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Result; - - ReadPmio (Address, OpFlag, &Result, StdHeader); - Result = (Result & AndMask) | OrMask; - WritePmio (Address, OpFlag, &Result, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PMIO2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * @param[in] StdHeader - * - */ -VOID -ReadPmio2 ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - OpFlag = 1 << (OpFlag - 1); - for ( i = 0; i < OpFlag; i++ ) { - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); - Address++; - LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); - } -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PMIO 2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * @param[in] StdHeader - * - */ -VOID -WritePmio2 ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - OpFlag = 1 << (OpFlag - 1); - - for ( i = 0; i < OpFlag; i++ ) { - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); - Address++; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * RwPmio2 - Read/Write PMIO2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] AndMask - Data And Mask 32 bits - * @param[in] OrMask - Data OR Mask 32 bits - * @param[in] StdHeader - * - */ -VOID -RwPmio2 ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 Result; - - ReadPmio2 (Address, OpFlag, &Result, StdHeader); - Result = (Result & AndMask) | OrMask; - WritePmio2 (Address, OpFlag, &Result, StdHeader); -} - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read BIOSRAM - * - * - * - * @param[in] Address - BIOSRAM Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * @param[in] StdHeader - * - */ -VOID -ReadBiosram ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - OpFlag = 1 << (OpFlag - 1); - for (i = 0; i < OpFlag; i++) { - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); - Address++; - LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write BIOSRAM - * - * - * - * @param[in] Address - BIOSRAM Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * @param[in] StdHeader - * - */ -VOID -WriteBiosram ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - OpFlag = 1 << (OpFlag - 1); - for (i = 0; i < OpFlag; i++) { - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); - Address++; - LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Record SMI Status - * - * - * @param[in] StdHeader - * - */ -VOID -RecordSmiStatus ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Index; - UINT8 SwSmiValue; - - ACPIMMIO8 (0xfed80320) |= 0x01; - for ( Index = 0; Index < 20; Index++ ) { - ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index); - } - LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader); - ACPIMMIO8 (0xfed10040) = SwSmiValue; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Clear All SMI Status - * - * - * @param[in] StdHeader - * - */ -VOID -ClearAllSmiStatus ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINTN Index; - - for ( Index = 0; Index < 20; Index++ ) { - ACPIMMIO8 (0xfed80280 + Index) |= 0; - } -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c index 1df709c..2b70e17 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c @@ -52,93 +52,6 @@ */ #define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*----------------------------------------------------------------------------------------*/ -/** - * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) - * - * - * - * @param[in] pSciMapTbl - Table data pointer - * @param[in] FchResetDataBlock - * - */ -VOID -ProgramFchSciMapTbl ( - IN SCI_MAP_CONTROL *pSciMapTbl, - IN FCH_RESET_DATA_BLOCK *FchResetDataBlock - ) -{ - AMD_CONFIG_PARAMS *StdHeader; - - UINT32 ddtempVar; - StdHeader = FchResetDataBlock->StdHeader; - - if (pSciMapTbl != NULL) { - while (pSciMapTbl->InputPin != 0xFF) { - if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) { - ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin; - if (((pSciMapTbl->InputPin == FCH_SMI_xHC0Pme) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \ - ((pSciMapTbl->InputPin == FCH_SMI_xHC1Pme) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) { - } else { - LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader); - } - } else { - //Assert Warning "SCI map is invalid" - } - pSciMapTbl++; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data) - * - * - * - * @param[in] pGpioTbl - Table data pointer - * - */ -VOID -ProgramFchGpioTbl ( - IN GPIO_CONTROL *pGpioTbl - ) -{ - if (pGpioTbl != NULL) { - while (pGpioTbl->GpioPin != 0xFF) { - ACPIMMIO8 (ACPI_MMIO_BASE + IOMUX_BASE + pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction); - ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte); - pGpioTbl++; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data) - * - * - * - * @param[in] pSataPhyTbl - Table data pointer - * @param[in] FchResetDataBlock - * - */ -VOID -ProgramFchSataPhyTbl ( - IN SATA_PHY_CONTROL *pSataPhyTbl, - IN FCH_RESET_DATA_BLOCK *FchResetDataBlock - ) -{ - if (pSataPhyTbl != NULL) { - while (pSataPhyTbl->PhyData != 0xFFFFFFFF) { - //to be implemented - pSataPhyTbl++; - } - } -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ - /** * GetChipSysMode - Get Chip status * @@ -180,299 +93,3 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/*----------------------------------------------------------------------------------------*/ -/** - * SbSleepTrapControl - SB Sleep Trap Control - * - * - * - * @param[in] SleepTrap - Whether sleep trap is enabled - * - */ -VOID -SbSleepTrapControl ( - IN BOOLEAN SleepTrap - ) -{ - if (SleepTrap) { - ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); - ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2; - - ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) &= ~ (BIT5); - ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); - ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1; - } else { - ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) |= BIT5; - ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); - ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0; - - ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); - } -} - -/** - * FchUsb3D3ColdCallback - Fch Usb3 D3Cold Callback - * - * - * @param[in] FchDataPtr - * - */ -VOID -FchUsb3D3ColdCallback ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - UINT8 Value8; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - //FCH_DEADLOOP (); - ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) |= FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown; - do { - } while ((ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) & FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown) == 0); - - ACPIMMIO32 (FCH_XHC_PMx00_Configure0) |= FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN; - - ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= ~ (AOAC_PWR_ON_DEV); - do { - } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 0); - - ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= 3; - - ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn; - - if ((ACPIMMIO8 (FCH_AOACx64_EHCI_D3_CONTROL) & 0x03) == 3) { - ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); - ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn; - } - - ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_XhcPwrGood + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); - Value8 = ACPIMMIO8 (0xFED803EE); - Value8 &= 0xFC; - Value8 |= 0x01; - ACPIMMIO8 (0xFED803EE) = Value8; -} - -/** - * FchUsb3D0Callback - Fch Usb3 D0 Callback - * - * - * @param[in] FchDataPtr - * - */ -VOID -FchUsb3D0Callback ( - IN VOID *FchDataPtr - ) -{ - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - UINT32 Dword32; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - ACPIMMIO8 (0xFED803EE) &= 0xFC; - - ACPIMMIO8 (FCH_AOACxA0_PwrGood_Control) |= (FCH_AOACxA0_PwrGood_Control_XhcPwrGood); - ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn); - ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn); - Dword32 = ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control); - Dword32 &= ~(FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); - ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) = ((FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB | Dword32) & (~ BIT29)); - - ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= 0xFC; - ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= (AOAC_PWR_ON_DEV); - do { - } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 7); - - do { - } while ((ACPIMMIO32 (FCH_XHC_PMx00_Configure0) & BIT7) != BIT7); - - ACPIMMIO32 (FCH_XHC_PMx00_Configure0) &= ~ (BIT16); - -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Checks Bristol or Stoney - * - * NOTE: - * - * @param[in] StdHeader - * - */ -BOOLEAN -FchCheckBR_ST ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - // Only initialize on CZ processors, otherwise exit. - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) { - return TRUE; - } - if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) { - return TRUE; - } - - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Checks Bristol - * - * NOTE: - * - * @param[in] StdHeader - * - */ -BOOLEAN -FchCheckBR ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - // Only initialize on CZ processors, otherwise exit. - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) { - return TRUE; - } - - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Checks Stoney - * - * NOTE: - * - * @param[in] StdHeader - * - */ -BOOLEAN -FchCheckST ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - // Only initialize on CZ processors, otherwise exit. - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) { - return TRUE; - } - - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Checks Carrizo - * - * NOTE: - * - * @param[in] StdHeader - * - */ -BOOLEAN -FchCheckCZ ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPU_LOGICAL_ID LogicalId; - - // Only initialize on CZ processors, otherwise exit. - GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - if ((LogicalId.Revision & AMD_F15_CZ_ALL) != 0) { - return TRUE; - } - - return FALSE; -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Checks Package AM4 - * - * NOTE: - * - * @param[in] StdHeader - * - */ -BOOLEAN -FchCheckPackageAM4 ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - CPUID_DATA CpuId; - UINT8 RegValue; - - LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); - RegValue = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 - ///@todo - update the PkgType once it is reflected in BKDG - if (RegValue == 2) { - return TRUE; - } else { - return FALSE; - } -} - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function Get Scratch Fuse - * - * NOTE: - * - * @param[in] StdHeader - * - */ -UINT64 -FchGetScratchFuse ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR D0F0xB8_SMU_Index_Address; - PCI_ADDR D0F0xBC_SMU_Index_Data; - UINT64 TempData64; - UINT32 TempData32; - - D0F0xB8_SMU_Index_Address.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xB8)); - D0F0xBC_SMU_Index_Data.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xBC)); - TempData64 = 0; - TempData32 = 0xC0016028; - LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); - LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); - TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) >> 9; - TempData32 = 0xC001602C; - LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); - LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); - TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (32 - 9); - TempData32 = 0xC0016030; - LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); - LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); - TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (64 - 9); - - return TempData64; -} -#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ -- To view, visit https://review.coreboot.org/28088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150 Gerrit-Change-Number: 28088 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Matt Delco has posted comments on this change. ( https://review.coreboot.org/28073 ) Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... Patch Set 1: > Again I don't think that statement is true, a value in _PR3 does not mean to > keep device power in D3Hot. For your reference, the following code > https://chromium.googlesource.com/chromiumos/third_party/kernel/+/stabilize… did explain that. Is there a particular place that is supposed to illustrate this? It looks to me like acpi_power_transition() calls acpi_power_on_list() on items in the list for the new power state and calls acpi_power_off_list() on items in old list. So, having a _PR3 keeps the power on in D3Hot. > May I know what kind of problem you are facing now? > The steps in _OFF had not been executed? The device (or at least the privacy light) never turns off in Windows. If no driver is installed for the camera then the light stays on. If I install a driver for the device then the light stays on. If I install a driver and modify ACPI then the light does turn off. I might be able to convince the light to go off by having the driver try harder to claim support for D3cold but this is going beyond the Intel reference examples and again I don't see any other MIPI camera outside of coreboot that uses _PR3. -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 20:43:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Lijian Zhao (Code Review) 14 Aug '18

14 Aug '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28073 ) Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > In this case, that means the _OFF in power resource will be called > > when transit into to D3hot state. > > That'd be true with this change, but prior to this change having a value in _PR3 means to keep the device on in D3hot. Is there any reason to provide power to the devices outside of D0? > > > the corresponding object to set the device into a deeper Dx must also be declared, and vice versa. > > That just says it needs to be declared, so I could stick in an empty _PS3 but nobody bothers to do that even if it's a stronger fit to the spec requirements. Again I don't think that statement is true, a value in _PR3 does not mean to keep device power in D3Hot. For your reference, the following code https://chromium.googlesource.com/chromiumos/third_party/kernel/+/stabilize… did explain that. May I know what kind of problem you are facing now? The steps in _OFF had not been executed? -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 20:27:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by Hannah Williams (Code Review) 14 Aug '18

14 Aug '18

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/28060/2/src/soc/intel/common/block/cpu/mp_i… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/#/c/28060/2/src/soc/intel/common/block/cpu/mp_i… PS2, Line 138: soc_init_cpus(dev->link_list); wrap it with if (dev && dev->link_list) With the entries we have in devicetree.cb it will not be NULL though https://review.coreboot.org/#/c/28060/2/src/soc/intel/common/block/graphics… File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/#/c/28060/2/src/soc/intel/common/block/graphics… PS2, Line 43: if (!dev->enabled) if (!dev || !dev->enabled) -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 19:47:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Matt Delco has posted comments on this change. ( https://review.coreboot.org/28076 ) Change subject: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28076/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28076/1//COMMIT_MSG@9 PS1, Line 9: change > please correct this typo. Done -- To view, visit https://review.coreboot.org/28076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Gerrit-Change-Number: 28076 Gerrit-PatchSet: 2 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 19:17:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28076 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable ...................................................................... mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable This file contains two instances of "dptf_enable" = "1". This change removes the 2nd instance (it doesn't have an explicit comment like the 1st instance). The dptf devices still seem to be present even with this change, as expected. Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28076/2 -- To view, visit https://review.coreboot.org/28076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Gerrit-Change-Number: 28076 Gerrit-PatchSet: 2 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable
by Sumeet R Pawnikar (Code Review) 14 Aug '18

14 Aug '18

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/28076 ) Change subject: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28076/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28076/1//COMMIT_MSG@9 PS1, Line 9: chanes please correct this typo. -- To view, visit https://review.coreboot.org/28076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Gerrit-Change-Number: 28076 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 18:59:38 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit August 2018