coreboot-gerrit August 2018

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Change in coreboot[master]: Snappy:TESTONLY Test setting is correct
by TungYang Huang (Code Review) 15 Aug '18

15 Aug '18

Hello Tony Huang, I'd like you to do a code review. Please visit https://review.coreboot.org/28098 to review the following change. Change subject: Snappy:TESTONLY Test setting is correct ...................................................................... Snappy:TESTONLY Test setting is correct BUG=None TEST=None Change-Id: Ieb6c859bba3aa2e53dfc491465188dccdfce3f40 Signed-off-by: TungYang Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/reef/variants/snappy/mainboard.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28098/1 diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index a625c60..665444c 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -1,3 +1,4 @@ +TEST ONLY /* * This file is part of the coreboot project. * -- To view, visit https://review.coreboot.org/28098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieb6c859bba3aa2e53dfc491465188dccdfce3f40 Gerrit-Change-Number: 28098 Gerrit-PatchSet: 1 Gerrit-Owner: TungYang Huang <Tony-Huang(a)quantatw.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable
by Patrick Georgi (Code Review) 15 Aug '18

15 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28076 ) Change subject: mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable ...................................................................... mb/google/poppy/variants/nocturne: remove dup'ed dptf_enable This file contains two instances of "dptf_enable" = "1". This change removes the 2nd instance (it doesn't have an explicit comment like the 1st instance). The dptf devices still seem to be present even with this change, as expected. Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Signed-off-by: Matt Delco <delco(a)chromium.org> Reviewed-on: https://review.coreboot.org/28076 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4fbd0ff..88af929 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -61,7 +61,6 @@ # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" - register "dptf_enable" = "1" register "tdp_pl2_override" = "18" register "psys_pmax" = "45" register "tcc_offset" = "10" -- To view, visit https://review.coreboot.org/28076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Gerrit-Change-Number: 28076 Gerrit-PatchSet: 3 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: sx9310 to 400kb
by Patrick Georgi (Code Review) 15 Aug '18

15 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28075 ) Change subject: mb/google/poppy/variants/nocturne: sx9310 to 400kb ...................................................................... mb/google/poppy/variants/nocturne: sx9310 to 400kb The spec of the sx9310 says the I2C interface can handle standard (100kb/s) and fast mode (400kb/s). The current setting is using fast plus (1000kb/s) so this change is reducing the speed to fast mode. I've been using the sensors with this change for a few weeks now, though I also don't recall seeing an issue prior to this change. Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Signed-off-by: Matt Delco <delco(a)chromium.org> Reviewed-on: https://review.coreboot.org/28075 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2c074e9..4fbd0ff 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -298,7 +298,7 @@ chip drivers/i2c/sx9310 register "desc" = ""Right SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" - register "speed" = "I2C_SPEED_FAST_PLUS" + register "speed" = "I2C_SPEED_FAST" register "uid" = "0" register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" @@ -339,7 +339,7 @@ chip drivers/i2c/sx9310 register "desc" = ""Left SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" - register "speed" = "I2C_SPEED_FAST_PLUS" + register "speed" = "I2C_SPEED_FAST" register "uid" = "1" register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" -- To view, visit https://review.coreboot.org/28075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Gerrit-Change-Number: 28075 Gerrit-PatchSet: 2 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Revert "mb/google/poppy/variants/atlas: enable camera power and relea...
by Patrick Georgi (Code Review) 15 Aug '18

15 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28072 ) Change subject: Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" ...................................................................... Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4. Camera power is now handled by ACPI rules - no need to force the GPIOs on by default. BUG=b:80106316,b:111141128 Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/28072 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Ping-chung Chen <ping-chung.chen(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Ping-chung Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index c0ef9ef..5f1a1f5 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -175,7 +175,7 @@ /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ - PAD_CFG_GPO(GPP_D8, 1, DEEP), + PAD_CFG_GPO(GPP_D8, 0, DEEP), /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ PAD_CFG_NF_1V8(GPP_D9, NONE, DEEP, NF1), /* D10 : ISH_SPI_CLK ==> ISH_SPI_CLK */ @@ -189,9 +189,9 @@ /* D16 : ISH_UART0_CTS# ==> NC */ PAD_CFG_NC(GPP_D16), /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ -- To view, visit https://review.coreboot.org/28072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Gerrit-Change-Number: 28072 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Tomasz Figa <tfiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin
by Patrick Georgi (Code Review) 15 Aug '18

15 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28070 ) Change subject: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin ...................................................................... mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin This defines new GPIO pin for controlling the display panel CABC function. The default value is high (enabled). BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/28070 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved caveh jalali: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 51dbf69..c0ef9ef 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -215,8 +215,8 @@ PAD_CFG_NC(GPP_E4), /* E5 : SATA_DEVSLP1 ==> NC */ PAD_CFG_NC(GPP_E5), - /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + /* E6 : SATA_DEVSLP2 ==> DISPLAY_DCR_EN */ + PAD_CFG_GPO(GPP_E6, 1, DEEP), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ -- To view, visit https://review.coreboot.org/28070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Gerrit-Change-Number: 28070 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/atlas: Update DPTF sensor names
by Patrick Georgi (Code Review) 15 Aug '18

15 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28069 ) Change subject: mb/google/atlas: Update DPTF sensor names ...................................................................... mb/google/atlas: Update DPTF sensor names This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 TEST=verified new strings show up in /sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/28069 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved caveh jalali: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index bb42351..685f4dd 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -18,22 +18,22 @@ #define DPTF_CPU_CRITICAL 105 #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "systherm0" +#define DPTF_TSR0_SENSOR_NAME "Ambient" #define DPTF_TSR0_PASSIVE 48 #define DPTF_TSR0_CRITICAL 90 #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "systherm1" +#define DPTF_TSR1_SENSOR_NAME "Charger" #define DPTF_TSR1_PASSIVE 48 #define DPTF_TSR1_CRITICAL 90 #define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "systherm2" +#define DPTF_TSR2_SENSOR_NAME "DRAM" #define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 -#define DPTF_TSR3_SENSOR_NAME "systherm3" +#define DPTF_TSR3_SENSOR_NAME "eMMC" #define DPTF_TSR3_PASSIVE 65 #define DPTF_TSR3_CRITICAL 75 -- To view, visit https://review.coreboot.org/28069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Gerrit-Change-Number: 28069 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: src/{commonlib, lib}: Fix typo
by Elyes HAOUAS (Code Review) 15 Aug '18

15 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28097 Change subject: src/{commonlib,lib}: Fix typo ...................................................................... src/{commonlib,lib}: Fix typo Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/mmc.c M src/lib/selfboot.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/28097/1 diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index e09d826..b62c8be 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -197,7 +197,7 @@ return ret; } -static int mmc_send_tunning_seq(struct sd_mmc_ctrlr *ctrlr, char *buffer) +static int mmc_send_tuning_seq(struct sd_mmc_ctrlr *ctrlr, char *buffer) { struct mmc_command cmd; struct mmc_data data; @@ -225,7 +225,7 @@ /* Request the device send the tuning sequence up to 40 times */ ctrlr->tuning_start(ctrlr, 0); for (index = 0; index < 40; index++) { - mmc_send_tunning_seq(ctrlr, buffer); + mmc_send_tuning_seq(ctrlr, buffer); if (ctrlr->is_tuning_complete(ctrlr, &successful)) { if (successful) return 0; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index a79f61d..fbd1cc4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -511,7 +511,7 @@ } /* - * Each architecture can perform additonal operations + * Each architecture can perform additional operations * on the loaded segment */ prog_segment_loaded((uintptr_t)dest, ptr->s_memsz, -- To view, visit https://review.coreboot.org/28097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Gerrit-Change-Number: 28097 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 15 Aug '18

15 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep/acpi.c: Add Netburst CPUs ...................................................................... Patch Set 20: (6 comments) https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/acpi.c@92 PS20, Line 92: else else is not generally useful after a break or return https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/speedstep.… PS20, Line 45: if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and line over 80 characters https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/speedstep.… PS20, Line 46: enabled bits */ line over 80 characters https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/speedstep.… PS20, Line 48: params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); line over 80 characters https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/speedstep.… PS20, Line 77: !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { line over 80 characters https://review.coreboot.org/#/c/22604/20/src/cpu/intel/speedstep/speedstep.… PS20, Line 79: params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); line over 80 characters -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 20 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Aug 2018 08:34:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add support for supervisor binary interface (SBI)
by Xiang Wang (Code Review) 15 Aug '18

15 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28096 to look at the new patch set (#3). Change subject: riscv: add support for supervisor binary interface (SBI) ...................................................................... riscv: add support for supervisor binary interface (SBI) SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/include/sbi.h A src/arch/riscv/sbi.c M src/arch/riscv/trap_handler.c 4 files changed, 167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28096/3 -- To view, visit https://review.coreboot.org/28096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Gerrit-Change-Number: 28096 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support for supervisor binary interface (SBI)
by Xiang Wang (Code Review) 15 Aug '18

15 Aug '18

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/28096 ) Change subject: riscv: add support for supervisor binary interface (SBI) ...................................................................... riscv: add support for supervisor binary interface (SBI) SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/include/sbi.h A src/arch/riscv/sbi.c M src/arch/riscv/trap_handler.c 4 files changed, 175 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28096/2 -- To view, visit https://review.coreboot.org/28096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Gerrit-Change-Number: 28096 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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coreboot-gerrit August 2018