coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/atlas: Update DPTF sensor names
by Sumeet R Pawnikar (Code Review) 14 Aug '18

14 Aug '18

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/28069 ) Change subject: mb/google/atlas: Update DPTF sensor names ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Gerrit-Change-Number: 28069 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 18:56:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Matt Delco (Code Review) 14 Aug '18

14 Aug '18

Matt Delco has posted comments on this change. ( https://review.coreboot.org/28073 ) Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... Patch Set 1: > Patch Set 1: > In this case, that means the _OFF in power resource will be called > when transit into to D3hot state. That'd be true with this change, but prior to this change having a value in _PR3 means to keep the device on in D3hot. Is there any reason to provide power to the devices outside of D0? > the corresponding object to set the device into a deeper Dx must also be declared, and vice versa. That just says it needs to be declared, so I could stick in an empty _PS3 but nobody bothers to do that even if it's a stronger fit to the spec requirements. -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 18:37:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by Hannah Williams (Code Review) 14 Aug '18

14 Aug '18

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 2: > Patch Set 1: > > (1 comment) > > > Martin, What tool are you using for this code scan - we're not > > getting these "soc issues" flagged, using Klocwork Static Code > > Analysis tool? > > We are getting different "warnings" in chip.c and gspi.c files. > > These are generated using clang's scan-build tool: > https://clang-analyzer.llvm.org/scan-build.html > > We also run coverity's stataic analysis on a bi-weekly basis. That output is here: > https://scan.coverity.com/projects/coreboot?tab=overview > That finds still different issues in soc/intel. I have a feeling that since static.c gets deleted from the emerge build, so KW does not see the dev_root structure and hence we have been getting errors reported for possible NULL access for dev = dev_find_path -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 18:23:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/tpm: Fix TPM 1.2 state machine issues
by Philipp Deppenwiese (Code Review) 14 Aug '18

14 Aug '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/28085 Change subject: security/tpm: Fix TPM 1.2 state machine issues ...................................................................... security/tpm: Fix TPM 1.2 state machine issues * Add hard_reset mechanism and result checks for the ramstage TPM driver. * Move enabling TPM before activating otherwise it isn't successful. More information can be found via the TCG specification. Tested=Elgon Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/drivers/tpm/tpm.c M src/security/tpm/tspi/tspi.c 2 files changed, 24 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28085/1 diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index e4a81c3..e7c1165 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -17,6 +17,7 @@ #include <stddef.h> #include <bootstate.h> #include <security/tpm/tspi.h> +#include <reset.h> #if IS_ENABLED(CONFIG_ARCH_X86) #include <arch/acpi.h> @@ -24,12 +25,15 @@ static void init_tpm_dev(void *unused) { + uint32_t result; #if IS_ENABLED(CONFIG_ARCH_X86) int s3resume = acpi_is_wakeup_s3(); - tpm_setup(s3resume); + result = tpm_setup(s3resume); #else - tpm_setup(false); + result = tpm_setup(false); #endif + if (result == TPM_E_MUST_REBOOT) + do_hard_reset(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL); diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 950e930..f3093e7 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -25,17 +25,31 @@ #if IS_ENABLED(CONFIG_TPM1) static uint32_t tpm1_invoke_state_machine(void) { - uint8_t disable; + uint8_t disabled; uint8_t deactivated; uint32_t result = TPM_SUCCESS; /* Check that the TPM is enabled and activated. */ - result = tlcl_get_flags(&disable, &deactivated, NULL); + result = tlcl_get_flags(&disabled, &deactivated, NULL); if (result != TPM_SUCCESS) { printk(BIOS_ERR, "TPM: Can't read capabilities.\n"); return result; } + if (disabled) { + printk(BIOS_INFO, "TPM: disabled (%d)." + "Enabling...\n", disabled); + + result = tlcl_set_enable(); + if (result != TPM_SUCCESS) { + printk(BIOS_ERR, "TPM: Can't set enabled state.\n"); + return result; + } + + printk(BIOS_INFO, "TPM: Must reboot to re-enable\n"); + result = TPM_E_MUST_REBOOT; + } + if (!!deactivated != IS_ENABLED(CONFIG_TPM_DEACTIVATE)) { printk(BIOS_INFO, "TPM: Unexpected TPM deactivated state. Toggling...\n"); @@ -50,19 +64,6 @@ result = TPM_E_MUST_REBOOT; } - if (disable && !deactivated) { - printk(BIOS_INFO, "TPM: disabled (%d). Enabling...\n", disable); - - result = tlcl_set_enable(); - if (result != TPM_SUCCESS) { - printk(BIOS_ERR, "TPM: Can't set enabled state.\n"); - return result; - } - - printk(BIOS_INFO, "TPM: Must reboot to re-enable\n"); - result = TPM_E_MUST_REBOOT; - } - return result; } #endif @@ -122,8 +123,8 @@ result = tlcl_physical_presence_cmd_enable(); if (result != TPM_SUCCESS) { printk( - BIOS_ERR, - "TPM: Can't enable physical presence command.\n"); + BIOS_ERR, + "TPM: Can't enable physical presence command.\n"); goto out; } -- To view, visit https://review.coreboot.org/28085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b Gerrit-Change-Number: 28085 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: google/grunt: Remove BayHub EMMC driving strength override
by Kevin Chiu (Code Review) 14 Aug '18

14 Aug '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/28084 Change subject: google/grunt: Remove BayHub EMMC driving strength override ...................................................................... google/grunt: Remove BayHub EMMC driving strength override Side effect was observed that after override BayHub EMMC driving strength to the max, EMMC CLK will be reduced to 51.x Mhz from 200 Mhz. This will cause OS installation fail on Samsung EMMC sku. BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28084/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index b1bd492..cf38b99 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -17,8 +17,6 @@ #include <baseboard/variants.h> #include <gpio.h> #include <variant/gpio.h> -#include <device/pci.h> -#include <drivers/generic/bayhub/bh720.h> uint8_t variant_board_sku(void) { @@ -37,26 +35,3 @@ gpio_set(GPIO_133, 0); } #endif - -void bh720_driving_strength(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Read current EMMC 1.8V CLK/DATA,CMD driving strength */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x40000304); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - - /* set EMMC 1.8V CLK/DATA,CMD the max level */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | (BH720_PCR_CLK_DRV_MAX << 4) | - (BH720_PCR_DATA_CMD_DRV_MAX << 1)); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x80000304); -} -- To view, visit https://review.coreboot.org/28084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Gerrit-Change-Number: 28084 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: vendorcode/amd/pi/00670F00/Lib: Remove read modify write functions
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28083 Change subject: vendorcode/amd/pi/00670F00/Lib: Remove read modify write functions ...................................................................... vendorcode/amd/pi/00670F00/Lib: Remove read modify write functions Now that the functions that used them were safely removed, remove LibAmdIoRMW(), LibAmdMemRMW() and LibAmdPciRMW(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Lib/amdlib.c M src/vendorcode/amd/pi/00670F00/Lib/amdlib.h 2 files changed, 4 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28083/1 diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c index b400bca..784ba46 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c @@ -61,6 +61,7 @@ IN AMD_CONFIG_PARAMS *StdHeader ); +#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) VOID STATIC LibAmdGetDataFromPtr ( @@ -70,6 +71,8 @@ OUT UINT32 *TemData, OUT UINT32 *TempDataMask ); +#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ + VOID IdsOutPort ( IN UINT32 Addr, @@ -579,36 +582,6 @@ } } -/*---------------------------------------------------------------------------------------*/ -/** - * IO read modify write - * - * - * @param[in] AccessWidth Access width - * @param[in] IoAddress IO address - * @param[in] Data OR data - * @param[in] DataMask Mask to be used before data write back to register. - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdIoRMW ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempData; - UINT32 TempMask; - UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL); - Value = (Value & (~TempMask)) | TempData; - LibAmdIoWrite (AccessWidth, IoAddress, &Value, NULL); -} - #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /*---------------------------------------------------------------------------------------*/ /** @@ -720,35 +693,6 @@ break; } } -/*---------------------------------------------------------------------------------------*/ -/** - * Memory/MMIO read modify write - * - * - * @param[in] AccessWidth Access width - * @param[in] MemAddress Memory address - * @param[in] Data OR data - * @param[in] DataMask Mask to be used before data write back to register. - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdMemRMW ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempData; - UINT32 TempMask; - UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL); - Value = (Value & (~TempMask)) | TempData; - LibAmdMemWrite (AccessWidth, MemAddress, &Value, NULL); -} #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /*---------------------------------------------------------------------------------------*/ @@ -891,36 +835,6 @@ } } -/*---------------------------------------------------------------------------------------*/ -/** - * PCI read modify write - * - * - * @param[in] AccessWidth Access width - * @param[in] PciAddress Pci address - * @param[in] Data OR Data - * @param[in] DataMask Mask to be used before data write back to register. - * @param[in] StdHeader Standard configuration header - * - */ -VOID -LibAmdPciRMW ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 TempData = 0; - UINT32 TempMask = 0; - UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL); - Value = (Value & (~TempMask)) | TempData; - LibAmdPciWrite (AccessWidth, PciAddress, &Value, NULL); -} - #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /*---------------------------------------------------------------------------------------*/ /** @@ -1297,6 +1211,7 @@ } #endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ +#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /*---------------------------------------------------------------------------------------*/ /** * Returns the package type mask for the processor @@ -1341,7 +1256,6 @@ } } -#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /*---------------------------------------------------------------------------------------*/ /** * Returns the package type mask for the processor diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h index 3f7fbbd..f41e0c4 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h @@ -164,15 +164,6 @@ ); VOID -LibAmdIoRMW ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID LibAmdIoPoll ( IN ACCESS_WIDTH AccessWidth, IN UINT16 IoAddress, @@ -200,15 +191,6 @@ ); VOID -LibAmdMemRMW ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID LibAmdMemPoll ( IN ACCESS_WIDTH AccessWidth, IN UINT64 MemAddress, @@ -236,15 +218,6 @@ ); VOID -LibAmdPciRMW ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID LibAmdPciPoll ( IN ACCESS_WIDTH AccessWidth, IN PCI_ADDR PciAddress, -- To view, visit https://review.coreboot.org/28083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be Gerrit-Change-Number: 28083 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW()
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28082 Change subject: vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW() ...................................................................... vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW() The functions that use LibAmdPciRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdPciRMW() itself. The functions to be removed are: >From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c: ProgramPciByteTable(). >From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(), RwXhci0IndReg() and RwXhci1IndReg(). >From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c 4 files changed, 0 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28082/1 diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h index 3f4bccf..aa11396 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h @@ -55,8 +55,6 @@ VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl); VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); @@ -346,9 +344,6 @@ VOID BackUpCG2 (OUT VOID); VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID AcLossControl (IN UINT8 AcLossControlValue); diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c index 37880b4..2c2b688 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c @@ -192,69 +192,6 @@ return RomSigPtr; } -/** RwXhciIndReg - Reserved **/ -VOID -RwXhciIndReg ( - IN UINT32 Index, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RevReg; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; - LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); - PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; - RevReg = ~AndMask; - LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); - - PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; - LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); - PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; - RevReg = ~AndMask; - LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); -} - -/** RwXhci0IndReg - Reserved **/ -VOID -RwXhci0IndReg ( - IN UINT32 Index, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RevReg; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; - LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); - PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; - RevReg = ~AndMask; - LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); -} - -/** RwXhci1IndReg - Reserved **/ -VOID -RwXhci1IndReg ( - IN UINT32 Index, - IN UINT32 AndMask, - IN UINT32 OrMask, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT32 RevReg; - PCI_ADDR PciAddress; - - PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; - LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); - PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; - RevReg = ~AndMask; - LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); -} - /** ReadXhci0Phy - Reserved **/ VOID ReadXhci0Phy ( diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c index ae02aec..1df709c 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c @@ -55,52 +55,6 @@ #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /*----------------------------------------------------------------------------------------*/ /** - * ProgramPciByteTable - Program PCI register by table (8 bits data) - * - * - * - * @param[in] pPciByteTable - Table data pointer - * @param[in] dwTableSize - Table length - * @param[in] StdHeader - * - */ -VOID -ProgramPciByteTable ( - IN REG8_MASK *pPciByteTable, - IN UINT16 dwTableSize, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 dbBusNo; - UINT8 dbDevFnNo; - UINT8 Or8; - UINT8 Mask8; - PCI_ADDR PciAddress; - - dbBusNo = pPciByteTable->RegIndex; - dbDevFnNo = pPciByteTable->AndMask; - pPciByteTable++; - - for ( i = 1; i < dwTableSize; i++ ) { - if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) { - pPciByteTable++; - dbBusNo = pPciByteTable->RegIndex; - dbDevFnNo = pPciByteTable->AndMask; - pPciByteTable++; - i++; - } else { - PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex; - Or8 = pPciByteTable->OrMask; - Mask8 = ~pPciByteTable->AndMask; - LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader); - pPciByteTable++; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) * * diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c index 7c55c4e..136353e 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c @@ -72,22 +72,3 @@ LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); } - -VOID -RwPci ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - UINT32 rMask; - - PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); - rMask = ~Mask; - LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader); -} - - -- To view, visit https://review.coreboot.org/28082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb Gerrit-Change-Number: 28082 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: vendorcode/amd/pi/00670F00: Remove functions that use LibAmdMemRMW()
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28081 Change subject: vendorcode/amd/pi/00670F00: Remove functions that use LibAmdMemRMW() ...................................................................... vendorcode/amd/pi/00670F00: Remove functions that use LibAmdMemRMW() The functions that use LibAmdMemRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdMemRMW() itself. The functions to be removed are: ProgramFchAcpiMmioTbl() and GetEfuseStatus(), both from vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c. BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c 2 files changed, 0 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28081/1 diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h index 00247f4..3f4bccf 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h @@ -57,7 +57,6 @@ VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl); VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); @@ -343,7 +342,6 @@ VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader); VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); -VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID TurnOffCG2 (OUT VOID); VOID BackUpCG2 (OUT VOID); VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c index c1b14f5..ae02aec 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c @@ -101,42 +101,6 @@ /*----------------------------------------------------------------------------------------*/ /** - * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data) - * - * - * - * @param[in] pAcpiTbl - Table data pointer - * @param[in] StdHeader - * - */ -VOID -ProgramFchAcpiMmioTbl ( - IN ACPI_REG_WRITE *pAcpiTbl, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 i; - UINT8 Or8; - UINT8 Mask8; - UINT32 ddtempVar; - - if (pAcpiTbl != NULL) { - if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) { - // Signature Checking - pAcpiTbl++; - for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) { - ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; - Or8 = pAcpiTbl->DataOrMask; - Mask8 = ~pAcpiTbl->DataAndMask; - LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader); - pAcpiTbl++; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) * * @@ -263,33 +227,6 @@ } #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) -/** - * GetEfuseStatue - Get Efuse status - * - * - * @param[in] Value - Return Chip strap status - * @param[in] StdHeader - * - */ -VOID -GetEfuseStatus ( - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Or8; - UINT8 Mask8; - - Or8 = BIT5; - Mask8 = BIT5; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); - LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader); - LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader); - Or8 = 0; - Mask8 = BIT5; - LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); -} - /*----------------------------------------------------------------------------------------*/ /** * SbSleepTrapControl - SB Sleep Trap Control -- To view, visit https://review.coreboot.org/28081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1 Gerrit-Change-Number: 28081 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: util/autoport: Adapt logmaker for newer ACPI versions
by Patrick Georgi (Code Review) 14 Aug '18

14 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28054 ) Change subject: util/autoport: Adapt logmaker for newer ACPI versions ...................................................................... util/autoport: Adapt logmaker for newer ACPI versions acpidump now creates dumps with 4 spaces instead of 2 in front of the hex dump, so be a bit smarter about the input with regexp. Tested with X220 autoport logs: Still creates the same coreboot code. Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/28054 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M util/autoport/log_reader.go 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go index c94d182..d9a687a 100644 --- a/util/autoport/log_reader.go +++ b/util/autoport/log_reader.go @@ -6,6 +6,7 @@ "fmt" "log" "os" + "regexp" "strconv" "strings" ) @@ -106,11 +107,13 @@ curTable := "" for scanner.Scan() { line := scanner.Text() + /* Only supports ACPI tables up to 0x10000 in size, FIXME if needed */ + is_hexline, _ := regexp.MatchString(" *[0-9A-Fa-f]{4}: ", line) switch { case len(line) >= 6 && line[5] == '@': curTable = line[0:4] Tables[curTable] = make([]byte, 0, 100000) - case len(line) > 7 && line[0:2] == " " && isXDigit(line[2]) && isXDigit(line[3]) && isXDigit(line[4]) && isXDigit(line[5]) && line[6] == ':': + case is_hexline: Tables[curTable] = l.AssignHexLine(line, Tables[curTable]) } } -- To view, visit https://review.coreboot.org/28054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Gerrit-Change-Number: 28054 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: eve: Support PL1 override option
by Lucas Chen (Code Review) 14 Aug '18

14 Aug '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/28079 Change subject: eve: Support PL1 override option ...................................................................... eve: Support PL1 override option AltOS DPTF prefers MMIO to control the PL1 setting. However, MSR PL1 also contributes to the decision of the max PL1 power. In the current design, the lower value takes effect. In order to align MMIO and MSR settings, a tdp_pl1_override option is added to override the MSR PL1 limitation. BRANCH=eve BUG=b:73133864 TEST=1. Write PL1 override setting in devicetree.cb 2. Verify the MSR PL1 limitation is set from TAT. Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28079/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a147d92..8cef686 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -99,6 +99,8 @@ /* PL2 Override value in Watts */ u32 tdp_pl2_override; + /* PL1 Override value in Watts */ + u32 tdp_pl1_override; /* SysPL2 Value in Watts */ u32 tdp_psyspl2; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5535ec6..417c4bc 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -117,7 +117,7 @@ msr_t msr = rdmsr(MSR_PLATFORM_INFO); msr_t limit; unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time, tdp_pl2; + unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; @@ -154,7 +154,9 @@ /* Set long term power limit to TDP */ limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? + tdp : (conf->tdp_pl1_override * power_unit)); + limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); /* Set PL1 Pkg Power clamp bit */ limit.lo |= PKG_POWER_LIMIT_CLAMP; -- To view, visit https://review.coreboot.org/28079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b Gerrit-Change-Number: 28079 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Wei Shun Chang <wei.shun.chang(a)intel.com>

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coreboot-gerrit August 2018