coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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1120 discussions

Change in coreboot[master]: Revert "mb/google/poppy/variants/atlas: enable camera power and relea...
by Caveh Jalali (Code Review) 14 Aug '18

14 Aug '18

Hello caveh jalali, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28072 to look at the new patch set (#2). Change subject: Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" ...................................................................... Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4. Camera power is now handled by ACPI rules - no need to force the GPIOs on by default. BUG=b:80106316 Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28072/2 -- To view, visit https://review.coreboot.org/28072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Gerrit-Change-Number: 28072 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin
by Caveh Jalali (Code Review) 14 Aug '18

14 Aug '18

Hello caveh jalali, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28070 to look at the new patch set (#3). Change subject: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin ...................................................................... mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin This defines new GPIO pin for controlling the display panel CABC function. The default value is high (enabled). BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28070/3 -- To view, visit https://review.coreboot.org/28070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Gerrit-Change-Number: 28070 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Lance Zhao (Code Review) 13 Aug '18

13 Aug '18

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/28073 ) Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28073/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28073/1//COMMIT_MSG@9 PS1, Line 9: This means that we're : telling the OS that the cams need power in both D0 and D3 (and not the : intermediate states) I don't think that's how OSPM to determine the power needed or not in D3 state. The power resource list in _PR3 will be turned off if OSPM decided to enter D3hot state(Or D3 cold depends on how OS decided in _OSC). My understanding is delete _PR3 will make power resources in FRPR kept in On state but not turned off. -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Aug 2018 23:40:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by John Zhao (Code Review) 13 Aug '18

13 Aug '18

John Zhao has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… PS1, Line 137: assert > It will only avoid the null pointer being dereferenced *IF* fatal asserts are turned on. […] Looks like CONFIG_FATAL_ASSERTS is on. If asserts fails, FILE/LINE are printed and code execution is halt. -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 13 Aug 2018 23:33:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/nocturne: turn off cams in D3
by Matt Delco (Code Review) 13 Aug '18

13 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28073 Change subject: mainboard/google/nocturne: turn off cams in D3 ...................................................................... mainboard/google/nocturne: turn off cams in D3 Power resources are cited for _PR0 and _PR3. This means that we're telling the OS that the cams need power in both D0 and D3 (and not the intermediate states). This change deletes _PR3 so that power isn't supplied during D3 and the camera light doesn't stay on continuously. Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28073/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl index ec4430d..1688356 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl @@ -71,7 +71,6 @@ }) Name (_PR0, Package () { FCPR }) - Name (_PR3, Package () { FCPR }) /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { @@ -134,7 +133,6 @@ Name (_DEP, Package () { CAM0 }) Name (_PR0, Package () { FCPR }) - Name (_PR3, Package () { FCPR }) Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl index 19146dc..3f6fe8d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl @@ -70,7 +70,6 @@ }) Name (_PR0, Package () { RCPR }) - Name (_PR3, Package () { RCPR }) /* Port0 of CAM1 is connected to port1 of CIO2 device */ Name (_DSD, Package () { @@ -138,7 +137,6 @@ Name (_DEP, Package() { CAM1 }) Name (_PR0, Package () { RCPR }) - Name (_PR3, Package () { RCPR }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), @@ -168,7 +166,6 @@ Name (_DEP, Package () { CAM1 }) Name (_PR0, Package () { RCPR }) - Name (_PR3, Package () { RCPR }) Name (_DSD, Package () { -- To view, visit https://review.coreboot.org/28073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id52c2499c3b7577f03395cc9ca2460f25b80e13f Gerrit-Change-Number: 28073 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: Revert "mb/google/poppy/variants/atlas: enable camera power and relea...
by Caveh Jalali (Code Review) 13 Aug '18

13 Aug '18

Hello caveh jalali, I'd like you to do a code review. Please visit https://review.coreboot.org/28072 to review the following change. Change subject: Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" ...................................................................... Revert "mb/google/poppy/variants/atlas: enable camera power and release reset" This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4. Camera power is now handled by ACPI rules - no need to force the GPIOs on by default. BUG=b:80106316 Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28072/1 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index c0ef9ef..5f1a1f5 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -175,7 +175,7 @@ /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ - PAD_CFG_GPO(GPP_D8, 1, DEEP), + PAD_CFG_GPO(GPP_D8, 0, DEEP), /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ PAD_CFG_NF_1V8(GPP_D9, NONE, DEEP, NF1), /* D10 : ISH_SPI_CLK ==> ISH_SPI_CLK */ @@ -189,9 +189,9 @@ /* D16 : ISH_UART0_CTS# ==> NC */ PAD_CFG_NC(GPP_D16), /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ - PAD_CFG_GPO(GPP_D17, 1, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ -- To view, visit https://review.coreboot.org/28072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Gerrit-Change-Number: 28072 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/atlas: Update DPTF sensor names
by Caveh Jalali (Code Review) 13 Aug '18

13 Aug '18

Hello caveh jalali, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28069 to look at the new patch set (#2). Change subject: mb/google/atlas: Update DPTF sensor names ...................................................................... mb/google/atlas: Update DPTF sensor names This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 TEST=verified new strings show up in /sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28069/2 -- To view, visit https://review.coreboot.org/28069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Gerrit-Change-Number: 28069 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin
by Caveh Jalali (Code Review) 13 Aug '18

13 Aug '18

Hello caveh jalali, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28070 to look at the new patch set (#2). Change subject: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin ...................................................................... mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin This defines new GPIO pin for controlling the display panel CABC function. BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28070/2 -- To view, visit https://review.coreboot.org/28070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Gerrit-Change-Number: 28070 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by Martin Roth (Code Review) 13 Aug '18

13 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 1: (1 comment) > Martin, What tool are you using for this code scan - we're not > getting these "soc issues" flagged, using Klocwork Static Code > Analysis tool? > We are getting different "warnings" in chip.c and gspi.c files. These are generated using clang's scan-build tool: https://clang-analyzer.llvm.org/scan-build.html We also run coverity's stataic analysis on a bi-weekly basis. That output is here: https://scan.coverity.com/projects/coreboot?tab=overview That finds still different issues in soc/intel. https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… PS1, Line 137: assert > Links are downstream buses attached to the device as: […] It will only avoid the null pointer being dereferenced *IF* fatal asserts are turned on. Typically, as I said, asserts in coreboot are non-fatal, so the NULL pointer *WILL* still be dereferenced. Think of assert in the coreboot codebase as a printk that gets output if the assert fails. Since they are non-fatal, the code still runs beyond this. https://review.coreboot.org/cgit/coreboot.git/tree/src/Kconfig#n691 https://review.coreboot.org/cgit/coreboot.git/tree/src/include/assert.h#n34 -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 13 Aug 2018 22:21:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus/var/bobba: Update GPIO config for bobba bid >= 1
by Justin TerAvest (Code Review) 13 Aug '18

13 Aug '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/28071 Change subject: mb/google/octopus/var/bobba: Update GPIO config for bobba bid >= 1 ...................................................................... mb/google/octopus/var/bobba: Update GPIO config for bobba bid >= 1 This change updates GPIO configuration for bobba boards with id >= 1 This follows the same model as fleex: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. BUG=b:112354568 TEST=Built firmware for bobba Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- A src/mainboard/google/octopus/variants/bobba/Makefile.inc A src/mainboard/google/octopus/variants/bobba/gpio.c A src/mainboard/google/octopus/variants/bobba/variant.c 3 files changed, 172 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28071/1 diff --git a/src/mainboard/google/octopus/variants/bobba/Makefile.inc b/src/mainboard/google/octopus/variants/bobba/Makefile.inc new file mode 100644 index 0000000..d54ed40 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bobba/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c new file mode 100644 index 0000000..4b9b7b2 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* CAM_SOC_EC_SYNC */ + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + DISPUPD), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + /* EN_PP3300_WLAN_L */ + PAD_CFG_GPO(GPIO_178, 0, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + switch (board_id()) { + case 0: + case UNDEFINED_STRAPPING_ID: + *num = 0; + break; + default: + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + return c; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + /* PCH_WP_OD */ + PAD_CFG_GPI(GPIO_190, NONE, DEEP), + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + DISPUPD), + /* H1_SLAVE_SPI_CLK_R */ + PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_CS_L_R */ + PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MISO */ + PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), + /* H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), + + /* WLAN_PE_RST */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), + + /* + * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * pull-up for proper operation. Since there is no external pull present + * on this platform, configure an internal weak pull-up. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, + ENPU), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + /* + * This is a hack to configure EN_PP3300_WLAN based on board id. Once + * board id 0 is deprecated, we can get rid of this. + */ + uint32_t bid = board_id(); + + if (bid == UNDEFINED_STRAPPING_ID || bid < 1) + gpio_output(GPIO_178, 1); + else + gpio_output(GPIO_178, 0); + + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c new file mode 100644 index 0000000..1ead5e2 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <device/device.h> +#include <drivers/i2c/generic/chip.h> +#include <drivers/i2c/hid/chip.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <string.h> + +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_hid_ops; + +void variant_update_devtree(struct device *dev) +{ + uint32_t bid; + struct device *touchscreen_i2c_host; + struct device *child; + const struct bus *children_bus; + static const struct acpi_gpio new_enable_gpio = + ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146); + + bid = board_id(); + + /* Nothing to update. */ + if (bid == UNDEFINED_STRAPPING_ID || bid < 1) + return; + + touchscreen_i2c_host = dev_find_slot(0, PCH_DEVFN_I2C7); + + if (touchscreen_i2c_host == NULL) + return; + + children_bus = touchscreen_i2c_host->link_list; + child = NULL; + + /* Find all children on bus to update touchscreen enable gpio. */ + while ((child = dev_bus_each_child(children_bus, child)) != NULL) { + struct drivers_i2c_generic_config *cfg; + + /* No configration to change. */ + if (child->chip_info == NULL) + continue; + + if (child->chip_ops == &drivers_i2c_generic_ops) + cfg = child->chip_info; + else if (child->chip_ops == &drivers_i2c_hid_ops) { + struct drivers_i2c_hid_config *hid_cfg; + hid_cfg = child->chip_info; + cfg = &hid_cfg->generic; + } else + continue; + + /* Update the enable gpio. */ + memcpy(&cfg->enable_gpio, &new_enable_gpio, + sizeof(new_enable_gpio)); + } +} -- To view, visit https://review.coreboot.org/28071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579 Gerrit-Change-Number: 28071 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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coreboot-gerrit August 2018