coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ifdtool: port the feature to set AltMeDisable/HAP bit here
by build bot (Jenkins) (Code Review) 13 Aug '18

13 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21437 ) Change subject: ifdtool: port the feature to set AltMeDisable/HAP bit here ...................................................................... Patch Set 65: (2 comments) https://review.coreboot.org/#/c/21437/65/util/ifdtool/ifdtool.c File util/ifdtool/ifdtool.c: https://review.coreboot.org/#/c/21437/65/util/ifdtool/ifdtool.c@188 PS65, Line 188: printf("Peculiar firmware descriptor, assuming Ibex Peak compatibility.\n"); line over 80 characters https://review.coreboot.org/#/c/21437/65/util/ifdtool/ifdtool.c@197 PS65, Line 197: printf("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); line over 80 characters -- To view, visit https://review.coreboot.org/21437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a Gerrit-Change-Number: 21437 Gerrit-PatchSet: 65 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Comment-Date: Mon, 13 Aug 2018 09:24:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common: Add function to set BILD bit in RTC
by Rizwan Qureshi (Code Review) 13 Aug '18

13 Aug '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28057 Change subject: soc/intel/common: Add function to set BILD bit in RTC ...................................................................... soc/intel/common: Add function to set BILD bit in RTC Add a function to set the Bios Interface Lock Down bit (bit 31) in RTC Configuration register (0x3400). This bit when set prevents the top swap enable bit (bit 0) in the RTC BUC register (0x3414) from being changed. Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/rtc.h M src/soc/intel/common/block/rtc/rtc.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28057/1 diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h index 56cfb2e..0faf0b0 100644 --- a/src/soc/intel/common/block/include/intelblocks/rtc.h +++ b/src/soc/intel/common/block/include/intelblocks/rtc.h @@ -45,4 +45,6 @@ */ enum ts_config get_rtc_buc_top_swap_status(void); +/* Set RTC Configuration BILD bit. */ +void rtc_conf_set_bios_interface_lockdown(void); #endif /* SOC_INTEL_COMMON_BLOCK_RTC_H */ diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index b8c8849..2fe4bd9 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -27,7 +27,10 @@ #define PCR_RTC_CONF_RESERVED (1 << 31) /* RTC backed up control register */ #define PCR_RTC_BUC 0x3414 -#define PCR_RTC_BUC_TOP_SWAP (1 << 0) +#define PCR_RTC_BUC_TOP_SWAP (1 << 0) + +#define PCR_RTC_CONF 0x3400 +#define PCR_RTC_CONF_BILD (1 << 31) void enable_rtc_upper_bank(void) { @@ -48,6 +51,12 @@ cmos_init(soc_get_rtc_failed()); } +void rtc_conf_set_bios_interface_lockdown(void) +{ + pcr_rmw32(PID_RTC, PCR_RTC_CONF, ~PCR_RTC_CONF_BILD, + PCR_RTC_CONF_BILD); +} + #if IS_ENABLED(CONFIG_INTEL_HAS_TOP_SWAP) void configure_rtc_buc_top_swap(enum ts_config ts_state) { -- To view, visit https://review.coreboot.org/28057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476 Gerrit-Change-Number: 28057 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mainboard/asrock/e350m1: Fix coding style
by Elyes HAOUAS (Code Review) 13 Aug '18

13 Aug '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/26470 ) Change subject: mainboard/asrock/e350m1: Fix coding style ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/26470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I9a6d5635dc10e486fa137cfec08842f634f34e66 Gerrit-Change-Number: 26470 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ifdtool: port the feature to set AltMeDisable/HAP bit here
by build bot (Jenkins) (Code Review) 13 Aug '18

13 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21437 ) Change subject: ifdtool: port the feature to set AltMeDisable/HAP bit here ...................................................................... Patch Set 63: (4 comments) https://review.coreboot.org/#/c/21437/63/util/ifdtool/ifdtool.c File util/ifdtool/ifdtool.c: https://review.coreboot.org/#/c/21437/63/util/ifdtool/ifdtool.c@188 PS63, Line 188: printf("Peculiar firmware descriptor, assuming Ibex Peak compatibility.\n"); line over 80 characters https://review.coreboot.org/#/c/21437/63/util/ifdtool/ifdtool.c@197 PS63, Line 197: printf("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); line over 80 characters https://review.coreboot.org/#/c/21437/63/util/ifdtool/ifdtool.c@1650 PS63, Line 1650: fpsba_t* fpsba = find_fpsba(image, size); "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/21437/63/util/ifdtool/ifdtool.c@1651 PS63, Line 1651: fmsba_t* fmsba = find_fmsba(image, size); "foo* bar" should be "foo *bar" -- To view, visit https://review.coreboot.org/21437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a Gerrit-Change-Number: 21437 Gerrit-PatchSet: 63 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Comment-Date: Mon, 13 Aug 2018 06:54:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/autoport: Adapt logmaker for newer ACPI versions
by Nico Huber (Code Review) 12 Aug '18

12 Aug '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28054 ) Change subject: util/autoport: Adapt logmaker for newer ACPI versions ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/28054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Gerrit-Change-Number: 28054 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 12 Aug 2018 20:46:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asus/maximus_iv_gene-z: Add VBT
by Arthur Heymans (Code Review) 12 Aug '18

12 Aug '18

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/28050 ) Change subject: mb/asus/maximus_iv_gene-z: Add VBT ...................................................................... mb/asus/maximus_iv_gene-z: Add VBT The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 3603). Tested with Linux 4.9 and everything works as expected. Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> Reviewed-on: https://review.coreboot.org/28050 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/maximus_iv_gene-z/Kconfig A src/mainboard/asus/maximus_iv_gene-z/data.vbt 2 files changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig index 13fad2d..4106c64 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/Kconfig +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -24,6 +24,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/mainboard/asus/maximus_iv_gene-z/data.vbt b/src/mainboard/asus/maximus_iv_gene-z/data.vbt new file mode 100644 index 0000000..e48d8f2 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/28050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1 Gerrit-Change-Number: 28050 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/autoport: Adapt logmaker for newer ACPI versions
by Arthur Heymans (Code Review) 12 Aug '18

12 Aug '18

Hello Angel Pons, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28054 to look at the new patch set (#4). Change subject: util/autoport: Adapt logmaker for newer ACPI versions ...................................................................... util/autoport: Adapt logmaker for newer ACPI versions acpidump now creates dumps with 4 spaces instead of 2 in front of the hex dump, so be a bit smarter about the input with regexp. Tested with X220 autoport logs: Still creates the same coreboot code. Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/autoport/log_reader.go 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28054/4 -- To view, visit https://review.coreboot.org/28054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Gerrit-Change-Number: 28054 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/hp/630: Add new mainboard (NOT WORKING)
by Angel Pons (Code Review) 12 Aug '18

12 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28056 Change subject: mb/hp/630: Add new mainboard (NOT WORKING) ...................................................................... mb/hp/630: Add new mainboard (NOT WORKING) This is a Nehalem laptop with an ITE IT8518E EC. I have managed to reach the payload stage, but SeaBIOS hangs. EC support is completely missing. Working: Reaching the payload, internal display. Not working: Everything else after what works. Change-Id: Ic9bf4bedb0724110965f2e22b2515cbbc5ed47c7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/hp/630/Kconfig A src/mainboard/hp/630/Kconfig.name A src/mainboard/hp/630/Makefile.inc A src/mainboard/hp/630/acpi/ec.asl A src/mainboard/hp/630/acpi/platform.asl A src/mainboard/hp/630/acpi/superio.asl A src/mainboard/hp/630/acpi_tables.c A src/mainboard/hp/630/board_info.txt A src/mainboard/hp/630/cmos.default A src/mainboard/hp/630/cmos.layout A src/mainboard/hp/630/devicetree.cb A src/mainboard/hp/630/dsdt.asl A src/mainboard/hp/630/gma-mainboard.ads A src/mainboard/hp/630/gpio.c A src/mainboard/hp/630/hda_verb.c A src/mainboard/hp/630/mainboard.c A src/mainboard/hp/630/romstage.c 17 files changed, 1,184 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28056/1 diff --git a/src/mainboard/hp/630/Kconfig b/src/mainboard/hp/630/Kconfig new file mode 100644 index 0000000..163aeff --- /dev/null +++ b/src/mainboard/hp/630/Kconfig @@ -0,0 +1,37 @@ +if BOARD_HP_630 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select NO_UART_ON_SUPERIO + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select INTEL_INT15 + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_LIBGFXINIT + #select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default hp/630 + +config MAINBOARD_PART_NUMBER + string + default "630" + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAX_CPUS + int + default 4 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 +endif diff --git a/src/mainboard/hp/630/Kconfig.name b/src/mainboard/hp/630/Kconfig.name new file mode 100644 index 0000000..bb7e097 --- /dev/null +++ b/src/mainboard/hp/630/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_630 + bool "630 Notebook PC" diff --git a/src/mainboard/hp/630/Makefile.inc b/src/mainboard/hp/630/Makefile.inc new file mode 100644 index 0000000..7088731 --- /dev/null +++ b/src/mainboard/hp/630/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/630/acpi/ec.asl b/src/mainboard/hp/630/acpi/ec.asl new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/mainboard/hp/630/acpi/ec.asl @@ -0,0 +1 @@ + diff --git a/src/mainboard/hp/630/acpi/platform.asl b/src/mainboard/hp/630/acpi/platform.asl new file mode 100644 index 0000000..893d224 --- /dev/null +++ b/src/mainboard/hp/630/acpi/platform.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, /* APM command */ + APMS, 8 /* APM status */ +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(UCMS, 1, Serialized) +{ +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + /* TRAP(71) */ /* TODO */ + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI)) { + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } + } + } +} diff --git a/src/mainboard/hp/630/acpi/superio.asl b/src/mainboard/hp/630/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/hp/630/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/630/acpi_tables.c b/src/mainboard/hp/630/acpi_tables.c new file mode 100644 index 0000000..0914299 --- /dev/null +++ b/src/mainboard/hp/630/acpi_tables.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <southbridge/intel/ibexpeak/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Set thermal levels */ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/630/board_info.txt b/src/mainboard/hp/630/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/hp/630/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/hp/630/cmos.default b/src/mainboard/hp/630/cmos.default new file mode 100644 index 0000000..38f2bd3 --- /dev/null +++ b/src/mainboard/hp/630/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI diff --git a/src/mainboard/hp/630/cmos.layout b/src/mainboard/hp/630/cmos.layout new file mode 100644 index 0000000..fad1868 --- /dev/null +++ b/src/mainboard/hp/630/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2013 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 1 e 1 power_management_beeps +#420 1 e 1 low_battery_beep +#421 1 e 9 sata_mode +#422 1 e 11 usb_always_on +#423 1 r 1 unused + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size +#427 5 r 0 unused +432 8 h 0 volume + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/hp/630/devicetree.cb b/src/mainboard/hp/630/devicetree.cb new file mode 100644 index 0000000..f782f6c --- /dev/null +++ b/src/mainboard/hp/630/devicetree.cb @@ -0,0 +1,90 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/nehalem + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + + + # Enable DisplayPort Hotplug with 6ms pulse + #register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "3" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2500" + register "gpu_panel_power_backlight_off_delay" = "2500" + register "gpu_cpu_backlight" = "0x58d" + register "gpu_pch_backlight" = "0x061a061a" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 02.0 on end # VGA controller + + chip southbridge/intel/ibexpeak + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + #register "gpi1_routing" = "2" + #register "gpi13_routing" = "2" + + register "sata_port_map" = "0x03" + + #register "gpe0_en" = "0x20022046" + #register "alt_gp_smi_en" = "0x0000" + #register "gen1_dec" = "0x7c1601" + #register "gen2_dec" = "0x0c15e1" + #register "gen3_dec" = "0x1c1681" + #register "gen4_dec" = "0x040069" + + #register "p_cnt_throttling_supported" = "1" + #register "c2_latency" = "1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 16.0 on end # HECI + device pci 16.2 on end # IDE/SATA + device pci 19.0 off end # Ethernet + device pci 1a.0 on end # USB2 EHCI + device pci 1b.0 on end # Audio Controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1d.0 on end # USB2 EHCI + device pci 1f.0 on end # PCI-LPC bridge + device pci 1f.2 on end # IDE/SATA + device pci 1f.3 on end # SMBUS + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/hp/630/dsdt.asl b/src/mainboard/hp/630/dsdt.asl new file mode 100644 index 0000000..681c655 --- /dev/null +++ b/src/mainboard/hp/630/dsdt.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, /* DSDT revision: ACPI v3.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20130325 /* OEM revision */ +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + + /* global NVS and variables */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + Device (UNCR) + { + Name (_BBN, 0xFF) + Name (_ADR, 0x00) + Name (RID, 0x00) + Name (_HID, EisaId ("PNP0A03")) + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* Granularity */ + 0x00FF, /* Range Minimum */ + 0x00FF, /* Range Maximum */ + 0x0000, /* Translation Offset */ + 0x0001, /* Length */ + ,, ) + }) + Device (SAD) + { + Name (_ADR, 0x01) + Name (RID, 0x00) + OperationRegion (SADC, PCI_Config, 0x00, 0x0100) + Field (SADC, DWordAcc, NoLock, Preserve) + { + Offset (0x40), + PAM0, 8, + PAM1, 8, + PAM2, 8, + PAM3, 8, + PAM4, 8, + PAM5, 8, + PAM6, 8 + } + } + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hp/630/gma-mainboard.ads b/src/mainboard/hp/630/gma-mainboard.ads new file mode 100644 index 0000000..4e9cf2a --- /dev/null +++ b/src/mainboard/hp/630/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/630/gpio.c b/src/mainboard/hp/630/gpio.c new file mode 100644 index 0000000..89ae9c0 --- /dev/null +++ b/src/mainboard/hp/630/gpio.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio51 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/630/hda_verb.c b/src/mainboard/hp/630/hda_verb.c new file mode 100644 index 0000000..4d6497c --- /dev/null +++ b/src/mainboard/hp/630/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0270, /* Codec Vendor / Device ID: Realtek */ + 0x103c3674, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c3674), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x99a30930), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11820), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40179a2d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x21. */ + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), + 0x80862804, /* Codec Vendor / Device ID: Intel */ + 0x103c3674, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x103c3674), + + /* NID 0x04. */ + AZALIA_PIN_CFG(0x3, 0x04, 0x58560010), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560020), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/630/mainboard.c b/src/mainboard/hp/630/mainboard.c new file mode 100644 index 0000000..f6732cf --- /dev/null +++ b/src/mainboard/hp/630/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/630/romstage.c b/src/mainboard/hp/630/romstage.c new file mode 100644 index 0000000..edb7a9c --- /dev/null +++ b/src/mainboard/hp/630/romstage.c @@ -0,0 +1,283 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <romstage_handoff.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <delay.h> +#include <timestamp.h> +#include <arch/acpi.h> +#include <cbmem.h> + +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/nehalem/nehalem.h> + +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> + +static void pch_enable_lpc(void) +{ + /* X201 EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN | GAMEL_LPC_EN); + + /*pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); + pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); + + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + + pci_write_config32(PCH_LPC_DEV, ETR3, + pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);*/ +} + +static void rcba_config(void) +{ + southbridge_configure_default_intmap(); + +#if 0 + static const u32 rcba_dump3[] = { + /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, + /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, + /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, + /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, + /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, + /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, + /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, + /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, + /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, + /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, + /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, + /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, + /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, + /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, + /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, + /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, + /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, + /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, + /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, + /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, + }; + unsigned int i; + for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3310); + } +#endif +} + +static inline void write_acpi32(u32 addr, u32 val) +{ + outl(val, DEFAULT_PMBASE | addr); +} + +static inline void write_acpi16(u32 addr, u16 val) +{ + outw(val, DEFAULT_PMBASE | addr); +} + +static inline u32 read_acpi32(u32 addr) +{ + return inl(DEFAULT_PMBASE | addr); +} + +/* +static void set_fsb_frequency(void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +}*/ + +void mainboard_romstage_entry(unsigned long bist) +{ + u32 reg32; + int s3resume = 0; + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + + timestamp_init(timestamp_get()); + + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + nehalem_early_initialization(NEHALEM_MOBILE); + + pch_enable_lpc(); + + /* Enable USB Power. We need to do it early for usbdebug to work. */ + //ec_set_bit(0x3b, 4); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + u8 reg8; + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + printk(BIOS_DEBUG, "a2: %02x\n", reg8); + if (!(reg8 & 0x20)) { + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); + } else { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + } else { + printk(BIOS_DEBUG, + "Resume from S3 detected, but disabled.\n"); + } + } + } + + /* Enable SMBUS. */ + enable_smbus(); +/* + outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, + DEFAULT_GPIOBASE | 0x3a); + outb(0x50, 0x15ec); + outb(inb(0x15ee) & 0x70, 0x15ee); + + write_acpi16(0x2, 0x0); + write_acpi32(0x28, 0x0); + write_acpi32(0x2c, 0x0); + if (!s3resume) { + read_acpi32(0x4); + read_acpi32(0x20); + read_acpi32(0x34); + write_acpi16(0x0, 0x900); + write_acpi32(0x20, 0xffff7ffe); + write_acpi32(0x34, 0x56974); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); + }*/ + + early_thermal_init(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + chipset_init(s3resume); + + //set_fsb_frequency(); + + raminit(s3resume, spd_addrmap); + + timestamp_add_now(TS_AFTER_INITRAM); + + intel_early_me_status(); + + if (s3resume) { + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } + + romstage_handoff_init(s3resume); + + if (!s3resume) + quick_ram_check(); +} -- To view, visit https://review.coreboot.org/28056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic9bf4bedb0724110965f2e22b2515cbbc5ed47c7 Gerrit-Change-Number: 28056 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: vendorcode/amd/pi/00670F00/Lib: Validate AccessWidth
by Richard Spiegel (Code Review) 12 Aug '18

12 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28055 Change subject: vendorcode/amd/pi/00670F00/Lib: Validate AccessWidth ...................................................................... vendorcode/amd/pi/00670F00/Lib: Validate AccessWidth For most io/mem/pci functions, if a AccessWidth is invalid, a default within a case statement will take care of it with no ill effects. However, for read/modify/write functions, though default will avoid ill effects, it does causes a static analysis error. Validate that the access width is within valid values for the particular interface io/mem/pci. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I962c6002fca2239bf71036a1e231f5f1ecf14c94 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Lib/amdlib.c M src/vendorcode/amd/pi/00670F00/Lib/amdlib.h 2 files changed, 65 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28055/1 diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c index b400bca..289336b 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c @@ -503,6 +503,39 @@ __asm__ volatile ("finit"); } #endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Check if AccessWidth is valid, used for read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in out) Control (in) = IO/MEM/PCI (out) = set INVALID_ACCESS if width invalid + * + */ +static VOID +LibAmdCheckWidth( + IN ACCESS_WIDTH AccessWidth, + IN OUT UINT16 *Control + ) +{ + ACCESS_WIDTH Checking; + ACCESS_WIDTH Limit; + + /* only width related bits */ + Checking = AccessWidth & 7; + if (Checking > 0) { + Checking--; + if (*Control == AccessMem) + Limit = AccessWidth64; + else + Limit = AccessWidth32; + if (Checking >= Limit) + *Control |= INVALID_ACCESS; + } else + *Control |= INVALID_ACCESS; /* AccessWidthNone is invalid */ +} + /*---------------------------------------------------------------------------------------*/ /** * Read IO port @@ -603,10 +636,14 @@ UINT32 TempData; UINT32 TempMask; UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL); - Value = (Value & (~TempMask)) | TempData; - LibAmdIoWrite (AccessWidth, IoAddress, &Value, NULL); + UINT16 Control = AccessIo; + LibAmdCheckWidth(AccessWidth, &Control); + if ((Control & INVALID_ACCESS) == 0) { + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL); + Value = (Value & (~TempMask)) | TempData; + LibAmdIoWrite (AccessWidth, IoAddress, &Value, NULL); + } } #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) @@ -744,10 +781,14 @@ UINT32 TempData; UINT32 TempMask; UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL); - Value = (Value & (~TempMask)) | TempData; - LibAmdMemWrite (AccessWidth, MemAddress, &Value, NULL); + UINT16 Control = AccessMem; + LibAmdCheckWidth(AccessWidth, &Control); + if ((Control & INVALID_ACCESS) == 0) { + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL); + Value = (Value & (~TempMask)) | TempData; + LibAmdMemWrite (AccessWidth, MemAddress, &Value, NULL); + } } #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) @@ -915,10 +956,14 @@ UINT32 TempData = 0; UINT32 TempMask = 0; UINT32 Value; - LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL); - Value = (Value & (~TempMask)) | TempData; - LibAmdPciWrite (AccessWidth, PciAddress, &Value, NULL); + UINT16 Control = AccessPci; + LibAmdCheckWidth(AccessWidth, &Control); + if ((Control & INVALID_ACCESS) == 0) { + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL); + Value = (Value & (~TempMask)) | TempData; + LibAmdPciWrite (AccessWidth, PciAddress, &Value, NULL); + } } #if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h index 3f7fbbd..04a164c 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h @@ -48,6 +48,14 @@ #include <agesa_headers.h> +typedef enum ACCESS_TYPE { + AccessIo = 1, + AccessMem, + AccessPci, +} ACCESS_TYPE; + +#define INVALID_ACCESS 0x0100 + #define IOCF8 0xCF8 #define IOCFC 0xCFC -- To view, visit https://review.coreboot.org/28055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I962c6002fca2239bf71036a1e231f5f1ecf14c94 Gerrit-Change-Number: 28055 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: util/autoport: Adapt logmaker for newer ACPI versions
by Nico Huber (Code Review) 12 Aug '18

12 Aug '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28054 ) Change subject: util/autoport: Adapt logmaker for newer ACPI versions ...................................................................... Patch Set 3: Code-Review+2 (1 comment) thanks https://review.coreboot.org/#/c/28054/3/util/autoport/log_reader.go File util/autoport/log_reader.go: https://review.coreboot.org/#/c/28054/3/util/autoport/log_reader.go@116 PS3, Line 116: len(line) > 7 && not sure if this is still needed -- To view, visit https://review.coreboot.org/28054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781 Gerrit-Change-Number: 28054 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 12 Aug 2018 02:54:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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