coreboot-gerrit August 2018

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Change in coreboot[master]: src/mb: Remove some unneeded includes
by Elyes HAOUAS (Code Review) 11 Aug '18

11 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28049 Change subject: src/mb: Remove some unneeded includes ...................................................................... src/mb: Remove some unneeded includes Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/apple/macbook21/romstage.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/i915.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cougar_canyon2/mainboard.c M src/mainboard/intel/cougar_canyon2/romstage.c M src/mainboard/intel/d510mo/mainboard.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/stargo2/mainboard.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t420s/smihandler.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t530/smihandler.c M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/lenovo/x220/smihandler.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/mainboard.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/ocp/monolake/mainboard.c M src/mainboard/ocp/wedge100s/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c M src/mainboard/roda/rk9/romstage.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/mainboard.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c 60 files changed, 0 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28049/1 diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index c5ed048..eb963ee 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <arch/io.h> #include <delay.h> @@ -25,7 +24,6 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <northbridge/intel/i945/i945.h> -#include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 19e62d3..ee322ae 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index 727dad3..93920f2 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -19,7 +19,6 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/i82801gx/nvs.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <pc80/mc146818rtc.h> #include <delay.h> #define GPE_EC_SCI 12 diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 35f7208..dacc396 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -28,7 +28,6 @@ #include <timestamp.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 9030698..ce12a8b 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -18,7 +18,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 56ef561..49a25af 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -27,7 +27,6 @@ #include <timestamp.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index eb1d31c..ae51d9e 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -26,7 +26,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index e7235ed..993c5e8 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <drivers/intel/gma/int15.h> #include <fmap.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index b6f9263..d68a46c 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -31,7 +30,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 755fecb..da6d698 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -22,7 +22,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <delay.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ce61912..6f529da 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -24,7 +24,6 @@ #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index e095254..495c80e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -32,7 +31,6 @@ #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 9940c14..e245e09 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index b5b084b..163f4c3 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -31,7 +30,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> #include "ec/compal/ene932/ec.h" diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 32ef960..eb2e6ab 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -24,7 +24,6 @@ #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index cfe0917..9443d28 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 399e2b4..d2925a8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 20914ec..d56dfd4 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -31,7 +30,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #include <bootmode.h> #include <cbfs.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index ec80a42..869a6cc 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -20,9 +20,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 996be0f..0330d82 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -17,14 +17,11 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index 395480b..c5db452 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -17,14 +17,11 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c index 829a962..07c39e0 100644 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ b/src/mainboard/intel/cougar_canyon2/mainboard.c @@ -17,12 +17,9 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 54d2c04..9d3b478 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -24,7 +24,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> #include <halt.h> @@ -38,7 +37,6 @@ #include <southbridge/intel/fsp_bd82x6x/gpio.h> #include <southbridge/intel/fsp_bd82x6x/me.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include "gpio.h" #define SIO_PORT 0x164e diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index 26d3dc1..d2751bc 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> #include <device/pci.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 7ea1c51..d5a4356 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -17,12 +17,9 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index fcb2b2c..a672294 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -22,9 +22,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <console/console.h> #include <superio/smsc/sio1007/chip.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> @@ -32,7 +30,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/intel/stargo2/mainboard.c b/src/mainboard/intel/stargo2/mainboard.c index 408e49c..da93acd 100644 --- a/src/mainboard/intel/stargo2/mainboard.c +++ b/src/mainboard/intel/stargo2/mainboard.c @@ -20,8 +20,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <boot/coreboot_tables.h> diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c index b873aca..cdf087a 100644 --- a/src/mainboard/intel/stargo2/romstage.c +++ b/src/mainboard/intel/stargo2/romstage.c @@ -24,9 +24,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/msr.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> #include <halt.h> #include <reset.h> #include <fsp_util.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 177eca0..6ec6dab 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -20,9 +20,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 32575c8..bb3eaa6 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -22,9 +22,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index fd3544e..1974ab6 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -21,12 +21,10 @@ #include <arch/io.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <cpu/intel/romstage.h> #include <cbmem.h> #include <lib.h> -#include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 0b48807..c34cb5b 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 9f0c4d9..328ae37 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -24,15 +24,12 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <cbfs.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <device/device.h> diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 387e305..4e61a98 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 297e1f1..0491392 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 167ffb2..bb52c87 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -21,7 +21,6 @@ #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> -#include <pc80/mc146818rtc.h> #include <drivers/intel/gma/int15.h> #include <arch/acpigen.h> diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index af79980..e4a8efb 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -26,7 +26,6 @@ #include <lib.h> #include <arch/acpi.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 49ed6b2..c12c1fc 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -25,7 +25,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> @@ -33,7 +32,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <cbfs.h> void pch_enable_lpc(void) diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 71de550..8c3e2b2 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -21,12 +21,10 @@ #include <arch/io.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <cpu/intel/romstage.h> #include <cbmem.h> #include <lib.h> -#include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5d0deea..4b01ada 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -23,7 +23,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <pc80/mc146818rtc.h> #include "dock.h" #include <drivers/intel/gma/int15.h> #include <pc80/keyboard.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1b49eb8..8752949 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> -#include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 93cc2b7..fbbec09 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -23,7 +23,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> #include "dock.h" diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 297e1f1..0491392 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> #include <southbridge/intel/bd82x6x/nvs.h> diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index fb0494c..1ddaedf 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -24,15 +24,12 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <cbfs.h> void pch_enable_lpc(void) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 925779e..96d8062 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -22,7 +22,6 @@ #include <arch/io.h> #include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> -#include <pc80/mc146818rtc.h> #include "dock.h" #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1cdce8c..81ee5da 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -26,7 +26,6 @@ #include <lib.h> #include <arch/acpi.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c index be4cf3c..5a565e0 100644 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ b/src/mainboard/lenovo/z61t/mainboard.c @@ -21,7 +21,6 @@ #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> -#include <pc80/mc146818rtc.h> #include <drivers/intel/gma/int15.h> #include <arch/acpigen.h> diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index cd5b25b..94c8a8f 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -26,7 +26,6 @@ #include <lib.h> #include <arch/acpi.h> #include <timestamp.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index 395480b..f1a3a20 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -14,21 +14,10 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> /* * mainboard_enable is executed as first thing after enumerate_buses(). diff --git a/src/mainboard/ocp/wedge100s/mainboard.c b/src/mainboard/ocp/wedge100s/mainboard.c index 395480b..f1a3a20 100644 --- a/src/mainboard/ocp/wedge100s/mainboard.c +++ b/src/mainboard/ocp/wedge100s/mainboard.c @@ -14,21 +14,10 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> /* * mainboard_enable is executed as first thing after enumerate_buses(). diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index b98b166..2691b67 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -27,8 +27,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> - -#include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> #include <drivers/intel/gma/int15.h> #include <arch/interrupt.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 676c051..56f11a1 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> -#include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index e94b61b..926650a 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> @@ -23,7 +22,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> -#include <pc80/mc146818rtc.h> #include <delay.h> static void mainboard_smm_init(void) diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 65ff0f8..4f6c5b7 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -26,7 +26,6 @@ #include <arch/acpi.h> #include <cbmem.h> #include <lib.h> -#include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 0a00612..8664217 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -19,11 +19,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <ec/smsc/mec1308/ec.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index ba25d54..4d5b667 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include <cbfs.h> #include <arch/acpi.h> #include <console/console.h> @@ -33,7 +32,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 7ea1c51..a62ad12 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -14,19 +14,9 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> #include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 5f56a3e..bb11761 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -34,7 +34,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 73290d5..1e6acc7 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -26,7 +26,6 @@ #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 1f67319..bd15af7 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -17,14 +17,12 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> -- To view, visit https://review.coreboot.org/28049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58 Gerrit-Change-Number: 28049 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: mb/intel/gd43gt: Enable the GBE
by Arthur Heymans (Code Review) 11 Aug '18

11 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28048 Change subject: mb/intel/gd43gt: Enable the GBE ...................................................................... mb/intel/gd43gt: Enable the GBE Change-Id: I94c917600421ee742ece7f6f71309da80261da28 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg43gt/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28048/1 diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index d3b2b6a..64b462f 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -49,7 +49,7 @@ RCBA8(0x31ff); RCBA32(0x3410) = 0x00060464; - RCBA32(0x3414) = 0x00000020; + RCBA32(RCBA_BUC) &= ~BUC_LAND; RCBA32(0x3418) = 0x01320001; RCBA32(0x341c) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; -- To view, visit https://review.coreboot.org/28048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I94c917600421ee742ece7f6f71309da80261da28 Gerrit-Change-Number: 28048 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: src/device/pci_early.c: Remove deprecated device_t
by Elyes HAOUAS (Code Review) 11 Aug '18

11 Aug '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28047 ) Change subject: src/device/pci_early.c: Remove deprecated device_t ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I30086d48a573e76f6dd577a3510fde3f50bd25c4 Gerrit-Change-Number: 28047 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/device/pci_early.c: Remove deprecated device_t
by Elyes HAOUAS (Code Review) 11 Aug '18

11 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28047 Change subject: src/device/pci_early.c: Remove deprecated device_t ...................................................................... src/device/pci_early.c: Remove deprecated device_t Use of device_t has been abandoned in ramstage. Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage. Change-Id: I30086d48a573e76f6dd577a3510fde3f50bd25c4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_early.c 1 file changed, 15 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28047/1 diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 6baebe0..34ed893 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> @@ -72,8 +70,11 @@ #if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) - -static void pci_bridge_reset_secondary(device_t p2p_bridge) +#ifdef __PRE_RAM__ +static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) +#else +static void pci_bridge_reset_secondary(struct device *p2p_bridge) +#endif { u16 reg16; @@ -90,7 +91,11 @@ pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); } -static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +#ifdef __PRE_RAM__ +static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary) +#else +static void pci_bridge_set_secondary(struct device *p2p_bridge, u8 secondary) +#endif { /* Disable config transaction forwarding. */ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); @@ -100,7 +105,11 @@ pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); } -static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +#ifdef __PRE_RAM__ +static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size) +#else +static void pci_bridge_set_mmio(struct device *p2p_bridge, u32 base, u32 size) +#endif { u16 reg16; -- To view, visit https://review.coreboot.org/28047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I30086d48a573e76f6dd577a3510fde3f50bd25c4 Gerrit-Change-Number: 28047 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mainboard/opencellular/elgon: Add mainboard support
by Patrick Rudolph (Code Review) 11 Aug '18

11 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28024 ) Change subject: mainboard/opencellular/elgon: Add mainboard support ...................................................................... Patch Set 5: (3 comments) https://review.coreboot.org/#/c/28024/5/src/mainboard/opencellular/elgon/Ma… File src/mainboard/opencellular/elgon/Makefile.inc: https://review.coreboot.org/#/c/28024/5/src/mainboard/opencellular/elgon/Ma… PS5, Line 35: gbcv2.dtb Actually it must be named sff8104-linux.dtb, see soc.c I'll remove the devicetree code from ATF as we don't need it at all, and than we don't need to include it into the CBFS. https://review.coreboot.org/#/c/28024/5/src/mainboard/opencellular/elgon/gb… File src/mainboard/opencellular/elgon/gbcv2.dts: https://review.coreboot.org/#/c/28024/5/src/mainboard/opencellular/elgon/gb… PS5, Line 195: serial@87e02a000000 I think there are only two UARTs exposed. The other entries could be removed. https://review.coreboot.org/#/c/28024/5/src/mainboard/opencellular/elgon/vb… File src/mainboard/opencellular/elgon/vboot.fmd: https://review.coreboot.org/#/c/28024/5/src/mainboard/opencellular/elgon/vb… PS5, Line 2: 0x63d4c0 Align to a supported flash protection range. 8 or 4 MiB. -- To view, visit https://review.coreboot.org/28024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Gerrit-Change-Number: 28024 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 11 Aug 2018 07:49:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sb/intel/{bd82x6x, ibexpeak}: Don't build with FAKE_IFD by default
by Tristan Corrick (Code Review) 11 Aug '18

11 Aug '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/28018 ) Change subject: sb/intel/{bd82x6x,ibexpeak}: Don't build with FAKE_IFD by default ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2c6a6586da9a6d26b0a5bf7d3ba8f3ffe3205647 Gerrit-Change-Number: 28018 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Aug 2018 05:04:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/lynxpoint: Don't build with FAKE_IFD by default
by Tristan Corrick (Code Review) 11 Aug '18

11 Aug '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/28009 ) Change subject: sb/intel/lynxpoint: Don't build with FAKE_IFD by default ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I21bc5bdc8b733fbfdb1b2a4fbcb572c76701074a Gerrit-Change-Number: 28009 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Aug 2018 05:04:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/braswell/Kconfig: Clean up redefined config options
by Tristan Corrick (Code Review) 11 Aug '18

11 Aug '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/28010 ) Change subject: soc/intel/braswell/Kconfig: Clean up redefined config options ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834 Gerrit-Change-Number: 28010 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Aug 2018 05:04:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware paths
by Tristan Corrick (Code Review) 11 Aug '18

11 Aug '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/28012 ) Change subject: mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware paths ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405 Gerrit-Change-Number: 28012 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Aug 2018 05:03:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/rambi: Don't set defaults for HAVE_IFD_BIN
by Tristan Corrick (Code Review) 11 Aug '18

11 Aug '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/28008 ) Change subject: mb/google/rambi: Don't set defaults for HAVE_IFD_BIN ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e Gerrit-Change-Number: 28008 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Aug 2018 05:03:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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