coreboot-gerrit August 2018

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Change in coreboot[master]: soc/intel/common: add more msr defines
by Matt Delco (Code Review) 13 Aug '18

13 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28067 to look at the new patch set (#2). Change subject: soc/intel/common: add more msr defines ...................................................................... soc/intel/common: add more msr defines This change adds some MSRs that are needed in a subsequent change to add support for Continuous Performance Control. Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/msr.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28067/2 -- To view, visit https://review.coreboot.org/28067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Gerrit-Change-Number: 28067 Gerrit-PatchSet: 2 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin
by Caveh Jalali (Code Review) 13 Aug '18

13 Aug '18

Hello caveh jalali, I'd like you to do a code review. Please visit https://review.coreboot.org/28070 to review the following change. Change subject: mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin ...................................................................... mb/google/atlas: Add DISPLAY_DCR_EN GPIO pin This defines new GPIO pin for controlling the display panel CABC function. BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28070/1 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 51dbf69..c0ef9ef 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -215,8 +215,8 @@ PAD_CFG_NC(GPP_E4), /* E5 : SATA_DEVSLP1 ==> NC */ PAD_CFG_NC(GPP_E5), - /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + /* E6 : SATA_DEVSLP2 ==> DISPLAY_DCR_EN */ + PAD_CFG_GPO(GPP_E6, 1, DEEP), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ -- To view, visit https://review.coreboot.org/28070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Gerrit-Change-Number: 28070 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: mb/google/atlas: Update DPTF sensor names
by Caveh Jalali (Code Review) 13 Aug '18

13 Aug '18

Hello caveh jalali, I'd like you to do a code review. Please visit https://review.coreboot.org/28069 to review the following change. Change subject: mb/google/atlas: Update DPTF sensor names ...................................................................... mb/google/atlas: Update DPTF sensor names This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28069/1 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index bb42351..685f4dd 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -18,22 +18,22 @@ #define DPTF_CPU_CRITICAL 105 #define DPTF_TSR0_SENSOR_ID 1 -#define DPTF_TSR0_SENSOR_NAME "systherm0" +#define DPTF_TSR0_SENSOR_NAME "Ambient" #define DPTF_TSR0_PASSIVE 48 #define DPTF_TSR0_CRITICAL 90 #define DPTF_TSR1_SENSOR_ID 2 -#define DPTF_TSR1_SENSOR_NAME "systherm1" +#define DPTF_TSR1_SENSOR_NAME "Charger" #define DPTF_TSR1_PASSIVE 48 #define DPTF_TSR1_CRITICAL 90 #define DPTF_TSR2_SENSOR_ID 3 -#define DPTF_TSR2_SENSOR_NAME "systherm2" +#define DPTF_TSR2_SENSOR_NAME "DRAM" #define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 -#define DPTF_TSR3_SENSOR_NAME "systherm3" +#define DPTF_TSR3_SENSOR_NAME "eMMC" #define DPTF_TSR3_PASSIVE 65 #define DPTF_TSR3_CRITICAL 75 -- To view, visit https://review.coreboot.org/28069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Gerrit-Change-Number: 28069 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: soc/intel/common/block/cpu: add function to init cppc_config
by Matt Delco (Code Review) 13 Aug '18

13 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28068 Change subject: soc/intel/common/block/cpu: add function to init cppc_config ...................................................................... soc/intel/common/block/cpu: add function to init cppc_config This change adds a method to init a cppc_config structure in a way that should ideally work across Intel processors that support EIST. Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 187 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28068/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a049..9191fd5 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -216,6 +216,185 @@ } /* + * Init cppc_config in a way that's appropriate for Intel + * processors with Intel Enhanced Speed Step Technology. + * NOTE: version 2 is expected to be the typical use case. + * For now this function 'punts' on version 3 and just + * populates the additional fields with 'unsupported'. + */ +void cpu_init_cppc_config(struct cppc_config *config, u32 version) +{ + acpi_addr_t msr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 8, + .bit_offset = 0, + { + .access_size = 4 + }, + .addrl = 0, + .addrh = 0, + }; + static const acpi_addr_t unsupported = { + .space_id = ACPI_ADDRESS_SPACE_MEMORY, + .bit_width = 0, + .bit_offset = 0, + { + .resv = 0 + }, + .addrl = 0, + .addrh = 0, + }; + + config->version = version; + + msr.addrl = MSR_HWP_CAPABILITIES; + + /* + * Highest Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)}, + */ + config->regs[CPPC_HIGHEST_PERF] = msr; + + /* + * Nominal Performance -> Guaranteed Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_NOMINAL_PERF] = msr; + + /* + * Lowest Nonlinear Performance -> Most Efficient Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, + */ + msr.bit_offset = 16; + config->regs[CPPC_LOWEST_NONL_PERF] = msr; + + /* + * Lowest Performance: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)}, + */ + msr.bit_offset = 24; + config->regs[CPPC_LOWEST_PERF] = msr; + + /* + * Guaranteed Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_GUARANTEED_PERF] = msr; + + msr.addrl = MSR_HWP_REQUEST; + + /* + * Desired Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)}, + */ + msr.bit_offset = 16; + config->regs[CPPC_DESIRED_PERF] = msr; + + /* + * Minimum Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)}, + */ + msr.bit_offset = 0; + config->regs[CPPC_MIN_PERF] = msr; + + /* + * Maximum Performance Register: + * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)}, + */ + msr.bit_offset = 8; + config->regs[CPPC_MAX_PERF] = msr; + + /* + * Performance Reduction Tolerance Register: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported; + + /* + * Time Window Register: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_TIME_WINDOW] = unsupported; + + /* + * Counter Wraparound Time: + * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + */ + config->regs[CPPC_COUNTER_WRAP] = unsupported; + + msr.addrl = MSR_MPERF; + + /* + * Reference Performance Counter Register: + * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)}, + */ + msr.bit_width = 64; + msr.bit_offset = 0; + config->regs[CPPC_REF_PERF_COUNTER] = msr; + + msr.addrl = MSR_APERF; + + /* + * Delivered Performance Counter Register: + * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)}, + */ + config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr; + + msr.addrl = MSR_HWP_STATUS; + + /* + * Performance Limited Register: + * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)}, + */ + msr.bit_width = 1; + msr.bit_offset = 2; + config->regs[CPPC_PERF_LIMITED] = msr; + + msr.addrl = MSR_PM_ENABLE; + + /* + * CPPC Enable Register: + * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)}, + */ + msr.bit_offset = 0; + config->regs[CPPC_ENABLE] = msr; + + if (version >= 2) { + /* Autonomous Selection Enable is populated below */ + + /* Autonomous Activity Window Register */ + config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = unsupported; + + /* Energy Performance Preference Register */ + config->regs[CPPC_PERF_PREF] = unsupported; + + /* Reference Performance */ + config->regs[CPPC_REF_PERF] = unsupported; + + if (version >= 3) { + /* Lowest Frequency */ + config->regs[CPPC_LOWEST_FREQ] = unsupported; + /* Nominal Frequency */ + config->regs[CPPC_NOMINAL_FREQ] = unsupported; + } + + /* + * Autonomous Selection Enable = 1 + * This field is actually the first addition in version 2 but + * it's so unlike the others I'm populating it last. + */ + msr.space_id = ACPI_ADDRESS_SPACE_MEMORY; + msr.bit_width = 32; + msr.bit_offset = 0; + msr.access_size = 0; + msr.addrl = 1; + config->regs[CPPC_AUTO_SELECT] = msr; + } +} + +/* * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode. */ diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 88f04b4..0071033 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -109,6 +109,14 @@ void cpu_disable_eist(void); /* + * Init CPPC block with MSRs for Intel Enhanced Speed Step Technology. + * Version 2 is suggested--this function's implementation of version 3 + * may have room for improvment. + */ +struct cppc_config; +void cpu_init_cppc_config(struct cppc_config *config, u32 version); + +/* * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode. */ -- To view, visit https://review.coreboot.org/28068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Gerrit-Change-Number: 28068 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: soc/intel/common: add more msr defines
by Matt Delco (Code Review) 13 Aug '18

13 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28067 Change subject: soc/intel/common: add more msr defines ...................................................................... soc/intel/common: add more msr defines This change adds some MSRs that are needed in a subsequent change to add support for Continuous Performance Control. Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/msr.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28067/1 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431..e588434 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -37,6 +37,8 @@ #define MSR_BIOS_UPGD_TRIG 0x7a #define SGX_ACTIVATE_BIT (1) #define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_MPERF 0xe7 +#define MSR_APERF 0xe8 #define MSR_POWER_MISC 0x120 #define ENABLE_IA_UNTRUSTED (1 << 6) #define FLUSH_DL1_L2 (1 << 8) @@ -118,6 +120,10 @@ #define PKG_POWER_LIMIT_TIME_MASK (0x7f) #define PKG_POWER_LIMIT_DUTYCYCLE_SHIFT 24 #define PKG_POWER_LIMIT_DUTYCYCLE_MASK (0x7f) +#define MSR_PM_ENABLE 0x770 +#define MSR_HWP_CAPABILITIES 0x771 +#define MSR_HWP_REQUEST 0x774 +#define MSR_HWP_STATUS 0x770 /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -- To view, visit https://review.coreboot.org/28067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Gerrit-Change-Number: 28067 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: arch/x86/acpigen: add methods for cppc
by Matt Delco (Code Review) 13 Aug '18

13 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28066 Change subject: arch/x86/acpigen: add methods for cppc ...................................................................... arch/x86/acpigen: add methods for cppc This change adds 2 methods for Conginuous Performance Control that was added in ACPI 5.0 and expanded twice in later versions. One function will create a global table based on a provided struct, while the other function is used to add a _CPC method in each processor object. Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 2 files changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28066/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index a614efb..06702ce 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1339,6 +1339,54 @@ acpigen_pop_len(); /* Method _DSM */ } +#define CPPC_PACKAGE_NAME "\\GCPC" + +void acpigen_write_CPPC_package(const struct cppc_config *config) +{ + u32 i; + u32 max; + switch (config->version) { + case 1: + max = CPPC_MAX_FIELDS_VER_1; + break; + case 2: + max = CPPC_MAX_FIELDS_VER_2; + break; + case 3: + max = CPPC_MAX_FIELDS_VER_3; + break; + default: + printk(BIOS_ERR, "ERROR: CPPC version %u is not implemented\n", + config->version); + return; + } + acpigen_write_name(CPPC_PACKAGE_NAME); + acpigen_write_package(max); + + acpigen_write_dword(max); + acpigen_write_byte(config->version); + + for (i = 0; i < max; ++i) { + const acpi_addr_t *reg = &(config->regs[i]); + if (reg->space_id == ACPI_ADDRESS_SPACE_MEMORY && + reg->bit_width == 32 && reg->access_size == 0) { + acpigen_write_dword(reg->addrl); + } else { + acpigen_write_register_resource(reg); + } + } + acpigen_pop_len(); +} + +void acpigen_write_CPPC_method(void) +{ + acpigen_write_method("_CPC", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(CPPC_PACKAGE_NAME); + acpigen_pop_len(); +} + + /* * Generate ACPI AML code for _ROM method. * This function takes as input ROM data and ROM length. diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 042c797..775339a 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -167,6 +167,56 @@ void *arg; }; +/*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */ +enum cppc_fields { + CPPC_HIGHEST_PERF, /* can be DWORD */ + CPPC_NOMINAL_PERF, /* can be DWORD */ + CPPC_LOWEST_NONL_PERF, /* can be DWORD */ + CPPC_LOWEST_PERF, /* can be DWORD */ + CPPC_GUARANTEED_PERF, + CPPC_DESIRED_PERF, + CPPC_MIN_PERF, + CPPC_MAX_PERF, + CPPC_PERF_REDUCE_TOLERANCE, + CPPC_TIME_WINDOW, + CPPC_COUNTER_WRAP, /* can be DWORD */ + CPPC_REF_PERF_COUNTER, + CPPC_DELIVERED_PERF_COUNTER, + CPPC_PERF_LIMITED, + CPPC_ENABLE, /* can be System I/O */ + CPPC_MAX_FIELDS_VER_1, + CPPC_AUTO_SELECT = /* can be DWORD */ + CPPC_MAX_FIELDS_VER_1, + CPPC_AUTO_ACTIVITY_WINDOW, + CPPC_PERF_PREF, + CPPC_REF_PERF, /* can be DWORD */ + CPPC_MAX_FIELDS_VER_2, + CPPC_LOWEST_FREQ = /* can be DWORD */ + CPPC_MAX_FIELDS_VER_2, + CPPC_NOMINAL_FREQ, /* can be DWORD */ + CPPC_MAX_FIELDS_VER_3, +}; + +struct cppc_config { + u32 version; /* must be 1, 2, or 3 */ + /* + * The generic acpi_addr_t structure is being used, though + * anything besides PPC or FFIXED generally requires checking + * if the OS has advertised support for it (via _OSC). + * + * NOTE: some fields permit DWORDs to be used. If you + * provide a System Memory register with all zeros (which + * represents unsupported) then this will be used as-is. + * Otherwise, a System Memory register with a 32-bit + * width will be converted into a DWORD field (the value + * of which will be the value of 'addrl'. Any other use + * of System Memory register is currently undefined. + * (i.e., if you have an actual need for System Memory + * then you'll need to adjust this kludge). + */ + acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3]; +}; + void acpigen_write_return_integer(uint64_t arg); void acpigen_write_return_string(const char *arg); void acpigen_write_len_f(void); @@ -269,6 +319,15 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count); /* + * Generate ACPI AML code for _CPC (Continuous Perfmance Control). + * Execute the package function once to create a global table, then + * execute the method function within each processor object to + * create a method that points to the global table. + */ +void acpigen_write_CPPC_package(const struct cppc_config *config); +void acpigen_write_CPPC_method(void); + +/* * Generate ACPI AML code for _ROM method. * This function takes as input ROM data and ROM length. * The ROM length has to be multiple of 4096 and has to be less -- To view, visit https://review.coreboot.org/28066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce Gerrit-Change-Number: 28066 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by AndreX Andraos (Code Review) 13 Aug '18

13 Aug '18

AndreX Andraos has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 2: > Only somewhat related, we've just added scan-build checking for > coreboot as well. > > There are a number of issues reported in soc/intel in the yorp > build. > > https://www.coreboot.org/scan-build/GOOGLE_YORP-scanbuild.chromeos/ Martin, What tool are you using for this code scan - we're not getting these "soc issues" flagged, using Klocwork Static Code Analysis tool? We are getting different "warnings" in chip.c and gspi.c files. -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 13 Aug 2018 19:23:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src: Remove duplicated 'include <device/device.h>'
by Elyes HAOUAS (Code Review) 13 Aug '18

13 Aug '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28064 Change subject: src: Remove duplicated 'include <device/device.h>' ...................................................................... src: Remove duplicated 'include <device/device.h>' Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/intel_ddi.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/link/i915.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/stargo2/mainboard.c M src/mainboard/intel/wtm2/mainboard.c 9 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28064/1 diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index c01aef4..93aa87d 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -29,7 +29,6 @@ #include <string.h> #include <stdlib.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index ae51d9e..bbfd385 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -23,7 +23,6 @@ #include <boot/coreboot_tables.h> #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index da6d698..8b8000c 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -17,7 +17,6 @@ #include <string.h> #include <stdlib.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 6f529da..91b7e59 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index eb2e6ab..641b4de 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 9443d28..582583a 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -18,7 +18,6 @@ #include <string.h> #include <smbios.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 869a6cc..8c8ae40 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/intel/stargo2/mainboard.c b/src/mainboard/intel/stargo2/mainboard.c index da93acd..c2b5d7d 100644 --- a/src/mainboard/intel/stargo2/mainboard.c +++ b/src/mainboard/intel/stargo2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/acpi.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 6ec6dab..83975db 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> -- To view, visit https://review.coreboot.org/28064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Gerrit-Change-Number: 28064 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by John Zhao (Code Review) 13 Aug '18

13 Aug '18

John Zhao has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… PS1, Line 137: assert > Note that asserts are typically non-fatal in coreboot, so this may not fix your issue. Links are downstream buses attached to the device as: DEVTREE_CONST struct bus *link_list assert(dev->link_list != NULL) would avoid NULL pointer to be dereferenced. -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 13 Aug 2018 18:18:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by John Zhao (Code Review) 13 Aug '18

13 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28060 to look at the new patch set (#2). Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... intel/common/block: Fix issues found by klockwork src/soc/intel/common/block/cpu/mp_init.c Function init_cpus: Pointer dev checked for NULL may be dereferenced. src/soc/intel/common/block/graphics/graphics.c Function graphics_get_bar: Pointer dev returned from call may be NULL and will be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/28060/2 -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit August 2018