coreboot-gerrit August 2018

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Change in coreboot[master]: riscv: add support for supervisor binary interface (SBI)
by Xiang Wang (Code Review) 15 Aug '18

15 Aug '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28096 Change subject: riscv: add support for supervisor binary interface (SBI) ...................................................................... riscv: add support for supervisor binary interface (SBI) SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Makefile.inc A src/arch/riscv/include/sbi.h A src/arch/riscv/sbi.c M src/arch/riscv/trap_handler.c 4 files changed, 175 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28096/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 89feb1b..eae0f0a 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -45,6 +45,7 @@ bootblock-y += trap_handler.c bootblock-y += fp_asm.S bootblock-y += misaligend.c +bootblock-y += sbi.c bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c diff --git a/src/arch/riscv/include/sbi.h b/src/arch/riscv/include/sbi.h new file mode 100644 index 0000000..2c6106d --- /dev/null +++ b/src/arch/riscv/include/sbi.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define IPI_SOFT 1 +#define IPI_FENCE_I 2 +#define IPI_SFENCE_VMA 4 +#define IPI_SFENCE_VMA_ASID 8 +#define IPI_SHUTDOWN 16 + +void handle_sbi(trapframe *tf); + diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c new file mode 100644 index 0000000..e76e152 --- /dev/null +++ b/src/arch/riscv/sbi.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mcall.h> +#include <stdint.h> +#include <compiler.h> +#include <arch/exception.h> +#include <sbi.h> +#include <vm.h> +#include <console/uart.h> + +void set_msip(int hartid, int val); + +/* FIXME: removed when implemented by a specific platform */ +__weak void set_msip(int hartid, int val) { } + +static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type) +{ + uintptr_t mask = mprv_read_ulong((unsigned long *)pmask); + for (int i = 0; mask; i++) { + if (mask & 1) { + OTHER_HLS(i)->ipi_pending |= type; + /* send soft interrupt to target hart */ + set_msip(i, 1); + } + mask = mask >> 1; + } + return 0; +} + +static uintptr_t sbi_set_timer(uint64_t when) +{ + *(HLS()->timecmp) = when; + clear_csr(mip, MIP_STIP); + set_csr(mie, MIP_MTIP); + return 0; +} + +static uintptr_t sbi_console_putchar(uint8_t ch) +{ +#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + uart_tx_byte(CONFIG_UART_FOR_CONSOLE, ch); + return 0; +#else + return -1; +#endif +} + +static uintptr_t sbi_console_getchar(void) +{ +#if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); +#else + return -1; +#endif +} + +static uintptr_t sbi_clear_ipi(void) +{ + return clear_csr(mip, MIP_SSIP) & MIP_SSIP; +} + +void handle_sbi(trapframe *tf) +{ +#define arg0 (tf->gpr[10]) +#define arg1 (tf->gpr[11]) +#define arg2 (tf->gpr[12]) +#define which (tf->gpr[17]) +#define ret (tf->gpr[10]) + switch (which) { + case SBI_SET_TIMER: +#if __riscv_xlen == 32 + ret = sbi_set_timer(arg0 + ((uint64_t)arg1 << 32)); +#else + ret = sbi_set_timer(arg0); +#endif + break; + case SBI_CONSOLE_PUTCHAR: + ret = sbi_console_putchar(arg0); + break; + case SBI_CONSOLE_GETCHAR: + ret = sbi_console_getchar(); + break; + case SBI_CLEAR_IPI: + ret = sbi_clear_ipi(); + break; + case SBI_SEND_IPI: + ret = send_ipi((uintptr_t *)arg0, IPI_SOFT); + break; + case SBI_REMOTE_FENCE_I: + ret = send_ipi((uintptr_t *)arg0, IPI_FENCE_I); + break; + case SBI_REMOTE_SFENCE_VMA: + ret = send_ipi((uintptr_t *)arg0, IPI_SFENCE_VMA); + break; + case SBI_REMOTE_SFENCE_VMA_ASID: + ret = send_ipi((uintptr_t *)arg0, IPI_SFENCE_VMA_ASID); + break; + case SBI_SHUTDOWN: + ret = send_ipi((uintptr_t *)arg0, IPI_SHUTDOWN); + break; + } +} + + + + + + + diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index e9771af..d4c3932 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <string.h> #include <vm.h> +#include <mcall.h> +#include <sbi.h> static uint64_t *time; static uint64_t *timecmp; @@ -135,6 +137,20 @@ msip |= SIP_STIP; write_csr(mip, msip); break; + case IRQ_M_SOFT: + if (HLS()->ipi_pending & IPI_SOFT) { + set_csr(mip, MIP_SSIP); + } else if (HLS()->ipi_pending & IPI_FENCE_I) { + asm("fence.i"); + } else if (HLS()->ipi_pending & IPI_SFENCE_VMA) { + asm("sfence.vma"); + } else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) { + asm("sfence.vma"); + } else if (HLS()->ipi_pending & IPI_SHUTDOWN) { + while (HLS()->ipi_pending & IPI_SHUTDOWN) + asm("wfi"); + } + break; default: printk(BIOS_EMERG, "======================================\n"); printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n", @@ -161,6 +177,9 @@ case CAUSE_STORE_ACCESS: case CAUSE_USER_ECALL: case CAUSE_SUPERVISOR_ECALL: + print_trap_information(tf); + handle_sbi(tf); + return; case CAUSE_HYPERVISOR_ECALL: case CAUSE_MACHINE_ECALL: print_trap_information(tf); -- To view, visit https://review.coreboot.org/28096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Gerrit-Change-Number: 28096 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: google/grunt/aleena: Update Raydium TS device ACPI nodes
by Tim Chen (Code Review) 15 Aug '18

15 Aug '18

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/28095 to review the following change. Change subject: google/grunt/aleena: Update Raydium TS device ACPI nodes ...................................................................... google/grunt/aleena: Update Raydium TS device ACPI nodes change I2C irq to EDGE trigger BUG=b:112616824 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: I86ec32bb3f2626e65d76c3259e3c4244a970e5de Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/28095/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index b330ec5..61476a2 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -140,7 +140,7 @@ register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" -- To view, visit https://review.coreboot.org/28095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I86ec32bb3f2626e65d76c3259e3c4244a970e5de Gerrit-Change-Number: 28095 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headers
by Richard Spiegel (Code Review) 15 Aug '18

15 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28093 Change subject: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headers ...................................................................... src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headers Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed. BUG=b:112602580 TEST=Build grunt and gardenia. Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h M src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h 4 files changed, 0 insertions(+), 573 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/28093/1 diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h deleted file mode 100644 index c84bd00..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h +++ /dev/null @@ -1,93 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH ACPI lib - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _FCH_ACPILIB_H_ -#define _FCH_ACPILIB_H_ -/// -/// RSDP - ACPI 2.0 table RSDP -/// -typedef struct _RSDP_HEADER { - UINT64 Signature; ///< RSDP signature "RSD PTR" - UINT8 CheckSum; ///< checksum of the first 20 bytes - UINT8 OEMID[6]; ///< OEM ID - UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0 - UINT32 RsdtAddress; ///< physical address of RSDT - UINT32 Length; ///< total length of RSDP (including extended part) - UINT64 XsdtAddress; ///< physical address of XSDT - UINT8 ExtendedCheckSum; ///< chechsum of whole table - UINT8 Reserved[3]; ///< Reserved -} RSDP_HEADER; - -/// -/// DESCRIPTION_HEADER - ACPI common table header -/// -typedef struct _DESCRIPTION_HEADER { - UINT32 Signature; ///< ACPI signature (4 ASCII characters) - UINT32 Length; ///< Length of table, in bytes, including header - UINT8 Revision; ///< ACPI Specification minor version # - UINT8 CheckSum; ///< To make sum of entire table == 0 - UINT8 OemId[6]; ///< OEM identification - UINT8 OemTableId[8]; ///< OEM table identification - UINT32 OemRevision; ///< OEM revision number - UINT32 CreatorId; ///< ASL compiler vendor ID - UINT32 CreatorRevision; ///< ASL compiler revision number -} DESCRIPTION_HEADER; - -/// -/// _AcpiRegWrite - ACPI MMIO register R/W structure -/// -typedef struct _ACPI_REG_WRITE { - UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02) - UINT8 MmioReg; /// MmioReg : Register index - UINT8 DataAndMask; /// DataANDMask : AND Register Data - UINT8 DataOrMask; /// DataOrMask : Or Register Data -} ACPI_REG_WRITE; - -VOID* AcpiLocateTable (IN UINT32 Signature); -VOID AcpiSetTableCheckSum (IN VOID *TablePtr); -UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr); -UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length); - -#endif diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h deleted file mode 100644 index 8208294..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h +++ /dev/null @@ -1,69 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH BIOS Ram usage - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _FCH_BIOS_RAM_USAGE_H_ -#define _FCH_BIOS_RAM_USAGE_H_ - -#define RESTORE_MEMORY_CONTROLLER_START 0 -#define XHCI_REGISTER_BAR00 0xD0 -#define XHCI_REGISTER_BAR01 0xD1 -#define XHCI_REGISTER_BAR02 0xD2 -#define XHCI_REGISTER_BAR03 0xD3 -#define XHCI_REGISTER_04H 0xD4 -#define XHCI_REGISTER_0CH 0xD5 -#define XHCI_REGISTER_3CH 0xD6 -#define XHCI1_REGISTER_BAR00 0xE0 -#define XHCI1_REGISTER_BAR01 0xE1 -#define XHCI1_REGISTER_BAR02 0xE2 -#define XHCI1_REGISTER_BAR03 0xE3 -#define XHCI1_REGISTER_04H 0xE4 -#define XHCI1_REGISTER_0CH 0xE5 -#define XHCI1_REGISTER_3CH 0xE6 -#define RTC_WORKAROUND_DATA_START 0xF0 -#define BOOT_TIME_FLAG_SEC 0xF8 -#define BOOT_TIME_FLAG_INT19 0xFC - -#endif - diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h deleted file mode 100644 index aa11396..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h +++ /dev/null @@ -1,408 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH routine definition - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include <check_for_wrapper.h> - -#ifndef _FCH_DEF_H_ -#define _FCH_DEF_H_ - - -UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); -VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); -VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); -VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); -VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl); -VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); -VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader); -VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader); -UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader); -UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN FchCheckBR_ST (IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN FchCheckBR (IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN FchCheckST (IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader); -UINT64 FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader); -VOID FchInitResetRequest (IN AMD_CONFIG_PARAMS *StdHeader); - -/// -/// Fch Ab Routines -/// -/// Pei Phase -/// -VOID FchInitResetAb (IN VOID* FchDataPtr); -VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvAb (IN VOID* FchDataPtr); -VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr); -VOID FchInitMidAb (IN VOID* FchDataPtr); -VOID FchInitLateAb (IN VOID* FchDataPtr); -/// -/// Other Public Routines -/// -VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr); -BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader); -VOID FchAbLateProgram (IN VOID* FchDataPtr); - -/// -/// Fch Pcie Routines -/// -/// -/// Dxe Phase -/// -VOID ProgramPcieNativeMode (IN VOID* FchDataPtr); - -/// -/// Fch Gpp Routines -/// - -/// -/// Common Gpp Routines -/// -VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); - -/// -/// Fch Azalia Routines -/// -/// Pei Phase -/// -VOID FchInitResetAzalia (IN VOID *FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvAzalia (IN VOID *FchDataPtr); -VOID FchInitMidAzalia (IN VOID *FchDataPtr); -VOID FchInitLateAzalia (IN VOID *FchDataPtr); - - -/// -/// Fch HwAcpi Routines -/// -/// Pei Phase -/// -VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr); -VOID FchInitResetHwAcpi (IN VOID *FchDataPtr); -VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr); -VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr); -VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr); -VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr); -VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr); -VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr); -VOID FchInitMidHwAcpi (IN VOID *FchDataPtr); -VOID FchInitLateHwAcpi (IN VOID *FchDataPtr); - -/// -/// Other Public Routines -/// -VOID HpetInit (IN VOID *FchDataPtr); -VOID MtC1eEnable (IN VOID *FchDataPtr); -VOID GcpuRelatedSetting (IN VOID *FchDataPtr); -VOID StressResetModeLate (IN VOID *FchDataPtr); - -/// -/// Fch Hwm Routines -/// -/// Pei Phase -/// -VOID FchInitResetHwm (IN VOID* FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvHwm (IN VOID* FchDataPtr); -VOID FchInitMidHwm (IN VOID* FchDataPtr); -VOID FchInitLateHwm (IN VOID* FchDataPtr); -/// -/// Other Public Routines -/// -VOID HwmInitRegister (IN VOID* FchDataPtr); -VOID FchECfancontrolservice (IN VOID* FchDataPtr); - - -/// -/// Fch EC Routines -/// -/// Pei Phase -/// -VOID FchInitResetEc (IN VOID *FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvEc (IN VOID *FchDataPtr); -VOID FchInitMidEc (IN VOID *FchDataPtr); -VOID FchInitLateEc (IN VOID *FchDataPtr); -/// -/// Other Public Routines -/// -VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); -VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader); - -/// -/// Fch Ir Routines -/// -/// Dxe Phase -/// -VOID FchInitEnvIr (IN VOID* FchDataPtr); -VOID FchInitMidIr (IN VOID* FchDataPtr); -VOID FchInitLateIr (IN VOID* FchDataPtr); - -/// -/// Fch SATA Routines -/// -/// Pei Phase -/// -VOID FchInitResetSata (IN VOID *FchDataPtr); -VOID FchInitResetSataProgram (IN VOID *FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitMidSata (IN VOID *FchDataPtr); -VOID FchInitEnvSata (IN VOID *FchDataPtr); -VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr); -VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr); -VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr); - -VOID FchInitLateSata (IN VOID *FchDataPtr); -VOID FchInitEnvSataIde (IN VOID *FchDataPtr); -VOID FchInitMidSataIde (IN VOID *FchDataPtr); -VOID FchInitLateSataIde (IN VOID *FchDataPtr); -VOID FchInitEnvSataAhci (IN VOID *FchDataPtr); -VOID FchInitMidSataAhci (IN VOID *FchDataPtr); -VOID FchInitLateSataAhci (IN VOID *FchDataPtr); -VOID FchInitEnvSataRaid (IN VOID *FchDataPtr); -VOID FchInitMidSataRaid (IN VOID *FchDataPtr); -VOID FchInitLateSataRaid (IN VOID *FchDataPtr); -VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr); -VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr); -VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr); - -VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr); -VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr); -VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr); -VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader); -VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); -VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); -VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); -VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr); -VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr); -VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); -VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); -VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); -VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); -VOID SataBar5RegSet (IN VOID *FchDataPtr); -VOID SataSetPortGenMode (IN VOID *FchDataPtr); -VOID FchSataSetPortGenMode (IN VOID *FchDataPtr); -VOID FchProgramSataPhy (IN VOID *FchDataPtr); -VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr); - -/// -/// FCH USB Controller Public Function -/// -/// Pei Phase -/// -VOID FchInitResetUsb (IN VOID *FchDataPtr); -VOID FchInitResetEhci (IN VOID *FchDataPtr); -VOID FchInitResetXhci (IN VOID *FchDataPtr); -VOID FchInitResetXhciProgram (IN VOID *FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvUsb (IN VOID *FchDataPtr); -VOID FchInitMidUsb (IN VOID *FchDataPtr); -VOID FchInitLateUsb (IN VOID *FchDataPtr); -VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr); -VOID FchInitMidUsbEhci (IN VOID *FchDataPtr); -VOID FchInitLateUsbEhci (IN VOID *FchDataPtr); -VOID FchEhciDebugPortService (IN VOID *FchDataPtr); -VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr); -VOID FchInitMidUsbXhci (IN VOID *FchDataPtr); -VOID FchInitLateUsbXhci (IN VOID *FchDataPtr); -VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr); -/// -/// Other Public Routines -/// -VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); -VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); -VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr); -VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr); -VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr); -VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr); -UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr); - -/// -/// Fch Sd Routines -/// -VOID FchInitEnvSd (IN VOID *FchDataPtr); -VOID FchInitMidSd (IN VOID *FchDataPtr); -VOID FchInitLateSd (IN VOID *FchDataPtr); - -/// -/// Other Public Routines -/// - -VOID FchInitEnvSdProgram (IN VOID *FchDataPtr); - -/// -/// Fch Spi Routines -/// -/// Pei Phase -/// -VOID FchInitResetSpi (IN VOID *FchDataPtr); -VOID FchInitResetLpc (IN VOID *FchDataPtr); -VOID FchInitResetLpcProgram (IN VOID *FchDataPtr); -/// -/// Dxe Phase -/// -VOID FchInitEnvSpi (IN VOID *FchDataPtr); -VOID FchInitMidSpi (IN VOID *FchDataPtr); -VOID FchInitLateSpi (IN VOID *FchDataPtr); -VOID FchInitEnvLpc (IN VOID *FchDataPtr); -VOID FchInitMidLpc (IN VOID *FchDataPtr); -VOID FchInitLateLpc (IN VOID *FchDataPtr); -VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); -/// -/// Other Public Routines -/// -VOID FchSpiUnlock (IN VOID *FchDataPtr); -VOID FchSpiLock (IN VOID *FchDataPtr); -VOID FchUsb3D3ColdCallback (IN VOID *FchDataPtr); -VOID FchUsb3D0Callback (IN VOID *FchDataPtr); - -/*--------------------------- Documentation Pages ---------------------------*/ -VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); -VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); -VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader); -VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); -VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); -VOID TurnOffCG2 (OUT VOID); -VOID BackUpCG2 (OUT VOID); -VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); -VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID AcLossControl (IN UINT8 AcLossControlValue); -VOID FchVgaInit (OUT VOID); -VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr); -VOID ValidateFchVariant (IN VOID *FchDataPtr); -VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); -VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr); -VOID SbSleepTrapControl (IN BOOLEAN SleepTrap); - -AGESA_STATUS -FchSpiTransfer ( - IN UINT8 PrefixCode, - IN UINT8 Opcode, - IN OUT UINT8 *DataPtr, - IN UINT8 *AddressPtr, - IN UINT8 Length, - IN BOOLEAN WriteFlag, - IN BOOLEAN AddressFlag, - IN BOOLEAN DataFlag, - IN BOOLEAN FinishedFlag - ); - -BOOLEAN -FchConfigureSpiDeviceDummyCycle ( - IN UINT32 DeviceID, - IN UINT8 SpiMode - ); - -UINT32 -FchReadSpiId ( - IN BOOLEAN Flag - ); - -BOOLEAN -FchPlatformSpiQe ( - IN VOID *FchDataPtr - ); - -FCH_DATA_BLOCK* -FchInitLoadDataBlock ( - IN FCH_INTERFACE *FchInterface, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -FCH_DATA_BLOCK* -FchInitEnvCreatePrivateData ( - IN AMD_ENV_PARAMS *EnvParams - ); - -FCH_RESET_DATA_BLOCK* -FchInitResetLoadPrivateDefault ( - IN AMD_RESET_PARAMS *ResetParams - ); - -VOID -RetrieveDataBlockFromInitReset ( - IN FCH_DATA_BLOCK *FchParams - ); - -#endif diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h index 04784fe..118473c 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h @@ -110,9 +110,6 @@ #include "Fch.h" #include "amdlib.h" #include "FchCommonCfg.h" -#include "AcpiLib.h" -#include "FchDef.h" -#include "FchBiosRamUsage.h" #include "AmdFch.h" extern CONST BUILD_OPT_CFG UserOptions; -- To view, visit https://review.coreboot.org/28093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65 Gerrit-Change-Number: 28093 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: google/grunt: Remove BayHub EMMC driving strength override
by Martin Roth (Code Review) 14 Aug '18

14 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28084 ) Change subject: google/grunt: Remove BayHub EMMC driving strength override ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Gerrit-Change-Number: 28084 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 23:43:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Remove duplicated 'include <device/device.h>'
by Martin Roth (Code Review) 14 Aug '18

14 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28064 ) Change subject: src: Remove duplicated 'include <device/device.h>' ...................................................................... src: Remove duplicated 'include <device/device.h>' Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28064 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/gma/intel_ddi.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/link/i915.c M src/mainboard/google/link/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/stargo2/mainboard.c M src/mainboard/intel/wtm2/mainboard.c 9 files changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index c01aef4..93aa87d 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -29,7 +29,6 @@ #include <string.h> #include <stdlib.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index ae51d9e..bbfd385 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -23,7 +23,6 @@ #include <boot/coreboot_tables.h> #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index da6d698..8b8000c 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -17,7 +17,6 @@ #include <string.h> #include <stdlib.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 6f529da..91b7e59 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index eb2e6ab..641b4de 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 9443d28..582583a 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -18,7 +18,6 @@ #include <string.h> #include <smbios.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 869a6cc..8c8ae40 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/intel/stargo2/mainboard.c b/src/mainboard/intel/stargo2/mainboard.c index da93acd..c2b5d7d 100644 --- a/src/mainboard/intel/stargo2/mainboard.c +++ b/src/mainboard/intel/stargo2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/acpi.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 6ec6dab..83975db 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <string.h> #include <device/device.h> -#include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> -- To view, visit https://review.coreboot.org/28064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Gerrit-Change-Number: 28064 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by John Zhao (Code Review) 14 Aug '18

14 Aug '18

John Zhao has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… PS1, Line 137: assert > I agree with Hannah's approach. […] While I referred to coreboot_serial.config, it appears CONFIG_FATAL_ASSERTS=y. Then any assert(0) will cause execution halt while booting image.serial.bin(debug). Yes, I agree no execution halt for image.bin(release) since FATAL_ASSERT is not set. -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 22:06:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Add bootblock_fch_init
by Martin Roth (Code Review) 14 Aug '18

14 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28059 ) Change subject: soc/amd/stoneyridge: Add bootblock_fch_init ...................................................................... soc/amd/stoneyridge: Add bootblock_fch_init Add a method in bootblock that can be used for printing registers. BUG=none TEST=compiled grunt Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/28059 Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 7b2c420..c2440b0 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -106,6 +106,8 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + bootblock_fch_init(); + /* Initialize any early i2c buses. */ i2c_soc_early_init(); } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 64b4b46..c6f7791 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -449,6 +449,7 @@ void xhci_pm_write32(uint8_t reg, uint32_t value); uint32_t xhci_pm_read32(uint8_t reg); void bootblock_fch_early_init(void); +void bootblock_fch_init(void); /** * @brief Save the UMA bize returned by AGESA * diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a6219b4..c4b8d04 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -621,6 +621,7 @@ } } +/* Before console init */ void bootblock_fch_early_init(void) { int reboot = 0; @@ -643,6 +644,9 @@ enable_aoac_devices(); } +/* After console init */ +void bootblock_fch_init(void) {} + void sb_enable(device_t dev) { printk(BIOS_DEBUG, "%s\n", __func__); -- To view, visit https://review.coreboot.org/28059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 Gerrit-Change-Number: 28059 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Add bootblock_fch_init
by Martin Roth (Code Review) 14 Aug '18

14 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28059 ) Change subject: soc/amd/stoneyridge: Add bootblock_fch_init ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 Gerrit-Change-Number: 28059 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 Aug 2018 21:54:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/common/block: Fix issues found by klockwork
by Martin Roth (Code Review) 14 Aug '18

14 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28060 ) Change subject: intel/common/block: Fix issues found by klockwork ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/#/c/28060/1/src/soc/intel/common/block/cpu/mp_i… PS1, Line 137: assert > Looks like CONFIG_FATAL_ASSERTS is on. […] I agree with Hannah's approach. I don't understand what you mean by "it looks like CONFIG_FATAL_ASSERTS is on". It's a kconfig option. It may be on in your particular config, but that doesn't mean that it's on in all configs. You *CANNOT* rely on asserts to guard your code in coreboot. -- To view, visit https://review.coreboot.org/28060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Gerrit-Change-Number: 28060 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 14 Aug 2018 21:51:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Stoneyridge: Remove VENDORCODE_FULL_SUPPORT
by Richard Spiegel (Code Review) 14 Aug '18

14 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28092 Change subject: Stoneyridge: Remove VENDORCODE_FULL_SUPPORT ...................................................................... Stoneyridge: Remove VENDORCODE_FULL_SUPPORT Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal of VENDORCODE_FULL_SUPPORT from coreboot. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Kconfig M src/vendorcode/amd/pi/00670F00/Makefile.inc D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c D src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c 6 files changed, 0 insertions(+), 405 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28092/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 594d22c..2716c8c 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -377,11 +377,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -config VENDORCODE_FULL_SUPPORT - def_bool n - help - This option determines if all files under - vendorcode/amd/pi/00670F00/ will be compiled or only - selected procedures of source files (minimum required). - endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index bd807a9..ad3955c 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -90,9 +90,6 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) -ifeq ($(CONFIG_VENDORCODE_FULL_SUPPORT),y) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) -endif agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c deleted file mode 100644 index 01ae71e..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c +++ /dev/null @@ -1,79 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH IO access common routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#include "FchPlatform.h" -#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE - -/**< FchStall - Reserved */ -VOID -FchStall ( - IN UINT32 uSec, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT16 timerAddr; - UINT32 startTime; - UINT32 elapsedTime; - - LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); - if ( timerAddr == 0 ) { - uSec = uSec / 2; - while ( uSec != 0 ) { - LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader); - uSec--; - } - } else { - LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); - for ( ;; ) { - LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); - if ( elapsedTime < startTime ) { - elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; - } else { - elapsedTime = elapsedTime - startTime; - } - if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { - break; - } - } - } -} - diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c deleted file mode 100644 index 2b70e17..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c +++ /dev/null @@ -1,95 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH IO access common routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include "FchPlatform.h" -#include "cpuFamilyTranslation.h" - /* - * Headers removed for coreboot. - * #include "Porting.h" - * #include "AMD.h" - * #include "amdlib.h" - * #include "heapManager.h" - */ -#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE - -/** - * GetChipSysMode - Get Chip status - * - * - * @param[in] Value - Return Chip strap status - * StrapStatus [15.0] - Hudson-2 chip Strap Status - * @li 0001 - Not USED FWH - * @li 0002 - Not USED LPC ROM - * @li 0004 - EC enabled - * @li 0008 - Reserved - * @li 0010 - Internal Clock mode - * @param[in] StdHeader - * - */ -VOID -GetChipSysMode ( - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader); -} - -/** - * IsImcEnabled - Is IMC Enabled - * @retval TRUE for IMC Enabled; FALSE for IMC Disabled - */ -BOOLEAN -IsImcEnabled ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 dbSysConfig; - GetChipSysMode (&dbSysConfig, StdHeader); - if (dbSysConfig & ChipSysEcEnable) { - return TRUE; - } else { - return FALSE; - } -} - diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c deleted file mode 100644 index de263dd..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c +++ /dev/null @@ -1,147 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH memory access lib - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#include "FchPlatform.h" - /* - * Header removed for coreboot. - * #include "Ids.h" - */ -#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE - - -/** - * ReadMem - Read FCH BAR Memory - * - * @param[in] Address - Memory BAR address - * @param[in] OpFlag - Access width - * @param[in] *ValuePtr - In/Out value pointer - * - */ -VOID -ReadMem ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID *ValuePtr - ) -{ - OpFlag = OpFlag & 0x7f; - - switch ( OpFlag ) { - case AccessWidth8: - *((UINT8*)ValuePtr) = *((volatile UINT8*) ((UINTN)Address)); - break; - - case AccessWidth16: - *((UINT16*)ValuePtr) = *((volatile UINT16*) ((UINTN)Address)); - break; - - case AccessWidth32: - *((UINT32*)ValuePtr) = *((volatile UINT32*) ((UINTN)Address)); - break; - - default: - ASSERT (FALSE); - break; - } -} - -/** - * WriteMem - Write FCH BAR Memory - * - * @param[in] Address - Memory BAR address - * @param[in] OpFlag - Access width - * @param[in] *ValuePtr - In/Out Value pointer - * - */ -VOID -WriteMem ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID *ValuePtr - ) -{ - OpFlag = OpFlag & 0x7f; - - switch ( OpFlag ) { - case AccessWidth8 : - *((volatile UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr); - break; - - case AccessWidth16: - *((volatile UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr); - break; - - case AccessWidth32: - *((volatile UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr); - break; - - default: - ASSERT (FALSE); - break; - } -} - -/** - * RwMem - Read & Write FCH BAR Memory - * - * @param[in] Address - Memory BAR address - * @param[in] OpFlag - Access width - * @param[in] Mask - Mask Value of data - * @param[in] Data - Write data - * - */ -VOID -RwMem ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data - ) -{ - UINT32 Result; - - ReadMem (Address, OpFlag, &Result); - Result = (Result & Mask) | Data; - WriteMem (Address, OpFlag, &Result); - ReadMem (Address, OpFlag, &Result); -} - diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c deleted file mode 100644 index 136353e..0000000 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c +++ /dev/null @@ -1,74 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH PCI access lib - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision$ @e \$Date$ - * - */ - /***************************************************************************** - * - * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ -#include "FchPlatform.h" -#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE - -VOID -ReadPci ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - - PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); - LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); -} - - -VOID -WritePci ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - PCI_ADDR PciAddress; - - PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); - LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); -} - -- To view, visit https://review.coreboot.org/28092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996 Gerrit-Change-Number: 28092 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit August 2018