coreboot-gerrit August 2018

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Change in coreboot[master]: Kconfig: add option for convertible
by Matt Delco (Code Review) 15 Aug '18

15 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28105 Change subject: Kconfig: add option for convertible ...................................................................... Kconfig: add option for convertible This change adds a boolean open to flag if a device is a convertible. This can be used to control SMBIOS enclosure type, and will be used in a later change to control the presense of an ACPI tablet model device when using a Chrome EC. Change-Id: I2cc47d3b6233198a35ffb9844ef4a839328238d5 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/Kconfig M src/arch/x86/acpi.c 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28105/1 diff --git a/src/Kconfig b/src/Kconfig index bce3e32..0e40e2a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -336,6 +336,11 @@ default n bool +# controls chasis type (and tablet mode detection with Chrome EC) +config SYSTEM_TYPE_CONVERTIBLE + default n + bool + config CBFS_AUTOGEN_ATTRIBUTES default n bool @@ -659,11 +664,13 @@ hex depends on GENERATE_SMBIOS_TABLES default 0x09 if SYSTEM_TYPE_LAPTOP + default 0x1f if SYSTEM_TYPE_CONVERTIBLE default 0x03 help System Enclosure or Chassis Types as defined in SMBIOS specification. The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or - SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set. + SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set or + SMBIOS_ENCLOSURE_CONVERTIBLE (0x1f) if SYSTEM_TYPE_CONVERTIBLE is set endmenu diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8d7579d..e294695 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -980,7 +980,8 @@ fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - if (IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP)) + if (IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP) || + IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE)) fadt->preferred_pm_profile = PM_MOBILE; else fadt->preferred_pm_profile = PM_DESKTOP; -- To view, visit https://review.coreboot.org/28105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2cc47d3b6233198a35ffb9844ef4a839328238d5 Gerrit-Change-Number: 28105 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: ec/google/chromeec: add KConfig option for tablet mode
by Matt Delco (Code Review) 15 Aug '18

15 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28106 Change subject: ec/google/chromeec: add KConfig option for tablet mode ...................................................................... ec/google/chromeec: add KConfig option for tablet mode This option will eventually replace the #define used by various instances of ec.h. Change-Id: I158d153297b5561e49c3fe0b287b7e0e066a5f94 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/ec/google/chromeec/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28106/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 1d59f1a..bd7bb0f 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -178,3 +178,9 @@ help Enable support for Chrome OS mode switches provided by the Chrome OS EC. + +config EC_GOOGLE_CHROMEEC_ACPI_TABLET_DEVICE + depends on EC_GOOGLE_CHROMEEC_LPC && SYSTEM_TYPE_CONVERTIBLE + def_bool n + help + Enable tablet mode device in ACPI. -- To view, visit https://review.coreboot.org/28106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I158d153297b5561e49c3fe0b287b7e0e066a5f94 Gerrit-Change-Number: 28106 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: security/tpm: Fix TPM 1.2 state machine issues
by Philipp Deppenwiese (Code Review) 15 Aug '18

15 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28085 to look at the new patch set (#2). Change subject: security/tpm: Fix TPM 1.2 state machine issues ...................................................................... security/tpm: Fix TPM 1.2 state machine issues * Add hard_reset mechanism and result checks for the ramstage TPM driver. * Move enabling TPM before activating otherwise it isn't successful. More information can be found via the TCG specification. Tested=Elgon Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/drivers/tpm/tpm.c M src/security/tpm/tspi/tspi.c 2 files changed, 24 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28085/2 -- To view, visit https://review.coreboot.org/28085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b Gerrit-Change-Number: 28085 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: lib/fit_payload: Add coreboot tables support for FDT.
by Philipp Deppenwiese (Code Review) 15 Aug '18

15 Aug '18

Philipp Deppenwiese has uploaded a new patch set (#2). ( https://review.coreboot.org/28104 ) Change subject: lib/fit_payload: Add coreboot tables support for FDT. ...................................................................... lib/fit_payload: Add coreboot tables support for FDT. * Copy code of depthcharge boot/coreboot.c and modify it. Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/lib/fit_payload.c 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28104/2 -- To view, visit https://review.coreboot.org/28104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Gerrit-Change-Number: 28104 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: lib/fit_payload: Add coreboot tables support for FDT.
by Philipp Deppenwiese (Code Review) 15 Aug '18

15 Aug '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/28104 Change subject: lib/fit_payload: Add coreboot tables support for FDT. ...................................................................... lib/fit_payload: Add coreboot tables support for FDT. * Copy code of depthcharge boot/coreboot.c and modify it. Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/lib/fit_payload.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28104/1 diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 9dbd878..430a597 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -29,6 +29,8 @@ #include <commonlib/compression.h> #include <lib.h> #include <fit_payload.h> +#include <boardid.h> +#include <arch/cbconfig.h> /* Pack the device_tree and place it at given position. */ static void pack_fdt(struct region *fdt, struct device_tree *dt) @@ -96,6 +98,60 @@ return false; } +static void coreboot_fdt_data(struct device_tree *tree) +{ + u32 addr_cells = 1, size_cells = 1; + static const char *firmware_path[] const = {"firmware", NULL}; + struct device_tree_node *firmware_node = dt_find_node(tree->root, + firmware_path, &addr_cells, &size_cells, 1); + + // Need to add 'ranges' to the intermediate node to make 'reg' work. + dt_add_bin_prop(firmware_node, "ranges", NULL, 0); + + static const char *coreboot_path[] const = {"coreboot", NULL}; + struct device_tree_node *coreboot_node = dt_find_node(firmware_node, + coreboot_path, &addr_cells, &size_cells, 1); + + dt_add_string_prop(coreboot_node, "compatible", (char *)"coreboot"); + + // Fetch CB tables from cbmem + void *cbtable = cbmem_find(CBMEM_ID_CBTABLE); + if (!cbtable) { + printk(BIOS_WARNING, "FIT: No coreboot table found!\n"); + return; + } + + u64 reg_addrs[2]; + u64 reg_sizes[2]; + + // First 'reg' address range is the coreboot table. + struct lb_header *header = cbtable; + reg_addrs[0] = (uintptr_t)header; + reg_sizes[0] = header->header_bytes + header->table_bytes; + + // Second is the CBMEM area (which usually includes the coreboot table). + reg_addrs[1] = (uintptr_t)cbmem_top(); + reg_sizes[1] = cbmem_overhead_size(); + + dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2, + addr_cells, size_cells); + + // Expose board ID, SKU ID, and RAM code exported from coreboot to + // userspace. + if (board_id() != UNDEFINED_STRAPPING_ID) { + dt_add_u32_prop(coreboot_node, + "board-id", board_id()); + } + if (sku_id() != UNDEFINED_STRAPPING_ID) { + dt_add_u32_prop(coreboot_node, + "sku-id", sku_id()); + } + if (ram_code() != UNDEFINED_STRAPPING_ID) { + dt_add_u32_prop(coreboot_node, + "ram-code", ram_code()); + } +} + /* * Parse the uImage FIT, choose a configuration and extract images. */ @@ -129,6 +185,8 @@ return; } + // Insert coreboot specific information + coreboot_fdt_data(dt); dt_apply_fixups(dt); /* Update device_tree */ -- To view, visit https://review.coreboot.org/28104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Gerrit-Change-Number: 28104 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: libpayload/x86/exception: Add ability to handle user defined interrupts
by Julius Werner (Code Review) 15 Aug '18

15 Aug '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/28100 ) Change subject: libpayload/x86/exception: Add ability to handle user defined interrupts ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… File payloads/libpayload/arch/x86/exception.c: https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… PS1, Line 165: /* Handle user defined vectors */ Not opposed to adding this capability in general, but I don't think it would be a good fit for the APIC timer stuff if we want to add it architecturally. In that case, I'd just hardcode an interrupt number for that and check it here directly. There can be only one exception hook, and that's currently used by GDB, so if you'd implement the APIC stuff through there you'd be breaking that. (The alternative would be to expand the hook system to a linked list.) https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… PS1, Line 167: die_if(!hook || !hook(vec), I don't think this does what you want, since even if hook(vec) returns true, you'll keep running through the code below and hit the vec >= EXC_COUNT. I think you meant to return here? -- To view, visit https://review.coreboot.org/28100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Gerrit-Change-Number: 28100 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 15 Aug 2018 22:26:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: tint: introduce the new tint build system with checksum verification
by build bot (Jenkins) (Code Review) 15 Aug '18

15 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 5: (12 comments) https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… File payloads/external/tint/generate_core.sh: https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 38: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 40: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 54: FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 64: import_from_file $buildgcc $corescript "# Find all the required tools" "# Allow" last_line_disabled || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 70: import_from_file $buildgcc $corescript "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 86: sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 95: # Insert prepare_${package} function call between the unpack and patch operations line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/generate_cor… PS5, Line 99: sed -i -e "/\$TAR \$FLAGS \$(basename \$archive)/a prepare_\${package} || exit \"\$?\"" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/tintify_core… File payloads/external/tint/tintify_core.sh: https://review.coreboot.org/#/c/23856/5/payloads/external/tint/tintify_core… PS5, Line 42: echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ]; then" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/tintify_core… PS5, Line 43: echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/tintify_core… PS5, Line 61: echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters https://review.coreboot.org/#/c/23856/5/payloads/external/tint/tintify_core… PS5, Line 65: echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters -- To view, visit https://review.coreboot.org/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 5 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Aug 2018 22:21:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload/x86/exception: Add ability to handle user defined interrupts
by Martin Roth (Code Review) 15 Aug '18

15 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28100 ) Change subject: libpayload/x86/exception: Add ability to handle user defined interrupts ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… File payloads/libpayload/arch/x86/exception_asm.S: https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… PS1, Line 73: stub \from : .if \to-\from You might want to just review tabs/spaces in the changes -- To view, visit https://review.coreboot.org/28100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Gerrit-Change-Number: 28100 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 15 Aug 2018 20:55:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/common: add function to init cppc_config
by Matt Delco (Code Review) 15 Aug '18

15 Aug '18

Matt Delco has posted comments on this change. ( https://review.coreboot.org/28068 ) Change subject: cpu/intel/common: add function to init cppc_config ...................................................................... Patch Set 4: > Why don't you put it into src/cpu/intel ? It looks like version 2 could be used on all Intel CPUs in tree. So I made an attempt to move it under there and revised the change. The best place I could spot was under common, and while I don't like sticking it in the only source file called common_init.c I also wasn't ready to break it out into a separate file yet either. The cpu/ and soc/ subdirs appear to be operating and evolving separately (e.g., they each have different implementations to enable vmx). I'm open to feedback on different ways to do this, though I'm also curious to see what the buildbot thinks of this attempt. -- To view, visit https://review.coreboot.org/28068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Gerrit-Change-Number: 28068 Gerrit-PatchSet: 4 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 15 Aug 2018 19:20:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: enable eist
by Matt Delco (Code Review) 15 Aug '18

15 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28103 Change subject: mb/google/poppy/variants/nocturne: enable eist ...................................................................... mb/google/poppy/variants/nocturne: enable eist Enable Enhanced Intel SpeedStep (EIST) on nocturne. Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/28103/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 88af929..4ee720f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -7,6 +7,8 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "eist_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE -- To view, visit https://review.coreboot.org/28103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa Gerrit-Change-Number: 28103 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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coreboot-gerrit August 2018