coreboot-gerrit August 2018

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Change in coreboot[master]: google/grunt: Update TP/TS/H1 i2c timings
by Martin Roth (Code Review) 16 Aug '18

16 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28119 ) Change subject: google/grunt: Update TP/TS/H1 i2c timings ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Gerrit-Change-Number: 28119 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 16 Aug 2018 15:01:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt: Update TP/TS/H1 i2c timings
by Kevin Chiu (Code Review) 16 Aug '18

16 Aug '18

Kevin Chiu has uploaded a new patch set (#2). ( https://review.coreboot.org/28119 ) Change subject: google/grunt: Update TP/TS/H1 i2c timings ...................................................................... google/grunt: Update TP/TS/H1 i2c timings After adjustment on Careena EVT TP: 400.0 KHz TS: 396.8 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/28119/2 -- To view, visit https://review.coreboot.org/28119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Gerrit-Change-Number: 28119 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: google/grunt: Update TP/TS/H1 i2c timings
by Kevin Chiu (Code Review) 16 Aug '18

16 Aug '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/28119 Change subject: google/grunt: Update TP/TS/H1 i2c timings ...................................................................... google/grunt: Update TP/TS/H1 i2c timings After adjustment on Careena EVT TP: 396.8 KHz TS: 398.4 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/28119/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 61476a2..513bd4e 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -32,22 +32,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, + .rise_time_ns = 45, .fall_time_ns = 4, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 117, - .fall_time_ns = 113, + .rise_time_ns = 67, + .fall_time_ns = 55, }" # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, + .rise_time_ns = 22, + .fall_time_ns = 19, }" device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/28119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Gerrit-Change-Number: 28119 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: libpayload/x86/exception: Add ability to handle user defined interrupts
by Raul Rangel (Code Review) 16 Aug '18

16 Aug '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28100 ) Change subject: libpayload/x86/exception: Add ability to handle user defined interrupts ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… File payloads/libpayload/arch/x86/exception.c: https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… PS1, Line 165: /* Handle user defined vectors */ > Not opposed to adding this capability in general, but I don't think it would be a good fit for the A […] Ah, I haven't tested with a gdb build yet, so I haven't seen it break. In the spirit of separation of concerns, I would like to avoid hard coding the interrupt number here. Instead of having a linked list for exception_install_hook. What if we kept a lookup table of handlers and added anew method set_interrupt_handler(void (*handler)(u32 vector)). This way we don't need to iterate over all the hooks checking the return status and we don't get into cases where we have two hooks that handle the same interrupt. https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… PS1, Line 167: die_if(!hook || !hook(vec), > I don't think this does what you want, since even if hook(vec) returns true, you'll keep running thr […] lol, thanks. I had it there originally, but when I went to make the commit, I forgot why I had it and removed it. https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… File payloads/libpayload/arch/x86/exception_asm.S: https://review.coreboot.org/#/c/28100/1/payloads/libpayload/arch/x86/except… PS1, Line 73: stub \from : .if \to-\from > You might want to just review tabs/spaces in the changes good catch -- To view, visit https://review.coreboot.org/28100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Gerrit-Change-Number: 28100 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 16 Aug 2018 14:38:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload/x86/exception: Add ability to handle user defined interrupts
by Raul Rangel (Code Review) 16 Aug '18

16 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28100 to look at the new patch set (#2). Change subject: libpayload/x86/exception: Add ability to handle user defined interrupts ...................................................................... libpayload/x86/exception: Add ability to handle user defined interrupts I need to setup the APIC timer to fire interrupts. I would like to reuse the existing interrupt table. So I extended it to support user defined interrupts. I just added all 255 vectors so there wouldn't need to be any additional build time configuration. BUG=b:109749762 TEST=Wrote an interrupt handler and fired an APIC timer interrupt and verified that vector 32 was returned. Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/arch/x86/exception.c M payloads/libpayload/arch/x86/exception_asm.S 2 files changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28100/2 -- To view, visit https://review.coreboot.org/28100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Gerrit-Change-Number: 28100 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: security/tpm: Fix TPM 1.2 state machine issues
by Randall Spangler (Code Review) 16 Aug '18

16 Aug '18

Randall Spangler has posted comments on this change. ( https://review.coreboot.org/28085 ) Change subject: security/tpm: Fix TPM 1.2 state machine issues ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28085/3/src/drivers/tpm/tpm.c File src/drivers/tpm/tpm.c: https://review.coreboot.org/#/c/28085/3/src/drivers/tpm/tpm.c@35 PS3, Line 35: if (result == TPM_E_MUST_REBOOT) : do_global_reset(); If the TPM is in a bad state, you could get stuck rebooting here forever. This may break Chrome OS recovery mode, which explicitly ignores TPM errors. -- To view, visit https://review.coreboot.org/28085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b Gerrit-Change-Number: 28085 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 16 Aug 2018 14:29:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: configs: Add various common non-default mainboards
by Patrick Rudolph (Code Review) 16 Aug '18

16 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28118 Change subject: configs: Add various common non-default mainboards ...................................................................... configs: Add various common non-default mainboards Build tests: * Option table * Static option table * Verbose debugging code * Sandy Bridge optional Kconfigs * TPM debugging code * Lenovo Bluetooth on Wifi * Libgfxinit on Sandy Bridge Change-Id: Ib463f578c97a212d0729aa6f54b7b6fba33e0478 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A configs/config.lenovo_t400_all_debug_and_option_table A configs/config.lenovo_t420_static_option_table_no_mem_fuses A configs/config.lenovo_thinkpad_t430_all_debug_and_option_table A configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi A configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs 5 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/28118/1 diff --git a/configs/config.lenovo_t400_all_debug_and_option_table b/configs/config.lenovo_t400_all_debug_and_option_table new file mode 100644 index 0000000..0ceee16 --- /dev/null +++ b/configs/config.lenovo_t400_all_debug_and_option_table @@ -0,0 +1,14 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_VENDOR_LENOVO=y +CONFIG_BOARD_LENOVO_T400=y +CONFIG_NO_POST=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_RAM_SETUP=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_SMM_RELOCATION=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_ACPI=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.lenovo_t420_static_option_table_no_mem_fuses b/configs/config.lenovo_t420_static_option_table_no_mem_fuses new file mode 100644 index 0000000..a268d88 --- /dev/null +++ b/configs/config.lenovo_t420_static_option_table_no_mem_fuses @@ -0,0 +1,7 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_VENDOR_LENOVO=y +CONFIG_BOARD_LENOVO_T420=y +CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y +CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y +# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set diff --git a/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table b/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table new file mode 100644 index 0000000..2c38734 --- /dev/null +++ b/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table @@ -0,0 +1,15 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_VENDOR_LENOVO=y +# CONFIG_POST_IO is not set +# CONFIG_POST_DEVICE is not set +CONFIG_BOARD_LENOVO_THINKPAD_T430=y +CONFIG_BOOTBLOCK_NORMAL=y +CONFIG_MAINBOARD_USE_LIBGFXINIT=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_DEBUG_RAM_SETUP=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_SMM_RELOCATION=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi new file mode 100644 index 0000000..697c26d --- /dev/null +++ b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi @@ -0,0 +1,14 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_VENDOR_LENOVO=y +CONFIG_BOARD_LENOVO_X201=y +CONFIG_H8_SUPPORT_BT_ON_WIFI=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_SMM_RELOCATION=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_ACPI=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y diff --git a/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs b/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs new file mode 100644 index 0000000..752e37f --- /dev/null +++ b/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs @@ -0,0 +1,5 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_VENDOR_LENOVO=y +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X220=y +CONFIG_DEBUG_TPM=y -- To view, visit https://review.coreboot.org/28118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib463f578c97a212d0729aa6f54b7b6fba33e0478 Gerrit-Change-Number: 28118 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: lib/fit_payload: Add coreboot tables support for FDT.
by Philipp Deppenwiese (Code Review) 16 Aug '18

16 Aug '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28104 to look at the new patch set (#8). Change subject: lib/fit_payload: Add coreboot tables support for FDT. ...................................................................... lib/fit_payload: Add coreboot tables support for FDT. * Copy code of depthcharge boot/coreboot.c and modify it. * Add const to last parameter of dt_add_string_prop function. Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/include/device_tree.h M src/lib/device_tree.c M src/lib/fit_payload.c 3 files changed, 76 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28104/8 -- To view, visit https://review.coreboot.org/28104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Gerrit-Change-Number: 28104 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: sandybridge/raminit_common.c: fix printram statement
by Arthur Heymans (Code Review) 16 Aug '18

16 Aug '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/28117 ) Change subject: sandybridge/raminit_common.c: fix printram statement ...................................................................... Patch Set 1: Code-Review+2 (1 comment) This fix is fine ofcourse, but the proper fix would be to replace all references to printram with printk(RAM_DEBUG, ...) or printk(RAM_SPEW, ...) in which case the code still gets compile tested. https://review.coreboot.org/#/c/28117/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/#/c/28117/1/src/northbridge/intel/sandybridge/r… PS1, Line 210: printram( You avoid these problems with printk(RAM_DEBUG/RAM_SPEW, ...) instead of using preprocessor dependent printram. -- To view, visit https://review.coreboot.org/28117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Gerrit-Change-Number: 28117 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 Aug 2018 08:56:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: sandybridge/raminit_common.c: fix printram statement
by Iru Cai (Code Review) 16 Aug '18

16 Aug '18

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/28117 Change subject: sandybridge/raminit_common.c: fix printram statement ...................................................................... sandybridge/raminit_common.c: fix printram statement Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/28117/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d806066..6944542 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -207,12 +207,15 @@ stretch = 3; MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff, (stretch << 12) | (stretch << 10)); - printram("OTHP Workaround [%x] = %x\n", addr, reg); + printram("OTHP Workaround [%x] = %x\n", + 0x401c + 0x400 * channel, + MCHBAR32(0x401c + 0x400 * channel)); } else { // OTHP MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff, (stretch << 16) | (stretch << 18)); - printram("OTHP [%x] = %x\n", addr, reg); + printram("OTHP [%x] = %x\n", 0x400c + 0x400 * channel + , MCHBAR32(0x400c + 0x400 * channel)); } } -- To view, visit https://review.coreboot.org/28117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Gerrit-Change-Number: 28117 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com>

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coreboot-gerrit August 2018