coreboot-gerrit August 2018

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Change in coreboot[master]: soc/amd/common/block/pi/agesawarapper.c: Use find_image()
by Richard Spiegel (Code Review) 16 Aug '18

16 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28164 Change subject: soc/amd/common/block/pi/agesawarapper.c: Use find_image() ...................................................................... soc/amd/common/block/pi/agesawarapper.c: Use find_image() In preparation to removing AmdLib, replace function LibAmdLocateImage() with its ported version find_image(). BUG=b:112625809 TEST=Build and boot grunt. Change-Id: I75ddd55f7e3e7f2cd7914f97c99b62690ae70660 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28164/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index c464b29..9a0f60d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -604,7 +604,7 @@ if (!agesa) return NULL; - image = LibAmdLocateImage(agesa, agesa + file_size, 4096, name); + image = find_image(agesa, agesa + file_size, 4096, name); if (!image) return NULL; -- To view, visit https://review.coreboot.org/28164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I75ddd55f7e3e7f2cd7914f97c99b62690ae70660 Gerrit-Change-Number: 28164 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: src/{commonlib, lib}: Fix typo
by Patrick Georgi (Code Review) 16 Aug '18

16 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28097 ) Change subject: src/{commonlib,lib}: Fix typo ...................................................................... src/{commonlib,lib}: Fix typo Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28097 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/commonlib/storage/mmc.c M src/lib/selfboot.c 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index e09d826..b62c8be 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -197,7 +197,7 @@ return ret; } -static int mmc_send_tunning_seq(struct sd_mmc_ctrlr *ctrlr, char *buffer) +static int mmc_send_tuning_seq(struct sd_mmc_ctrlr *ctrlr, char *buffer) { struct mmc_command cmd; struct mmc_data data; @@ -225,7 +225,7 @@ /* Request the device send the tuning sequence up to 40 times */ ctrlr->tuning_start(ctrlr, 0); for (index = 0; index < 40; index++) { - mmc_send_tunning_seq(ctrlr, buffer); + mmc_send_tuning_seq(ctrlr, buffer); if (ctrlr->is_tuning_complete(ctrlr, &successful)) { if (successful) return 0; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index a79f61d..fbd1cc4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -511,7 +511,7 @@ } /* - * Each architecture can perform additonal operations + * Each architecture can perform additional operations * on the loaded segment */ prog_segment_loaded((uintptr_t)dest, ptr->s_memsz, -- To view, visit https://review.coreboot.org/28097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Gerrit-Change-Number: 28097 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/common/block: Port vendorcode's LibAmdLocateImage
by Richard Spiegel (Code Review) 16 Aug '18

16 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28144 Change subject: soc/amd/common/block: Port vendorcode's LibAmdLocateImage ...................................................................... soc/amd/common/block: Port vendorcode's LibAmdLocateImage In preparation to removing AmdLib, function LibAmdLocateImage() has to be ported to be used by agesawrapper. The most important aspect of this porting is that it has to obey coreboot format, specifically 8 character tab and 80 characters max. This required breaking the function in 2 (to solve indentation) and rename some variables to shorter names. One important aspect was breaking (AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset) into: image_ptr = (AMD_IMAGE_HEADER *) current_ptr; if (validate_image((void *)image_ptr->ModuleInfoOffset, and, within validate_image completed by: AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain; BUG=b:112625809 TEST=Build grunt, functionality tested in next commit. Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A src/soc/amd/common/block/image/Kconfig A src/soc/amd/common/block/image/Makefile.inc A src/soc/amd/common/block/image/image.c A src/soc/amd/common/block/include/amdblocks/image.h M src/soc/amd/stoneyridge/Kconfig 5 files changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28144/1 diff --git a/src/soc/amd/common/block/image/Kconfig b/src/soc/amd/common/block/image/Kconfig new file mode 100644 index 0000000..9f0f9ea --- /dev/null +++ b/src/soc/amd/common/block/image/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_IMAGE + bool + default n + help + This option builds in the image find functions. diff --git a/src/soc/amd/common/block/image/Makefile.inc b/src/soc/amd/common/block/image/Makefile.inc new file mode 100644 index 0000000..91701e5 --- /dev/null +++ b/src/soc/amd/common/block/image/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_IMAGE),y) + +romstage-y += image.c + +ramstage-y += image.c + +endif diff --git a/src/soc/amd/common/block/image/image.c b/src/soc/amd/common/block/image/image.c new file mode 100644 index 0000000..288afce --- /dev/null +++ b/src/soc/amd/common/block/image/image.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Silverback, ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <agesa_headers.h> +#include <amdblocks/image.h> + +/* Check if the image has the desired module. */ +static bool validate_image(void *module_chain, const char module_signature[8]) +{ + AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain; + uint64_t signature = *(uint64_t *)module_signature; + char *checking_str; + + while ((mod_ptr != NULL) && + (MODULE_SIGNATURE == *(uint32_t *)&mod_ptr->ModuleHeaderSignature)) { + checking_str = (char *)&mod_ptr->ModuleIdentifier; + if (signature == *(uint64_t *)checking_str) + return true; + mod_ptr = (AMD_MODULE_HEADER *)mod_ptr->NextBlock; + } + return false; +} + +/* + * Find an image that has the desired module. The image is aligned within + * a given range. + */ +void *find_image(const void *start_address, const void *end_address, + uint32_t alignment, const char name[8]) +{ + uint8_t *current_ptr = (uint8_t *)start_address; + uint8_t *start = (uint8_t *)start_address; + uint8_t *end = (uint8_t *)end_address; + AMD_IMAGE_HEADER *image_ptr; + + while ((current_ptr >= start) && (current_ptr < end)) { + if (IMAGE_SIGNATURE == *((uint32_t *)current_ptr)) { + image_ptr = (AMD_IMAGE_HEADER *) current_ptr; + + /* Check if the image has the desired module */ + if (validate_image((void *)image_ptr->ModuleInfoOffset, + name)) + return current_ptr; + } + current_ptr += alignment; + } + return NULL; +} diff --git a/src/soc/amd/common/block/include/amdblocks/image.h b/src/soc/amd/common/block/include/amdblocks/image.h new file mode 100644 index 0000000..3e03e10 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/image.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Silverback, ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_IMAGE_H__ +#define __AMD_IMAGE_H__ + +#include <stdint.h> + +void *find_image(const void *start_address, const void *end_address, + uint32_t alignment, const char name[8]); + +#endif /* __AMD_IMAGE_H__ */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 2716c8c..38cb268 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PI + select SOC_AMD_COMMON_BLOCK_IMAGE select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 if HAVE_ACPI_RESUME -- To view, visit https://review.coreboot.org/28144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc Gerrit-Change-Number: 28144 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: x86/acpigen: Fix ACPI _ROM method
by Patrick Rudolph (Code Review) 16 Aug '18

16 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28124 ) Change subject: x86/acpigen: Fix ACPI _ROM method ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Gerrit-Change-Number: 28124 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 Aug 2018 18:03:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Fix PCI ACPI _OSC methods
by Martin Roth (Code Review) 16 Aug '18

16 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28121 ) Change subject: Fix PCI ACPI _OSC methods ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Gerrit-Change-Number: 28121 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 Aug 2018 18:01:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/kahlee: Fix ACPI method Not Serialized error
by Martin Roth (Code Review) 16 Aug '18

16 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28122 ) Change subject: mainboard/google/kahlee: Fix ACPI method Not Serialized error ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Gerrit-Change-Number: 28122 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 16 Aug 2018 17:53:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: x86/acpigen: Fix ACPI _ROM method
by Marc Jones (Code Review) 16 Aug '18

16 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28124 Change subject: x86/acpigen: Fix ACPI _ROM method ...................................................................... x86/acpigen: Fix ACPI _ROM method Fix the following Error: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 142 Line | AML source -------------------------------------------------------------------------------- 00139| 00140| Scope (\_SB.PCI0.IGFX) 00141| { 00142| Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00143| { 00144| OperationRegion (ROMS, SystemMemory, 0xCD520000, 0xFE00) 00145| Field (ROMS, AnyAcc, NoLock, Preserve) ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. Use the acpigen_write_method_serialized() to correct the error. BUG=b:112476331 TEST=Run FWTS. Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/arch/x86/acpigen.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28124/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index a614efb..c842cca 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1405,7 +1405,7 @@ ASSERT(length) /* Method (_ROM, 2, NotSerialized) */ - acpigen_write_method("_ROM", 2); + acpigen_write_method_serialized("_ROM", 2); /* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */ struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY, -- To view, visit https://review.coreboot.org/28124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Gerrit-Change-Number: 28124 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: ec/google/chromeec: Fix ACPI FWTS error
by Marc Jones (Code Review) 16 Aug '18

16 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28123 Change subject: ec/google/chromeec: Fix ACPI FWTS error ...................................................................... ec/google/chromeec: Fix ACPI FWTS error Fix the following FWTS error: FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line 3038 Line | AML source -------------------------------------------------------------------------------- 03035| Return (One) 03036| } 03037| 03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query | ^ | Warning 3115: Not all control paths return a value (_Q09) 03039| { 03040| If (Acquire (PATM, 0x03E8)) 03041| { ================================================================================ ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths do not return a value. All control paths that return must return a value otherwise unexpected behaviour may occur. This error occurs because a branch on an conditional op-code returns a value and another does not, which is inconsistent behaviour. _Q09 is a reserved method and can't return a value. Change the logic so that no return is used and avoid this test error. BUG=b:112476331 TEST=Run FWTS. Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 12 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/28123/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 94917dd..453a6d7 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -467,25 +467,23 @@ */ Method (_Q09, 0, NotSerialized) { - If (Acquire (^PATM, 1000)) { - Return () - } + If (LNot(Acquire (^PATM, 1000))) { + /* Read sensor ID for event */ + Store (^PATI, Local0) - /* Read sensor ID for event */ - Store (^PATI, Local0) - - /* When sensor ID returns 0xFF then no more events */ - While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) - { + /* When sensor ID returns 0xFF then no more events */ + While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) + { #ifdef HAVE_THERM_EVENT_HANDLER - \_SB.DPTF.TEVT (Local0) + \_SB.DPTF.TEVT (Local0) #endif - /* Keep reaading sensor ID for event */ - Store (^PATI, Local0) - } + /* Keep reaading sensor ID for event */ + Store (^PATI, Local0) + } - Release (^PATM) + Release (^PATM) + } } /* -- To view, visit https://review.coreboot.org/28123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Gerrit-Change-Number: 28123 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: mainboard/google/kahlee: Fix ACPI method Not Serialized error
by Marc Jones (Code Review) 16 Aug '18

16 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28122 Change subject: mainboard/google/kahlee: Fix ACPI method Not Serialized error ...................................................................... mainboard/google/kahlee: Fix ACPI method Not Serialized error Fix the following failure from FWTS: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 131 Line | AML source -------------------------------------------------------------------------------- 00128| } 00129| } 00130| }) 00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00132| { 00133| Name (RBUF, ResourceTemplate () 00134| { ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. BUG=b:112476331 TEST= Run FWTS. Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/28122/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 28599a0..6bb41ae 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -31,7 +31,7 @@ } }) - Method (_CRS, 0x0, NotSerialized) { + Method (_CRS, 0x0, Serialized) { Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. -- To view, visit https://review.coreboot.org/28122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Gerrit-Change-Number: 28122 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: Fix PCI ACPI _OSC methods
by Marc Jones (Code Review) 16 Aug '18

16 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28121 Change subject: Fix PCI ACPI _OSC methods ...................................................................... Fix PCI ACPI _OSC methods Fix the IASL build warnings: Object is not referenced (Name [CDW2] is within a method [_OSC]) Object is not referenced (Name [CDW3] is within a method [_OSC]) Remove the not referenced objects. They are not needed. BUG=b:112476331 TEST=IASL doesn't give the warning. Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/northbridge/intel/i945/acpi/i945.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/fch.asl 5 files changed, 5 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/28121/1 diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 5a93238..79fb371 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -20,17 +20,13 @@ /* Operating System Capabilities Method */ Method (_OSC, 4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 0, CDW1) - CreateDWordField(Arg3, 4, CDW2) - CreateDWordField(Arg3, 8, CDW3) - /* Check for proper PCI/PCIe UUID */ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return(Arg3) } Else { + CreateDWordField(Arg3, 0, CDW1) Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 2855b23..cdda503 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -22,17 +22,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index efd6a93..2bbaa25 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -20,17 +20,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 6f0826f..2dc3438 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -19,17 +19,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 2586dd4..b33a440 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -20,17 +20,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } -- To view, visit https://review.coreboot.org/28121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Gerrit-Change-Number: 28121 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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coreboot-gerrit August 2018