coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

1 participants
1120 discussions

Change in coreboot[master]: nb/intel/sandybridge: Fill in DIMM serial number
by Patrick Rudolph (Code Review) 17 Aug '18

17 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28191 Change subject: nb/intel/sandybridge: Fill in DIMM serial number ...................................................................... nb/intel/sandybridge: Fill in DIMM serial number Fill in SMBIOS type 17 DIMM serial number, read from SPD. Fixes FWTS SMBIOS type 17 test. Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h M src/northbridge/intel/sandybridge/raminit.c 3 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/28191/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index a084ca0..2fe9a62 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -398,6 +398,9 @@ memcpy(dimm->part_number, &spd[128], 16); printram(" Part number : %s\n", dimm->part_number); + memcpy(&dimm->serial, &spd[122], 4); + printram(" Serial number : 0x%x\n", dimm->serial); + return ret; } diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 9a24661..951d9c5 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -174,6 +174,8 @@ u16 manufacturer_id; /* ASCII part number - NULL terminated */ u8 part_number[17]; + /* Serial number */ + u32 serial; } dimm_attr; enum ddr3_xmp_profile { diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 47474ee..c397fa5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -114,6 +114,8 @@ dimm->mod_id = info->dimm[channel][slot].manufacturer_id; dimm->mod_type = info->dimm[channel][slot].dimm_type; dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only + memcpy(&dimm->serial, &info->dimm[channel][slot].serial, + DIMM_INFO_SERIAL_SIZE); mem_info->dimm_cnt++; } } -- To view, visit https://review.coreboot.org/28191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d Gerrit-Change-Number: 28191 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: cbtable: remove chromeos_acpi from cbtable
by Joel Kitching (Code Review) 17 Aug '18

17 Aug '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28190 Change subject: cbtable: remove chromeos_acpi from cbtable ...................................................................... cbtable: remove chromeos_acpi from cbtable Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M src/soc/amd/stoneyridge/include/soc/nvs.h M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/baytrail/include/soc/device_nvs.h M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/include/soc/device_nvs.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/include/soc/device_nvs.h M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/cannonlake/include/soc/nvs.h M src/soc/intel/fsp_baytrail/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/device_nvs.h M src/soc/intel/skylake/include/soc/nvs.h M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/fsp_bd82x6x/nvs.h M src/southbridge/intel/fsp_i89xx/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/nvs.h M src/vendorcode/google/chromeos/gnvs.h 23 files changed, 24 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/28190/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 4cf57c5..1568526 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -200,7 +200,6 @@ struct cb_gpio gpios[0]; }; -#define CB_TAG_CHROMEOS_ACPI 0x0015 #define CB_TAG_VBNV 0x0019 #define CB_TAG_VBOOT_HANDOFF 0x0020 #define CB_TAG_DMA 0x0022 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 66933e3..bd64cdb 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -97,8 +97,6 @@ void *vboot_handoff; u32 vboot_handoff_size; - void *chromeos_acpi_addr; - u32 chromeos_acpi_size; #if IS_ENABLED(CONFIG_LP_ARCH_X86) int x86_rom_var_mtrr_index; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index b879987..2189161 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -106,14 +106,6 @@ info->gpios[i] = gpios->gpios[i]; } -static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info) -{ - struct lb_range *chromeos_acpi = (struct lb_range *) ptr; - - info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start); - info->chromeos_acpi_size = chromeos_acpi->range_size; -} - static void cb_parse_mac_addresses(unsigned char *ptr, struct sysinfo_t *info) { @@ -357,9 +349,6 @@ case CB_TAG_GPIO: cb_parse_gpios(ptr, info); break; - case CB_TAG_CHROMEOS_ACPI: - cb_parse_chromeos_acpi(ptr, info); - break; case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 34726ab..6ca0f77 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -290,7 +290,6 @@ struct lb_gpio gpios[0]; }; -#define LB_TAG_CHROMEOS_ACPI 0x0015 #define LB_TAG_VBNV 0x0019 #define LB_TAB_VBOOT_HANDOFF 0x0020 #define LB_TAB_DMA 0x0022 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6b0e1a0..62b3aaa 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -195,19 +195,6 @@ } } -static void lb_chromeos_acpi(struct lb_header *header) -{ -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - struct lb_range *chromeos_acpi; - - chromeos_acpi = (struct lb_range *)lb_new_record(header); - chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI; - chromeos_acpi->size = sizeof(*chromeos_acpi); - acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start, - &chromeos_acpi->range_size); -#endif -} - static void lb_vbnv(struct lb_header *header) { #if IS_ENABLED(CONFIG_PC80_SYSTEM) @@ -547,9 +534,6 @@ /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); - /* pass along the chromeos_acpi_t buffer address */ - lb_chromeos_acpi(head); - /* pass along VBNV offsets in CMOS */ lb_vbnv(head); diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index b4f7213..bcac3a9 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -55,6 +55,6 @@ /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index c7be979..3250aeb 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -53,6 +53,6 @@ /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index b4fe65e..bc6f7ec 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include <stdint.h> #include <compiler.h> -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 21cdb14..715929d 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -102,7 +102,7 @@ /* Baytrail LPSS (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 268655e..8ed534e 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -20,9 +20,6 @@ #include <stdint.h> #include <compiler.h> -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 89a434b..05831bb 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -106,7 +106,7 @@ /* LPSS (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #if ENV_SMM diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h index 15240d1..d17b3d4 100644 --- a/src/soc/intel/broadwell/include/soc/device_nvs.h +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include <stdint.h> #include <compiler.h> -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define SIO_NVS_DMA 0 #define SIO_NVS_I2C0 1 #define SIO_NVS_I2C1 2 diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 34673d5..2e51e1b 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -94,7 +94,7 @@ /* Device specific (0x1000) */ device_nvs_t dev; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); void acpi_create_gnvs(global_nvs_t *gnvs); #ifdef __SMM__ diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h index 6c64f3a..1e55625 100644 --- a/src/soc/intel/cannonlake/include/soc/nvs.h +++ b/src/soc/intel/cannonlake/include/soc/nvs.h @@ -46,7 +46,7 @@ /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h index 5bafea6..8eff8cd 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h @@ -19,9 +19,6 @@ #include <stdint.h> #include <compiler.h> -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h index 02c9e65..2b7d126 100644 --- a/src/soc/intel/skylake/include/soc/device_nvs.h +++ b/src/soc/intel/skylake/include/soc/device_nvs.h @@ -20,9 +20,6 @@ #include <stdint.h> #include <compiler.h> -/* Offset in Global NVS where this structure lives */ -#define DEVICE_NVS_OFFSET 0x1000 - #define SIO_NVS_I2C0 0 #define SIO_NVS_I2C1 1 #define SIO_NVS_I2C2 2 diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index bd3610e..53fdded 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -102,6 +102,6 @@ /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #endif diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 207f763..537139d 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -154,7 +154,7 @@ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index a0e063c..c8af5b9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -150,7 +150,7 @@ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h index a0e063c..c8af5b9 100644 --- a/src/southbridge/intel/fsp_i89xx/nvs.h +++ b/src/southbridge/intel/fsp_i89xx/nvs.h @@ -150,7 +150,7 @@ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 8703911..7b9fd24 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -152,7 +152,7 @@ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index e7d4a8b..fd0d8bc 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -128,7 +128,7 @@ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __packed global_nvs_t; -check_member(global_nvs_t, chromeos, 0x100); +check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); #ifdef __SMM__ /* Used in SMM to find the ACPI GNVS address */ diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index e865c0e..62fa08c 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -41,6 +41,18 @@ #define ACTIVE_ECFW_RO 0 #define ACTIVE_ECFW_RW 1 +/* + * chromeos_acpi_t portion of ACPI GNVS is assumed to live at + * 0x100 - 0x1000. When defining global_nvs_t, use check_member + * to ensure that it is properly aligned: + * + * check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + */ +#define GNVS_CHROMEOS_ACPI_OFFSET 0x100 + +/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */ +#define GNVS_DEVICE_NVS_OFFSET 0x1000 + typedef struct { /* ChromeOS specific */ u32 vbt0; // 00 boot reason -- To view, visit https://review.coreboot.org/28190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Gerrit-Change-Number: 28190 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

1 0

Change in coreboot[master]: acpi: remove CBMEM_ID_ACPI_GNVS_PTR entry
by Joel Kitching (Code Review) 17 Aug '18

17 Aug '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/28189 Change subject: acpi: remove CBMEM_ID_ACPI_GNVS_PTR entry ...................................................................... acpi: remove CBMEM_ID_ACPI_GNVS_PTR entry Since we can retrieve the address of ACPI GNVS directly from CBMEM_ID_ACPI_GNVS, there is no need to store and update a pointer separately. Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea --- M src/arch/x86/acpi.c M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/acpi.h M src/commonlib/include/commonlib/cbmem_id.h M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/skylake/acpi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 4 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/28189/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8d7579d..78eeaa7 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1252,13 +1252,6 @@ return wake_vec; } -void acpi_save_gnvs(u32 gnvs_address) -{ - u32 *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS_PTR, sizeof(*gnvs)); - if (gnvs) - *gnvs = gnvs_address; -} - __weak int acpi_get_gpe(int gpe) { return -1; /* implemented by SOC */ diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index f6ed108..28e8f89 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -226,13 +226,13 @@ void acpi_resume(void *wake_vec) { if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR); + u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS); /* Restore GNVS pointer in SMM if found */ - if (gnvs_address && *gnvs_address) { + if (gnvs_address) { printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", - *gnvs_address); - smm_setup_structures((void *)*gnvs_address, NULL, NULL); + (u32)gnvs_address); + smm_setup_structures((void *)gnvs_address, NULL, NULL); } } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 1811965..40fbd54 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -771,8 +771,6 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, void *data, u16 len); -void acpi_save_gnvs(u32 gnvs_address); - /* For ACPI S3 support. */ void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 287de1d..042ea6e 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -19,7 +19,6 @@ #define CBMEM_ID_ACPI 0x41435049 #define CBMEM_ID_ACPI_GNVS 0x474e5653 -#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E @@ -81,7 +80,6 @@ #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ - { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 466b545..7b4f07b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -293,7 +293,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - acpi_save_gnvs((uintptr_t)gnvs); /* Add it to DSDT */ acpigen_write_scope("\\"); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 8dd8986..83f4227 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -509,7 +509,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 91d4925..ebca9fa 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -542,7 +542,6 @@ gnvs->cid1 = wifi_regulatory_domain(); else gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index c13c92a..ff7ff81 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -607,7 +607,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 01a4928..17ee85c 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -237,7 +237,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - acpi_save_gnvs((uintptr_t) gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 640dc79..07278c5 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -319,7 +319,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 7ce1b35..748b6cf 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -594,7 +594,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 5bed118..06c4ede 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -668,7 +668,6 @@ if (gnvs) { acpi_create_gnvs(gnvs); acpi_mainboard_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index a8b8757..88cc73f 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -434,7 +434,6 @@ if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - acpi_save_gnvs((unsigned long)gnvs); #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 9d686de..8f695cd 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -779,7 +779,6 @@ gnvs->ndid = gfx->ndid; memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); - acpi_save_gnvs((unsigned long)gnvs); /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); -- To view, visit https://review.coreboot.org/28189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea Gerrit-Change-Number: 28189 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

1 0

Change in coreboot[master]: mb/google/poppy/variant/nami: Tune Fan speed
by TH Lin (Code Review) 17 Aug '18

17 Aug '18

TH Lin has posted comments on this change. ( https://review.coreboot.org/28188 ) Change subject: mb/google/poppy/variant/nami: Tune Fan speed ...................................................................... Patch Set 1: will test & verify later... -- To view, visit https://review.coreboot.org/28188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice42461d0db2ebf8d7dd25514765791ebe613b83 Gerrit-Change-Number: 28188 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 17 Aug 2018 10:33:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy/variant/nami: Tune Fan speed
by TH Lin (Code Review) 17 Aug '18

17 Aug '18

TH Lin has uploaded this change for review. ( https://review.coreboot.org/28188 Change subject: mb/google/poppy/variant/nami: Tune Fan speed ...................................................................... mb/google/poppy/variant/nami: Tune Fan speed Rescale DFPS table from 10% Level to 5% level BUG=b:112438998#3 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test image with dptf.dv Change-Id: Ice42461d0db2ebf8d7dd25514765791ebe613b83 Signed-off-by: T.H. Lin <t.h_lin(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl 1 file changed, 19 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/28188/1 diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index 2b3bd25..caf3689 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -71,15 +71,25 @@ * These are initial reference values. */ /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {100, 0xFFFFFFFF, 6700, 250, 2500}, + Package () {90, 0xFFFFFFFF, 6300, 225, 2250}, + Package () {85, 0xFFFFFFFF, 6000, 210, 2100}, + Package () {80, 0xFFFFFFFF, 5800, 200, 2000}, + Package () {75, 0xFFFFFFFF, 5400, 185, 1850}, + Package () {70, 0xFFFFFFFF, 5000, 175, 1750}, + Package () {65, 0xFFFFFFFF, 4700, 160, 1600}, + Package () {60, 0xFFFFFFFF, 4400, 150, 1500}, + Package () {55, 0xFFFFFFFF, 4100, 135, 1350}, + Package () {50, 0xFFFFFFFF, 3800, 125, 1250}, + Package () {45, 0xFFFFFFFF, 3500, 110, 1100}, + Package () {40, 0xFFFFFFFF, 3300, 100, 1000}, + Package () {35, 0xFFFFFFFF, 2900, 85, 800}, + Package () {30, 0xFFFFFFFF, 2500, 75, 750}, + Package () {25, 0xFFFFFFFF, 2000, 60, 600}, + Package () {20, 0xFFFFFFFF, 1500, 50, 500}, + Package () {15, 0xFFFFFFFF, 1000, 35, 350}, + Package () {10, 0xFFFFFFFF, 800, 25, 250}, + Package () {5, 0xFFFFFFFF, 500, 10, 150}, Package () {0, 0xFFFFFFFF, 0, 0, 50} }) -- To view, visit https://review.coreboot.org/28188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ice42461d0db2ebf8d7dd25514765791ebe613b83 Gerrit-Change-Number: 28188 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com>

1 0

Change in coreboot[master]: lib/fit_payload: Add coreboot tables support for FDT.
by Patrick Rudolph (Code Review) 17 Aug '18

17 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28104 ) Change subject: lib/fit_payload: Add coreboot tables support for FDT. ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/28104/8/src/lib/fit_payload.c File src/lib/fit_payload.c: https://review.coreboot.org/#/c/28104/8/src/lib/fit_payload.c@140 PS8, Line 140: cbmem_get_imd > I'm confused... how does this build? cbmem_get_imd() is a static inline in another .c file. […] It's not build tested. I'll add a config in a separate commit. -- To view, visit https://review.coreboot.org/28104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Gerrit-Change-Number: 28104 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 17 Aug 2018 10:13:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy/variant/nami: Tune Fan speed
by TH Lin (Code Review) 17 Aug '18

17 Aug '18

TH Lin has abandoned this change. ( https://review.coreboot.org/28186 ) Change subject: mb/google/poppy/variant/nami: Tune Fan speed ...................................................................... Abandoned get wrong code.. -- To view, visit https://review.coreboot.org/28186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I680ee589872e998ba69735cb03728e2d83f187cc Gerrit-Change-Number: 28186 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/google/poppy/variant/nami: Tune Fan speed
by TH Lin (Code Review) 17 Aug '18

17 Aug '18

TH Lin has posted comments on this change. ( https://review.coreboot.org/28186 ) Change subject: mb/google/poppy/variant/nami: Tune Fan speed ...................................................................... Patch Set 1: get wrong download... Abandon... -- To view, visit https://review.coreboot.org/28186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I680ee589872e998ba69735cb03728e2d83f187cc Gerrit-Change-Number: 28186 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Aug 2018 09:55:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/poppy/variant/nami: Tune Fan speed
by TH Lin (Code Review) 17 Aug '18

17 Aug '18

TH Lin has posted comments on this change. ( https://review.coreboot.org/28186 ) Change subject: mb/google/poppy/variant/nami: Tune Fan speed ...................................................................... Patch Set 1: Need to verify DFPS tablet level, test.... -- To view, visit https://review.coreboot.org/28186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I680ee589872e998ba69735cb03728e2d83f187cc Gerrit-Change-Number: 28186 Gerrit-PatchSet: 1 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 17 Aug 2018 09:40:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP]: mb/google/octopus/variants/baseboard: Update DPTF parameters
by Sumeet R Pawnikar (Code Review) 17 Aug '18

17 Aug '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/28187 Change subject: [WIP]: mb/google/octopus/variants/baseboard: Update DPTF parameters ...................................................................... [WIP]: mb/google/octopus/variants/baseboard: Update DPTF parameters Update TSR1 trip point from 48C to 50C. Also, change power limit2 minimum value from 8W to 10W. Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28187/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl index 0b26129..1fc412e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -28,7 +28,7 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Ambient" -#define DPTF_TSR1_PASSIVE 48 +#define DPTF_TSR1_PASSIVE 50 #define DPTF_TSR1_CRITICAL 90 #define DPTF_TSR2_SENSOR_ID 2 @@ -77,7 +77,7 @@ Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ + 10000, /* PowerLimitMinimum */ 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ -- To view, visit https://review.coreboot.org/28187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b Gerrit-Change-Number: 28187 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2018