coreboot-gerrit August 2018

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Change in coreboot[master]: Makefile.inc: Ensure update of build.h
by Nico Huber (Code Review) 17 Aug '18

17 Aug '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28197 Change subject: Makefile.inc: Ensure update of build.h ...................................................................... Makefile.inc: Ensure update of build.h There were so many pitfalls that I wrote my own version of this even- tually. This version is inspired by the procedure of Alex Thiessen[1]. Instead of generating a `build.h` on demand, we always generate a tem- porary version that, if it differs from the current one, is added as a dependency. As we use .SECONDEXPANSION on the prerequisites, special care is taken that we won't generate the file twice. As it would be too late to add the dependency if we'd run `genbuild_h.sh` inside a recipe, we have to run it through the `$(shell)` function. But that brings us to the next issue: The make variables used by `genbuild_h.sh` are not expor- ted to this shell like they would be in a recipe. So we export them manually. We could also make these variables explicit parameters of `genbuild_h.sh` instead. An alternative to always creating the temporary `build.h` would be to add a phony target as dependency instead, and finally calling `genbuild_h.sh` again in case we need an update. But, um, we create so many files anyway... [1] https://review.coreboot.org/25685 Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile.inc 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/28197/1 diff --git a/Makefile.inc b/Makefile.inc index 7ce2360..3840505 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -464,11 +464,24 @@ ####################################################################### # generate build support files -$(obj)/build.h: .xcompile + +build_h := $(obj)/build.h + +# We have to manually export variables that `genbuild_h.sh` uses +# when we call it through the `$(shell)` function. This is fragile +# but as variables newly added to `genbuild_h.sh` would just not +# work, we'd notice that instantly at least. +build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION + +# Report new `build.ht` as dependency if `build.h` differs. +build_h_check := \ + export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \ + util/genbuild_h/genbuild_h.sh >$(build_h)t 2>/dev/null; \ + cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t + +$(build_h): $$(shell $$(build_h_check)) @printf " GEN build.h\n" - rm -f $(obj)/build.h - util/genbuild_h/genbuild_h.sh > $(obj)/build.ht - mv $(obj)/build.ht $(obj)/build.h + mv $< $@ build-dirs: mkdir -p $(objcbfs) $(objgenerated) -- To view, visit https://review.coreboot.org/28197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0 Gerrit-Change-Number: 28197 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: ec/lenovo/pmh7: support 9bit address space
by Alexander Couzens (Code Review) 17 Aug '18

17 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28196 to look at the new patch set (#2). Change subject: ec/lenovo/pmh7: support 9bit address space ...................................................................... ec/lenovo/pmh7: support 9bit address space The pmh7 has at least a 9bit address space. The h8s allows to access the 9th address space by using io port 0x15ed as second address register. The pmh7 is connected via SPI to the h8s. The h8s is acting as proxy to access the address space. Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/ec/lenovo/pmh7/pmh7.c M src/ec/lenovo/pmh7/pmh7.h 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28196/2 -- To view, visit https://review.coreboot.org/28196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a Gerrit-Change-Number: 28196 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ec/lenovo/pmh7: use read/write function in clear_bit/set_bit
by Alexander Couzens (Code Review) 17 Aug '18

17 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28195 to look at the new patch set (#2). Change subject: ec/lenovo/pmh7: use read/write function in clear_bit/set_bit ...................................................................... ec/lenovo/pmh7: use read/write function in clear_bit/set_bit Make the code simpler and improve readability. Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/ec/lenovo/pmh7/pmh7.c 1 file changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/28195/2 -- To view, visit https://review.coreboot.org/28195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Gerrit-Change-Number: 28195 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: add support for hynix memory
by build bot (Jenkins) (Code Review) 17 Aug '18

17 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27781 ) Change subject: mb/lenovo/x1_carbon_gen1: add support for hynix memory ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27781/5/src/mainboard/lenovo/x1_carbon_gen1… File src/mainboard/lenovo/x1_carbon_gen1/romstage.c: https://review.coreboot.org/#/c/27781/5/src/mainboard/lenovo/x1_carbon_gen1… PS5, Line 118: die("Unsupported Memory. (detected 'reserved' memory configuration)."); line over 80 characters -- To view, visit https://review.coreboot.org/27781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f Gerrit-Change-Number: 27781 Gerrit-PatchSet: 5 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Aug 2018 16:59:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: add support for hynix memory
by build bot (Jenkins) (Code Review) 17 Aug '18

17 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27781 ) Change subject: mb/lenovo/x1_carbon_gen1: add support for hynix memory ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27781/4/src/mainboard/lenovo/x1_carbon_gen1… File src/mainboard/lenovo/x1_carbon_gen1/romstage.c: https://review.coreboot.org/#/c/27781/4/src/mainboard/lenovo/x1_carbon_gen1… PS4, Line 117: die("Unsupported Memory. (detected 'reserved' memory configuration)."); line over 80 characters -- To view, visit https://review.coreboot.org/27781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f Gerrit-Change-Number: 27781 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Aug 2018 16:58:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: ec/pmh7: support 9bit address space
by Alexander Couzens (Code Review) 17 Aug '18

17 Aug '18

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/28196 Change subject: ec/pmh7: support 9bit address space ...................................................................... ec/pmh7: support 9bit address space The pmh7 has at least a 9bit address space. The h8s allows to access the 9th address space by using io port 0x15ed as second address register. The pmh7 is connected via SPI to the h8s. The h8s is acting as proxy to access the address space. Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a --- M src/ec/lenovo/pmh7/pmh7.c M src/ec/lenovo/pmh7/pmh7.h 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/28196/1 diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index b160fd0..765aa78 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -82,13 +82,15 @@ char pmh7_register_read(int reg) { - outb(reg, EC_LENOVO_PMH7_ADDR); + outb(reg & 0xff, EC_LENOVO_PMH7_ADDR_0); + outb((reg & 0xff00) >> 8, EC_LENOVO_PMH7_ADDR_1); return inb(EC_LENOVO_PMH7_DATA); } void pmh7_register_write(int reg, int val) { - outb(reg, EC_LENOVO_PMH7_ADDR); + outb(reg & 0xff, EC_LENOVO_PMH7_ADDR_0); + outb((reg & 0xff00) >> 8, EC_LENOVO_PMH7_ADDR_1); outb(val, EC_LENOVO_PMH7_DATA); } diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index d486ceb..c5551a7 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -19,7 +19,8 @@ #define EC_LENOVO_PMH7_INDEX 0x77 #define EC_LENOVO_PMH7_BASE 0x15e0 -#define EC_LENOVO_PMH7_ADDR (EC_LENOVO_PMH7_BASE + 0x0c) +#define EC_LENOVO_PMH7_ADDR_0 (EC_LENOVO_PMH7_BASE + 0x0c) +#define EC_LENOVO_PMH7_ADDR_1 (EC_LENOVO_PMH7_BASE + 0x0d) #define EC_LENOVO_PMH7_DATA (EC_LENOVO_PMH7_BASE + 0x0e) #define EC_LENOVO_PMH7_REG_ID 0xc2 -- To view, visit https://review.coreboot.org/28196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a Gerrit-Change-Number: 28196 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>

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Change in coreboot[master]: ec/pmh7: use read/write function in clear_bit/set_bit
by Alexander Couzens (Code Review) 17 Aug '18

17 Aug '18

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/28195 Change subject: ec/pmh7: use read/write function in clear_bit/set_bit ...................................................................... ec/pmh7: use read/write function in clear_bit/set_bit Make the code simpler and improve readability. Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c --- M src/ec/lenovo/pmh7/pmh7.c 1 file changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/28195/1 diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index c975679..b160fd0 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -68,20 +68,16 @@ { char val; - outb(reg, EC_LENOVO_PMH7_ADDR); - val = inb(EC_LENOVO_PMH7_DATA); - outb(reg, EC_LENOVO_PMH7_ADDR); - outb(val | (1 << bit), EC_LENOVO_PMH7_DATA); + val = pmh7_register_read(reg); + pmh7_register_write(reg, val | (1 << bit)); } void pmh7_register_clear_bit(int reg, int bit) { char val; - outb(reg, EC_LENOVO_PMH7_ADDR); - val = inb(EC_LENOVO_PMH7_DATA); - outb(reg, EC_LENOVO_PMH7_ADDR); - outb(val &= ~(1 << bit), EC_LENOVO_PMH7_DATA); + val = pmh7_register_read(reg); + pmh7_register_write(reg, val & ~(1 << bit)); } char pmh7_register_read(int reg) -- To view, visit https://review.coreboot.org/28195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Gerrit-Change-Number: 28195 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>

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Change in coreboot[master]: vendorcode/amd/pi/00670F00/Lib: Remove unused functions
by Richard Spiegel (Code Review) 17 Aug '18

17 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28194 Change subject: vendorcode/amd/pi/00670F00/Lib: Remove unused functions ...................................................................... vendorcode/amd/pi/00670F00/Lib: Remove unused functions The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These functions are used bi PspBaseLib. Remove all functions that are not used, directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite(). BUG=b:112688270 TEST=Build grunt Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/vendorcode/amd/pi/00670F00/Lib/amdlib.c M src/vendorcode/amd/pi/00670F00/Lib/amdlib.h 2 files changed, 0 insertions(+), 256 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/28194/1 diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c index 7181d1d..b03beee 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c @@ -62,13 +62,6 @@ ); VOID -IdsOutPort ( - IN UINT32 Addr, - IN UINT32 Value, - IN UINT32 Flag - ); - -VOID CpuidRead ( IN UINT32 CpuidFcnAddress, OUT CPUID_DATA *Value @@ -582,89 +575,6 @@ return MmioIsEnabled; } -/*---------------------------------------------------------------------------------------*/ -/** - * Verify checksum of binary image (B1/B2/B3) - * - * - * @param[in] ImagePtr Pointer to image start - * @retval TRUE Checksum valid - * @retval FALSE Checksum invalid - */ -BOOLEAN -LibAmdVerifyImageChecksum ( - IN CONST VOID *ImagePtr - ) -{ - // Assume ImagePtr points to the binary start ($AMD) - // Checksum is on an even boundary in AMD_IMAGE_HEADER - - UINT16 Sum; - UINT32 i; - - Sum = 0; - - i = ((AMD_IMAGE_HEADER*) ImagePtr)->ImageSize; - - while (i > 1) { - Sum = Sum + *((UINT16 *)ImagePtr); - ImagePtr = (VOID *) ((UINT8 *)ImagePtr + 2); - i = i - 2; - } - if (i > 0) { - Sum = Sum + *((UINT8 *) ImagePtr); - } - - return (Sum == 0)?TRUE:FALSE; -} - -/*---------------------------------------------------------------------------------------*/ -/** - * Locate AMD binary image that contain specific module - * - * - * @param[in] StartAddress Pointer to start range - * @param[in] EndAddress Pointer to end range - * @param[in] Alignment Image address alignment - * @param[in] ModuleSignature Module signature. - * @retval NULL if image not found - * @retval pointer to image header - */ -CONST VOID * -LibAmdLocateImage ( - IN CONST VOID *StartAddress, - IN CONST VOID *EndAddress, - IN UINT32 Alignment, - IN CONST CHAR8 ModuleSignature[8] - ) - -{ - CONST UINT8 *CurrentPtr = StartAddress; - AMD_MODULE_HEADER *ModuleHeaderPtr; - CONST UINT64 SearchStr = *((UINT64*)ModuleSignature); - - // Search from start to end incrementing by alignment - while ((CurrentPtr >= (UINT8 *) StartAddress) && (CurrentPtr < (UINT8 *) EndAddress)) { - // First find a binary image - if (IMAGE_SIGNATURE == *((UINT32 *) CurrentPtr)) { - // TODO Figure out a way to fix the AGESA binary checksum -// if (LibAmdVerifyImageChecksum (CurrentPtr)) { - // If we have a valid image, search module linked list for a match - ModuleHeaderPtr = (AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset); - while ((ModuleHeaderPtr != NULL) && - (MODULE_SIGNATURE == *((UINT32*)&(ModuleHeaderPtr->ModuleHeaderSignature)))) { - if (SearchStr == *((UINT64*)&(ModuleHeaderPtr->ModuleIdentifier))) { - return CurrentPtr; - } - ModuleHeaderPtr = (AMD_MODULE_HEADER *)ModuleHeaderPtr->NextBlock; - } -// } - } - CurrentPtr += Alignment; - } - return NULL; -} - BOOLEAN IdsErrorStop ( IN UINT32 FileCode diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h index f41e0c4..fc97213 100644 --- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h +++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.h @@ -126,11 +126,6 @@ IN UINT32 Data ); -UINT64 -ReadTSC ( - void - ); - // MSR VOID LibAmdMsrRead ( @@ -163,16 +158,6 @@ IN OUT AMD_CONFIG_PARAMS *StdHeader ); -VOID -LibAmdIoPoll ( - IN ACCESS_WIDTH AccessWidth, - IN UINT16 IoAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN UINT64 Delay, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - // Memory or MMIO VOID LibAmdMemRead ( @@ -190,16 +175,6 @@ IN OUT AMD_CONFIG_PARAMS *StdHeader ); -VOID -LibAmdMemPoll ( - IN ACCESS_WIDTH AccessWidth, - IN UINT64 MemAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN UINT64 Delay, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - // PCI VOID LibAmdPciRead ( @@ -217,40 +192,6 @@ IN OUT AMD_CONFIG_PARAMS *StdHeader ); -VOID -LibAmdPciPoll ( - IN ACCESS_WIDTH AccessWidth, - IN PCI_ADDR PciAddress, - IN CONST VOID *Data, - IN CONST VOID *DataMask, - IN UINT64 Delay, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdPciReadBits ( - IN PCI_ADDR Address, - IN UINT8 Highbit, - IN UINT8 Lowbit, - OUT UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdPciWriteBits ( - IN PCI_ADDR Address, - IN UINT8 Highbit, - IN UINT8 Lowbit, - IN CONST UINT32 *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdPciFindNextCap ( - IN OUT PCI_ADDR *Address, - IN AMD_CONFIG_PARAMS *StdHeader - ); - // CPUID VOID LibAmdCpuidRead ( @@ -258,111 +199,4 @@ OUT CPUID_DATA *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ); - -// Utility Functions -VOID -LibAmdMemFill ( - IN VOID *Destination, - IN UINT8 Value, - IN UINTN FillLength, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -VOID -LibAmdMemCopy ( - IN VOID *Destination, - IN CONST VOID *Source, - IN UINTN CopyLength, - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -CONST VOID * -LibAmdLocateImage ( - IN CONST VOID *StartAddress, - IN CONST VOID *EndAddress, - IN UINT32 Alignment, - IN CONST CHAR8 ModuleSignature[8] - ); - -UINT32 -LibAmdGetPackageType ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -BOOLEAN -LibAmdVerifyImageChecksum ( - IN CONST VOID *ImagePtr - ); - -UINT8 -LibAmdBitScanReverse ( - IN UINT32 value - ); -UINT8 -LibAmdBitScanForward ( - IN UINT32 value - ); - -VOID -LibAmdReadCpuReg ( - IN UINT8 RegNum, - OUT UINT32 *Value - ); -VOID -LibAmdWriteCpuReg ( - IN UINT8 RegNum, - IN UINT32 Value - ); - -VOID -LibAmdWriteBackInvalidateCache ( - void - ); - -VOID -LibAmdSimNowEnterDebugger ( - void - ); - -VOID -LibAmdHDTBreakPoint ( - void - ); - -UINT8 -LibAmdAccessWidth ( - IN ACCESS_WIDTH AccessWidth - ); - -VOID -LibAmdCLFlush ( - IN UINT64 Address, - IN UINT8 Count - ); - -VOID -StopHere ( - void - ); - -VOID -LibAmdFinit ( - void - ); - -VOID -LibAmdFnclex ( - void - ); - -VOID -LibAmdReadMxcsr ( - OUT UINT32 *Value - ); - -VOID -LibAmdWriteMxcsr ( - IN UINT32 *Value - ); - #endif // _AMD_LIB_H_ -- To view, visit https://review.coreboot.org/28194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed Gerrit-Change-Number: 28194 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: ACPI: Get rid of FADT model field
by Patrick Rudolph (Code Review) 17 Aug '18

17 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28193 Change subject: ACPI: Get rid of FADT model field ...................................................................... ACPI: Get rid of FADT model field ACPI spec 2.0 recommends to set it to zero, while one is still allowed. Remove the mixed occurences and always set it to zero. Fixes FWTS FADT test. Change-Id: I74e83e3c8c0fa80d830565e5bc487d21fef35e6f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/beltino/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/google/slippy/fadt.c M src/mainboard/intel/baskingridge/fadt.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/intel/strago/fadt.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/roda/rk9/fadt.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 30 files changed, 3 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/28193/1 diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 418d547..262b790 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -45,7 +45,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ fadt->sci_int = 0x9; diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 83d25d7..09cfb65 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -57,7 +57,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = 0; diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index dea67d0..a9c307f 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -32,7 +32,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/beltino/fadt.c b/src/mainboard/google/beltino/fadt.c index 486a343..a065565 100644 --- a/src/mainboard/google/beltino/fadt.c +++ b/src/mainboard/google/beltino/fadt.c @@ -35,7 +35,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index d62c28d..62f1c31 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -32,7 +32,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index dea67d0..a9c307f 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -32,7 +32,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index b0fe9d6..a0e1381 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -31,7 +31,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c index fe86f56..7220b86 100644 --- a/src/mainboard/google/slippy/fadt.c +++ b/src/mainboard/google/slippy/fadt.c @@ -35,7 +35,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; diff --git a/src/mainboard/intel/baskingridge/fadt.c b/src/mainboard/intel/baskingridge/fadt.c index e32e9f2..63d8de1 100644 --- a/src/mainboard/intel/baskingridge/fadt.c +++ b/src/mainboard/intel/baskingridge/fadt.c @@ -35,7 +35,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_DESKTOP; fadt->sci_int = 0x9; diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index 9f41f64..1e1e71b 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -36,7 +36,6 @@ fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index af222b5..c62f6fd 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -32,7 +32,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index d474fc4..f9d0e08 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -31,7 +31,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index fe988d6..2989a40 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index fe988d6..2989a40 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index 9cbcd3f..6503b1d 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (u32)facs; fadt->dsdt = (u32)dsdt; - fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (u32)facs; diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index fe988d6..1684d27 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -35,7 +35,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 9f41f64..1e1e71b 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -36,7 +36,6 @@ fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; - fadt->model = 1; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 5f9e792..c0d9113 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -85,7 +85,6 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 7ce1b35..9631a78 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -201,7 +201,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 38b4d47..875050b 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -177,7 +177,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = 0; fadt->sci_int = acpi_sci_irq(); diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index c1d9b72..5aeb0f9 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -65,7 +65,6 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index ad47ad7..1313a53 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -69,7 +69,6 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 84c6a1d..133470e 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -57,7 +57,6 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index d9e72b4..5cd70ff 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -759,8 +759,6 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; - fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 431587d..a24f4db 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -617,8 +617,6 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; - fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index f584f36..b17af61 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -529,8 +529,6 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; - fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index 45f0558..c224d22 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -58,7 +58,6 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ac83ec9..842868a 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -577,7 +577,6 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index cd5e307..8d691a0 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -590,7 +590,6 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index b09951f..ca7858b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -652,8 +652,6 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; - fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; -- To view, visit https://review.coreboot.org/28193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I74e83e3c8c0fa80d830565e5bc487d21fef35e6f Gerrit-Change-Number: 28193 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Fix DIMM type mapping
by Patrick Rudolph (Code Review) 17 Aug '18

17 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28192 Change subject: nb/intel/sandybridge/raminit: Fix DIMM type mapping ...................................................................... nb/intel/sandybridge/raminit: Fix DIMM type mapping The DIMM type read from SPD needs to be converted to make sure SMBIOS fills in the correct formfactor. Tested on Lenovo T430: The Form Factor no longer reads as unknown. Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/28192/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c397fa5..6e408f1 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -112,7 +112,29 @@ memcpy(dimm->module_part_number, info->dimm[channel][slot].part_number, 16); dimm->mod_id = info->dimm[channel][slot].manufacturer_id; - dimm->mod_type = info->dimm[channel][slot].dimm_type; + + switch (info->dimm[channel][slot].dimm_type) { + case SPD_DIMM_TYPE_SO_DIMM: + dimm->mod_type = SPD_SODIMM; + break; + case SPD_DIMM_TYPE_72B_SO_CDIMM: + dimm->mod_type = SPD_72B_SO_CDIMM; + break; + case SPD_DIMM_TYPE_72B_SO_RDIMM: + dimm->mod_type = SPD_72B_SO_RDIMM; + break; + case SPD_DIMM_TYPE_UDIMM: + dimm->mod_type = SPD_UDIMM; + break; + case SPD_DIMM_TYPE_RDIMM: + dimm->mod_type = SPD_RDIMM; + break; + case SPD_DIMM_TYPE_UNDEFINED: + default: + dimm->mod_type = SPD_UNDEFINED; + break; + } + dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only memcpy(&dimm->serial, &info->dimm[channel][slot].serial, DIMM_INFO_SERIAL_SIZE); -- To view, visit https://review.coreboot.org/28192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030 Gerrit-Change-Number: 28192 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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coreboot-gerrit August 2018