coreboot-gerrit August 2018

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Change in coreboot[master]: util/lint: Exclude util/superiotool from checkpatch
by Nico Huber (Code Review) 19 Aug '18

19 Aug '18

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28214 to look at the new patch set (#2). Change subject: util/lint: Exclude util/superiotool from checkpatch ...................................................................... util/lint: Exclude util/superiotool from checkpatch `superiotool` follows its own style (e.g. lot's of missing spaces and odd placement of braces in the register descriptions). Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/lint/lint-007-checkpatch 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/28214/2 -- To view, visit https://review.coreboot.org/28214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233 Gerrit-Change-Number: 28214 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/raminit: Remove unused headers
by Felix Held (Code Review) 19 Aug '18

19 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28212 ) Change subject: nb/intel/raminit: Remove unused headers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071 Gerrit-Change-Number: 28212 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 19 Aug 2018 11:20:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/lint: Exclude util/superiotool from checkpatch
by Angel Pons (Code Review) 19 Aug '18

19 Aug '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28214 ) Change subject: util/lint: Exclude util/superiotool from checkpatch ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/28214/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28214/1//COMMIT_MSG@8 PS1, Line 8: I would give a reason for this change. Experience tells me the reason is related to Jenkins spamming every superiotool change with syntax warnings. -- To view, visit https://review.coreboot.org/28214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233 Gerrit-Change-Number: 28214 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 19 Aug 2018 11:00:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/lint: Exclude util/superiotool from checkpatch
by Nico Huber (Code Review) 19 Aug '18

19 Aug '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28214 Change subject: util/lint: Exclude util/superiotool from checkpatch ...................................................................... util/lint: Exclude util/superiotool from checkpatch Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/lint/lint-007-checkpatch 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/28214/1 diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch index 34b9331..abc63f1 100755 --- a/util/lint/lint-007-checkpatch +++ b/util/lint/lint-007-checkpatch @@ -23,6 +23,7 @@ ^payloads/libpayload/curses/PDCurses\|\ ^util/crossgcc/patches\|\ ^util/kconfig\|\ +^util/superiotool\|\ ^src/vendorcode\|\ ^Documentation" -- To view, visit https://review.coreboot.org/28214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233 Gerrit-Change-Number: 28214 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c
by Patrick Rudolph (Code Review) 19 Aug '18

19 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28213 Change subject: nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c ...................................................................... nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c There's nothing Sandy Bridge specific in this code. Make it available on all platforms to reduce code duplication. Tested on Lenovo T430: SMBIOS entry 17 is still valid. Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h M src/northbridge/intel/sandybridge/raminit.c 3 files changed, 89 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/28213/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 7655b32..563ff8b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -24,6 +24,9 @@ #include <device/device.h> #include <device/dram/ddr3.h> #include <string.h> +#include <memory_info.h> +#include <cbmem.h> +#include <smbios.h> /*============================================================================== * = DDR3 SPD decoding helpers @@ -522,6 +525,83 @@ return ret; } + +/** + * Fill cbmem with information for SMBIOS type 17. + * + * @param channel Corresponding channel of provided @info + * @param slot Corresponding slot of provided @info + * @param selected_freq The actual frequency the DRAM is running on + * @param info DIMM parameters read from SPD + * + * @return CB_SUCCESS if DIMM info was written + */ +enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, + const u16 selected_freq, + const dimm_attr *info) +{ + struct memory_info *mem_info; + struct dimm_info *dimm; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_find(CBMEM_ID_MEMINFO); + if (!mem_info) { + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", + mem_info); + if (!mem_info) + return CB_ERR; + + memset(mem_info, 0, sizeof(*mem_info)); + } + + dimm = &mem_info->dimm[mem_info->dimm_cnt]; + if (info->size_mb) { + dimm->ddr_type = MEMORY_TYPE_DDR3; + dimm->ddr_frequency = selected_freq; + dimm->dimm_size = info->size_mb; + dimm->channel_num = channel; + dimm->rank_per_dimm = info->ranks; + dimm->dimm_num = slot; + memcpy(dimm->module_part_number, info->part_number, 16); + dimm->mod_id = info->manufacturer_id; + dimm->mod_type = info->dimm_type; + dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only + + switch (info->dimm_type) { + case SPD_DIMM_TYPE_SO_DIMM: + dimm->mod_type = SPD_SODIMM; + break; + case SPD_DIMM_TYPE_72B_SO_CDIMM: + dimm->mod_type = SPD_72B_SO_CDIMM; + break; + case SPD_DIMM_TYPE_72B_SO_RDIMM: + dimm->mod_type = SPD_72B_SO_RDIMM; + break; + case SPD_DIMM_TYPE_UDIMM: + dimm->mod_type = SPD_UDIMM; + break; + case SPD_DIMM_TYPE_RDIMM: + dimm->mod_type = SPD_RDIMM; + break; + case SPD_DIMM_TYPE_UNDEFINED: + default: + dimm->mod_type = SPD_UNDEFINED; + break; + } + + memcpy(dimm->serial, info->serial, + MIN(sizeof(dimm->serial), sizeof(info->serial))); + mem_info->dimm_cnt++; + } + + return CB_SUCCESS; +} + /* * The information printed below has a more informational character, and is not * necessarily tied in to RAM init debugging. Hence, we stop using printram(), diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 563be10..5643787 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -32,6 +32,7 @@ #include <stdint.h> #include <spd.h> #include <device/dram/common.h> +#include <types.h> /** @@ -193,7 +194,9 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm, spd_raw_data spd, enum ddr3_xmp_profile profile); - +enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, + const u16 selected_freq, + const dimm_attr *info); /** * \brief Read double word from specified address * diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4d02a64..0f72d88 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -16,7 +16,6 @@ */ #include <console/console.h> -#include <console/usb.h> #include <commonlib/region.h> #include <bootmode.h> #include <string.h> @@ -29,8 +28,6 @@ #include <southbridge/intel/common/smbus.h> #include <cpu/x86/msr.h> #include <delay.h> -#include <smbios.h> -#include <memory_info.h> #include <lib.h> #include "raminit_native.h" #include "raminit_common.h" @@ -81,67 +78,14 @@ */ static void fill_smbios17(ramctr_timing *ctrl) { - struct memory_info *mem_info; int channel, slot; - struct dimm_info *dimm; - uint16_t ddr_freq; - dimm_info *info = &ctrl->info; - - ddr_freq = (1000 << 8) / ctrl->tCK; - - /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ - mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); - printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); - if (!mem_info) - return; - - memset(mem_info, 0, sizeof(*mem_info)); + const u16 ddr_freq = (1000 << 8) / ctrl->tCK; FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { - dimm = &mem_info->dimm[mem_info->dimm_cnt]; - if (info->dimm[channel][slot].size_mb) { - dimm->ddr_type = MEMORY_TYPE_DDR3; - dimm->ddr_frequency = ddr_freq; - dimm->dimm_size = info->dimm[channel][slot].size_mb; - dimm->channel_num = channel; - dimm->rank_per_dimm = info->dimm[channel][slot].ranks; - dimm->dimm_num = slot; - memcpy(dimm->module_part_number, - info->dimm[channel][slot].part_number, 16); - dimm->mod_id = info->dimm[channel][slot].manufacturer_id; - - switch (info->dimm[channel][slot].dimm_type) { - case SPD_DIMM_TYPE_SO_DIMM: - dimm->mod_type = SPD_SODIMM; - break; - case SPD_DIMM_TYPE_72B_SO_CDIMM: - dimm->mod_type = SPD_72B_SO_CDIMM; - break; - case SPD_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = SPD_72B_SO_RDIMM; - break; - case SPD_DIMM_TYPE_UDIMM: - dimm->mod_type = SPD_UDIMM; - break; - case SPD_DIMM_TYPE_RDIMM: - dimm->mod_type = SPD_RDIMM; - break; - case SPD_DIMM_TYPE_UNDEFINED: - default: - dimm->mod_type = SPD_UNDEFINED; - break; - } - - dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only - - memcpy(dimm->serial, info->dimm[channel][slot].serial, - MIN(sizeof(dimm->serial), - sizeof(info->dimm[channel][slot].serial))); - mem_info->dimm_cnt++; - } + enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, + &ctrl->info.dimm[channel][slot]); + if (ret != CB_SUCCESS) + printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); } } -- To view, visit https://review.coreboot.org/28213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Gerrit-Change-Number: 28213 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/raminit: Remove unused headers
by Patrick Rudolph (Code Review) 19 Aug '18

19 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28212 Change subject: nb/intel/raminit: Remove unused headers ...................................................................... nb/intel/raminit: Remove unused headers Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/28212/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index a90b055..071f360 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -16,12 +16,8 @@ */ #include <console/console.h> -#include <console/usb.h> #include <string.h> #include <arch/io.h> -#include <cbmem.h> -#include <arch/cbfs.h> -#include <cbfs.h> #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> -- To view, visit https://review.coreboot.org/28212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071 Gerrit-Change-Number: 28212 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: Makefile.inc: Ensure update of build.h
by Patrick Rudolph (Code Review) 19 Aug '18

19 Aug '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28197 ) Change subject: Makefile.inc: Ensure update of build.h ...................................................................... Patch Set 1: Code-Review+2 Tested, works -- To view, visit https://review.coreboot.org/28197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0 Gerrit-Change-Number: 28197 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alex Thiessen <pandokos+coreboot(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 19 Aug 2018 08:22:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/lenovo/pmh7: support 9bit address space
by Felix Held (Code Review) 19 Aug '18

19 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28196 ) Change subject: ec/lenovo/pmh7: support 9bit address space ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/28196/2/src/ec/lenovo/pmh7/pmh7.h File src/ec/lenovo/pmh7/pmh7.h: https://review.coreboot.org/#/c/28196/2/src/ec/lenovo/pmh7/pmh7.h@23 PS2, Line 23: #define EC_LENOVO_PMH7_ADDR_1 (EC_LENOVO_PMH7_BASE + 0x0d) maybe use the suffixes _L and _H instead of _0 and _1; at least for me it would be clearer that those are the lower and higher byte of the address -- To view, visit https://review.coreboot.org/28196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a Gerrit-Change-Number: 28196 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 19 Aug 2018 01:37:59 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/lenovo/pmh7: use read/write function in clear_bit/set_bit
by Felix Held (Code Review) 19 Aug '18

19 Aug '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28195 ) Change subject: ec/lenovo/pmh7: use read/write function in clear_bit/set_bit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Gerrit-Change-Number: 28195 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 19 Aug 2018 01:35:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/docker/doc.coreboot.org/Dockerfile: Use alpine:3.8, Sphinx 1.7
by Tom Hiller (Code Review) 19 Aug '18

19 Aug '18

Tom Hiller has posted comments on this change. ( https://review.coreboot.org/28211 ) Change subject: util/docker/doc.coreboot.org/Dockerfile: Use alpine:3.8, Sphinx 1.7 ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/28211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53f246206458b1de34cd7f3a42481b91ca285ff0 Gerrit-Change-Number: 28211 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 19 Aug 2018 00:42:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit August 2018