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Change in coreboot[master]: Makefile.inc: Ensure update of build.h
by Patrick Georgi (Code Review) 20 Aug '18

20 Aug '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28197 ) Change subject: Makefile.inc: Ensure update of build.h ...................................................................... Makefile.inc: Ensure update of build.h There were so many pitfalls that I wrote my own version of this even- tually. This version is inspired by the procedure of Alex Thiessen[1]. Instead of generating a `build.h` on demand, we always generate a tem- porary version that, if it differs from the current one, is added as a dependency. As we use .SECONDEXPANSION on the prerequisites, special care is taken that we won't generate the file twice. As it would be too late to add the dependency if we'd run `genbuild_h.sh` inside a recipe, we have to run it through the `$(shell)` function. But that brings us to the next issue: The make variables used by `genbuild_h.sh` are not expor- ted to this shell like they would be in a recipe. So we export them manually. We could also make these variables explicit parameters of `genbuild_h.sh` instead. An alternative to always creating the temporary `build.h` would be to add a phony target as dependency instead, and finally calling `genbuild_h.sh` again in case we need an update. But, um, we create so many files anyway... [1] https://review.coreboot.org/25685 Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/28197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Makefile.inc 1 file changed, 17 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 7ce2360..3840505 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -464,11 +464,24 @@ ####################################################################### # generate build support files -$(obj)/build.h: .xcompile + +build_h := $(obj)/build.h + +# We have to manually export variables that `genbuild_h.sh` uses +# when we call it through the `$(shell)` function. This is fragile +# but as variables newly added to `genbuild_h.sh` would just not +# work, we'd notice that instantly at least. +build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION + +# Report new `build.ht` as dependency if `build.h` differs. +build_h_check := \ + export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \ + util/genbuild_h/genbuild_h.sh >$(build_h)t 2>/dev/null; \ + cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t + +$(build_h): $$(shell $$(build_h_check)) @printf " GEN build.h\n" - rm -f $(obj)/build.h - util/genbuild_h/genbuild_h.sh > $(obj)/build.ht - mv $(obj)/build.ht $(obj)/build.h + mv $< $@ build-dirs: mkdir -p $(objcbfs) $(objgenerated) -- To view, visit https://review.coreboot.org/28197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0 Gerrit-Change-Number: 28197 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alex Thiessen <pandokos+coreboot(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/ifdfake: Remove deprecated utility
by Angel Pons (Code Review) 20 Aug '18

20 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28234 Change subject: util/ifdfake: Remove deprecated utility ...................................................................... util/ifdfake: Remove deprecated utility Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove it from "util/", as well as any leftover references in other files. Change-Id: I45fe3d9fd606a61d5c3b9d0e6489a1df6d6510f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M .gitignore M Documentation/util.md M MAINTAINERS M util/README.md D util/ifdfake/Makefile D util/ifdfake/description.md D util/ifdfake/ifdfake.c 7 files changed, 0 insertions(+), 267 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28234/1 diff --git a/.gitignore b/.gitignore index 378741f..7523a5f 100644 --- a/.gitignore +++ b/.gitignore @@ -99,7 +99,6 @@ util/genprof/genprof util/getpir/getpir util/ifdtool/ifdtool -util/ifdfake/ifdfake util/intelmetool/intelmetool util/inteltool/.dependencies util/inteltool/inteltool diff --git a/Documentation/util.md b/Documentation/util.md index be7cc99..72355e3 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -46,8 +46,6 @@ * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdfake__ - Create an Intel Firmware Descriptor with just a section -layout `C` * __ifdtool__ - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine diff --git a/MAINTAINERS b/MAINTAINERS index 0875fdd..ca8a6f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -414,7 +414,6 @@ IFDTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/ifdtool/ -F: util/ifdfake/ BUILD SYSTEM M: Patrick Georgi <patrick(a)georgi-clan.de> diff --git a/util/README.md b/util/README.md index 96d5918..69ed11e 100644 --- a/util/README.md +++ b/util/README.md @@ -44,8 +44,6 @@ * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdfake__ - Create an Intel Firmware Descriptor with just a section -layout `C` * __ifdtool__ - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine diff --git a/util/ifdfake/Makefile b/util/ifdfake/Makefile deleted file mode 100644 index 4080ef9..0000000 --- a/util/ifdfake/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -# ifdfake - Create an Intel Firmware Descriptor with just a section layout -# -# Copyright (C) 2013 secunet Security Networks AG -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -PROGRAM = ifdfake - -CC ?= gcc -INSTALL ?= /usr/bin/install -PREFIX ?= /usr/local -CFLAGS ?= -O2 -g -Wall -W - -OBJS = ifdfake.o - -all: $(PROGRAM) - -$(PROGRAM): $(OBJS) - $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) - -clean: - rm -f $(PROGRAM) *.o *~ - -distclean: clean - -install: $(PROGRAM) - mkdir -p $(DESTDIR)$(PREFIX)/bin - $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin - -.PHONY: all clean distclean diff --git a/util/ifdfake/description.md b/util/ifdfake/description.md deleted file mode 100644 index 5835bec..0000000 --- a/util/ifdfake/description.md +++ /dev/null @@ -1 +0,0 @@ -Create an Intel Firmware Descriptor with just a section layout `C` diff --git a/util/ifdfake/ifdfake.c b/util/ifdfake/ifdfake.c deleted file mode 100644 index b549f3a..0000000 --- a/util/ifdfake/ifdfake.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * ifdfake - Create an Intel Firmware Descriptor with just a section layout - * - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <errno.h> -#include <stdio.h> -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <getopt.h> - -#define REGION_COUNT 5 - -#define FDBAR_OFFSET 0x10 -#define FRBA_OFFSET 0x40 - -typedef struct { - uint32_t base, limit, size; -} region_t; - -static void write_image(const region_t regions[], const char *const image) -{ - FILE *const f = fopen(image, "w"); - if (!f) { - perror("Could not open file"); - exit(EXIT_FAILURE); - } - - if (fseek(f, 0x1000 - 1, SEEK_SET)) { - perror("Failed to seek to end of descriptor"); - exit(EXIT_FAILURE); - } - char zero = '\0'; - if (fwrite(&zero, 1, 1, f) != 1) { - fprintf(stderr, "Failed to write at end of descriptor.\n"); - exit(EXIT_FAILURE); - } - - if (fseek(f, FDBAR_OFFSET, SEEK_SET)) { - perror("Failed to seek to fdbar"); - exit(EXIT_FAILURE); - } - - struct { - uint32_t flvalsig; - uint32_t flmap0; - } fdbar; - memset(&fdbar, 0x00, sizeof(fdbar)); - fdbar.flvalsig = 0x0ff0a55a; - fdbar.flmap0 = (REGION_COUNT - 1) << 24 | (FRBA_OFFSET >> 4) << 16; - if (fwrite(&fdbar, sizeof(fdbar), 1, f) != 1) { - fprintf(stderr, "Failed to write fdbar.\n"); - exit(EXIT_FAILURE); - } - - int i; - uint32_t frba[REGION_COUNT]; - for (i = 0; i < REGION_COUNT; ++i) { - if (regions[i].size) - frba[i] = ((regions[i].limit & 0xfff000) << (16 - 12)) | - ((regions[i].base & 0xfff000) >> 12); - else - frba[i] = 0x00000fff; - } - - if (fseek(f, FRBA_OFFSET, SEEK_SET)) { - perror("Failed to seek to frba"); - exit(EXIT_FAILURE); - } - if (fwrite(frba, sizeof(frba), 1, f) != 1) { - fprintf(stderr, "Failed to write frba.\n"); - exit(EXIT_FAILURE); - } - - fclose(f); -} - -static int parse_region(const char *_arg, region_t *const region) -{ - char *const start = strdup(_arg); - int size_spec = 0; - unsigned long first, second; - if (!start) { - fprintf(stderr, "Out of memory.\n"); - exit(EXIT_FAILURE); - } - - char *colon = strchr(start, ':'); - if (!colon) { - colon = strchr(start, '+'); - if (!colon) { - free(start); - return -1; - } - size_spec = 1; - } - *colon = '\0'; - - char *const end = colon + 1; - - errno = 0; - first = strtoul(start, NULL, 0); - second = strtoul(end, NULL, 0); - - if (size_spec) { - region->base = first; - region->size = second; - region->limit = region->base + region->size - 1; - } else { - region->base = first; - region->limit = second; - region->size = region->limit - region->base + 1; - } - - free(start); - if (errno) { - perror("Failed to parse region"); - return -1; - } else { - return 0; - } -} - -static void print_usage(const char *name) -{ - printf("usage: %s [(-b|-m|-g|-p) <start>:<end>]... <output file>\n", name); - printf("\n" - " -b | --bios <start>:<end> BIOS region\n" - " -m | --me <start>:<end> Intel ME region\n" - " -g | --gbe <start>:<end> Gigabit Ethernet region\n" - " -p | --platform <start>:<end> Platform Data region\n" - " -h | --help print this help\n\n" - "<start> and <end> bounds are given in bytes, the <end> bound is inclusive.\n" - "All regions must be multiples of 4K in size and 4K aligned.\n" - "The descriptor region always resides in the first 4K.\n\n" - "An IFD created with ifdfake won't work as a replacement for a real IFD.\n" - "Never try to flash such an IFD to your board!\n\n"); -} - -int main(int argc, char *argv[]) -{ - int opt, option_index = 0, idx; - region_t regions[REGION_COUNT]; - - memset(regions, 0x00, sizeof(regions)); - - static struct option long_options[] = { - {"bios", 1, NULL, 'b'}, - {"me", 1, NULL, 'm'}, - {"gbe", 1, NULL, 'g'}, - {"platform", 1, NULL, 'p'}, - {"help", 0, NULL, 'h'}, - {0, 0, 0, 0} - }; - - while ((opt = getopt_long(argc, argv, "b:m:g:p:h?", - long_options, &option_index)) != EOF) { - switch (opt) { - case 'b': case 'm': case 'g': case 'p': - switch (opt) { - case 'b': idx = 1; break; - case 'm': idx = 2; break; - case 'g': idx = 3; break; - case 'p': idx = 4; break; - default: idx = 0; break; /* can't happen */ - } - if (parse_region(optarg, &regions[idx])) { - print_usage(argv[0]); - exit(EXIT_FAILURE); - } - break; - case 'h': - case '?': - default: - print_usage(argv[0]); - exit(EXIT_SUCCESS); - break; - } - } - - if (optind + 1 != argc) { - fprintf(stderr, "No output file given.\n\n"); - print_usage(argv[0]); - exit(EXIT_FAILURE); - } - - regions[0].base = 0x00000000; - regions[0].limit = 0x00000fff; - regions[0].size = 0x00001000; - for (idx = 1; idx < REGION_COUNT; ++idx) { - if (regions[idx].size) { - if (regions[idx].base & 0xfff) - fprintf(stderr, "Region %d is " - "not 4K aligned.\n", idx); - else if (regions[idx].size & 0xfff) - fprintf(stderr, "Region %d size is " - "no multiple of 4K.\n", idx); - else if (regions[idx].limit <= regions[idx].base) - fprintf(stderr, "Region %d is empty.\n", idx); - else - continue; - print_usage(argv[0]); - exit(EXIT_FAILURE); - } - } - - write_image(regions, argv[optind]); - - return 0; -} -- To view, visit https://review.coreboot.org/28234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I45fe3d9fd606a61d5c3b9d0e6489a1df6d6510f0 Gerrit-Change-Number: 28234 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: Kconfig, Makefile.inc: Remove all traces of ifdfake
by Angel Pons (Code Review) 20 Aug '18

20 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28233 Change subject: Kconfig, Makefile.inc: Remove all traces of ifdfake ...................................................................... Kconfig, Makefile.inc: Remove all traces of ifdfake Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove it from the build system. Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Makefile.inc M src/southbridge/intel/common/firmware/Kconfig M src/southbridge/intel/common/firmware/Makefile.inc 3 files changed, 4 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28233/1 diff --git a/Makefile.inc b/Makefile.inc index 7ce2360..46e833e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -457,7 +457,7 @@ endif additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ - $(objutil)/ifdfake $(objutil)/options $(objutil)/amdfwtool \ + $(objutil)/options $(objutil)/amdfwtool \ $(objutil)/cbootimage $(objutil)/bimgtool export $(COREBOOT_EXPORTS) @@ -519,11 +519,6 @@ +$(MAKE) -C $(top)/util/ifdtool cp -a $(top)/util/ifdtool/ifdtool $@ -IFDFAKE:=$(objutil)/ifdfake/ifdfake -$(IFDFAKE): $(top)/util/ifdfake/ifdfake.c - @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -o $@ $< - AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" @@ -603,7 +598,7 @@ include util/crossgcc/Makefile.inc .PHONY: tools -tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG) +tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG) ########################################################################### # Common recipes for all stages diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index c9cf6f8..590d120 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -33,7 +33,7 @@ config IFD_BIN_PATH string "Path and filename of the descriptor.bin file" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" - depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD + depends on HAVE_IFD_BIN config HAVE_ME_BIN bool "Add Intel ME/TXE firmware" @@ -132,67 +132,6 @@ depends on HAVE_EC_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/ec.bin" -##### Fake IFD ##### - -config BUILD_WITH_FAKE_IFD - bool "Build with a fake IFD" if !HAVE_IFD_BIN - help - If you don't have an Intel Firmware Descriptor (descriptor.bin) for your - board, you can select this option and coreboot will build without it. - The resulting coreboot.rom will not contain all parts required - to get coreboot running on your board. You can however write only the - BIOS section to your board's flash ROM and keep the other sections - untouched. Unfortunately the current version of flashrom doesn't - support this yet. But there is a patch pending [1]. - - WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. - - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html - -config IFD_BIOS_SECTION - depends on BUILD_WITH_FAKE_IFD - string "BIOS Region Starting:Ending addresses within the ROM" - default "" - help - The BIOS region is typically the size of the CBFS area, and is located - at the end of the ROM space. - - For an 8MB ROM with a 3MB CBFS area, this would look like: - 0x00500000:0x007fffff - -config IFD_ME_SECTION - depends on BUILD_WITH_FAKE_IFD - string "ME/TXE Region Starting:Ending addresses within the ROM" - default "" - help - The ME/TXE region typically starts at around 0x1000 and often fills the - ROM space not used by CBFS. - - For an 8MB ROM with a 3MB CBFS area, this might look like: - 0x00001000:0x004fffff - -config IFD_GBE_SECTION - depends on BUILD_WITH_FAKE_IFD - string "GBE Region Starting:Ending addresses within the ROM" - default "" - help - The Gigabit Ethernet ROM region is used when an Intel NIC is built into - the Southbridge/SOC and the platform uses this device instead of an external - PCIe NIC. It will be located between the ME/TXE and the BIOS region. - - Leave this empty if you're unsure. - -config IFD_PLATFORM_SECTION - depends on BUILD_WITH_FAKE_IFD - string "Platform Region Starting:Ending addresses within the Rom" - default "" - help - The Platform region is used for platform specific data. - It will be located between the ME/TXE and the BIOS region. - - Leave this empty if you're unsure. - config LOCK_MANAGEMENT_ENGINE bool "Lock ME/TXE section" default n diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 737a79d..a1c09c9 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -24,29 +24,12 @@ INTERMEDIATE+=add_intel_firmware endif -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) -INTERMEDIATE+=add_intel_firmware -IFD_BIN_PATH := $(objgenerated)/ifdfake.bin -IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ - $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ - $(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \ - $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) -else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) ifneq ($(call strip_quotes,$(CONFIG_IFD_CHIPSET)),) IFDTOOL_USE_CHIPSET := -p $(CONFIG_IFD_CHIPSET) endif -endif -add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) -ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf "\n** WARNING **\n" - printf "coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" - printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" - printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" - $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) -endif +add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 @@ -88,11 +71,6 @@ $(objutil)/ifdtool/ifdtool \ $(IFDTOOL_USE_CHIPSET) -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool \ - $(IFDTOOL_USE_CHIPSET) -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_EM100),y) -- To view, visit https://review.coreboot.org/28233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2 Gerrit-Change-Number: 28233 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: src/mainboard/*: Remove IFD_*_REGION values for ifdfake
by Angel Pons (Code Review) 20 Aug '18

20 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28232 Change subject: src/mainboard/*: Remove IFD_*_REGION values for ifdfake ...................................................................... src/mainboard/*: Remove IFD_*_REGION values for ifdfake Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove the IFD_*_REGION values on the few motherboards with them. Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3v/Kconfig M src/mainboard/intel/dcp847ske/Kconfig M src/mainboard/kontron/ktqm77/Kconfig M src/mainboard/roda/rv11/Kconfig 5 files changed, 0 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28232/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 7ec9fe9..7aefcfb 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -47,12 +47,4 @@ string default "pci8086,0162.rom" -config IFD_BIOS_SECTION - string - default "0x00600000:0x007fffff" - -config IFD_ME_SECTION - string - default "0x00001000:0x004fffff" - endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index 12b1844..a2a89b9 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -46,12 +46,4 @@ string default "pci8086,0102.rom" -config IFD_BIOS_SECTION - string - default "0x00600000:0x007fffff" - -config IFD_ME_SECTION - string - default "0x00001000:0x004fffff" - endif # BOARD_GIGABYTE_GA_B75M_D3V diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index ae93e9d..508cedf 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -57,18 +57,6 @@ int default 2 -config IFD_GBE_SECTION - string - default "0x00001000:0x00002fff" - -config IFD_ME_SECTION - string - default "0x00003000:0x001bffff" - -config IFD_BIOS_SECTION - string - default "0x001c0000:0x007fffff" - config CBFS_SIZE hex default 0x00640000 diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 10da8d1..a8aca1c 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -44,16 +44,4 @@ string default "Kontron" -config IFD_BIOS_SECTION - string - default "0x00580000:0x007fffff" - -config IFD_ME_SECTION - string - default "0x00003000:0x0057ffff" - -config IFD_GBE_SECTION - string - default "0x00001000:0x00002fff" - endif # BOARD_KONTRON_KTQM77 diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig index 4485aee..9e81841 100644 --- a/src/mainboard/roda/rv11/Kconfig +++ b/src/mainboard/roda/rv11/Kconfig @@ -43,16 +43,4 @@ string default "Roda" -config IFD_BIOS_SECTION - string - default "0x00d80000:0x00ffffff" - -config IFD_ME_SECTION - string - default "0x00003000:0x00d7ffff" - -config IFD_GBE_SECTION - string - default "0x00001000:0x00002fff" - endif # BOARD_RODA_RV11 || BOARD_RODA_RW11 -- To view, visit https://review.coreboot.org/28232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9 Gerrit-Change-Number: 28232 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: configs: Build test verbose BDK and FIT payload support
by Philipp Deppenwiese (Code Review) 20 Aug '18

20 Aug '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28228 ) Change subject: configs: Build test verbose BDK and FIT payload support ...................................................................... configs: Build test verbose BDK and FIT payload support Change-Id: I2075142a0b241222839899e707a1e3d264746432 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28228 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- A configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved diff --git a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support new file mode 100644 index 0000000..951855e --- /dev/null +++ b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support @@ -0,0 +1,9 @@ +CONFIG_VENDOR_CAVIUM=y +CONFIG_CAVIUM_BDK_VERBOSE_INIT=y +CONFIG_CAVIUM_BDK_VERBOSE_DRAM=y +CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST=y +CONFIG_CAVIUM_BDK_VERBOSE_QLM=y +CONFIG_CAVIUM_BDK_VERBOSE_PCIE_CONFIG=y +CONFIG_CAVIUM_BDK_VERBOSE_PCIE=y +CONFIG_CAVIUM_BDK_VERBOSE_PHY=y +CONFIG_PAYLOAD_FIT_SUPPORT=y -- To view, visit https://review.coreboot.org/28228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I2075142a0b241222839899e707a1e3d264746432 Gerrit-Change-Number: 28228 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: configs: Build test verbose BDK and FIT payload support
by Philipp Deppenwiese (Code Review) 20 Aug '18

20 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28228 ) Change subject: configs: Build test verbose BDK and FIT payload support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2075142a0b241222839899e707a1e3d264746432 Gerrit-Change-Number: 28228 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 20 Aug 2018 14:34:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation/northbridge/intel/sandybridge/*: fix typos
by Angel Pons (Code Review) 20 Aug '18

20 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28231 Change subject: Documentation/northbridge/intel/sandybridge/*: fix typos ...................................................................... Documentation/northbridge/intel/sandybridge/*: fix typos Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy Bridge". Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/northbridge/intel/sandybridge/nri_read.md M Documentation/northbridge/intel/sandybridge/nri_registers.md 4 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28231/1 diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 1b07ba4..812cd23 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -3,7 +3,7 @@ ## Introduction This documentation is intended to document the closed source memory controller -hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs. +hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs. The memory initialization code has to take care of lots of duties: 1. Selection of operating frequency @@ -41,13 +41,13 @@ ``` ## (Inoffical) register documentation -- [Sandy Bride - Register documentation](nri_registers.md) +- [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection -- [Sandy Bride - Frequency selection](nri_freq.md) +- [Sandy Bridge - Frequency selection](nri_freq.md) ## Read training -- [Sandy Bride - Read training](nri_read.md) +- [Sandy Bridge - Read training](nri_read.md) ### SMBIOS type 17 The SMBIOS specification allows to report the memory configuration in use. @@ -113,7 +113,7 @@ > **Note:** This feature is available since coreboot 4.5 Try to swap memory modules and or try to use a different vendor. If nothing -helps you could have a look at capter [Debuggin] or report a ticket +helps you could have a look at chapter [Debugging] or report a ticket at [ticket.coreboot.org]. Please provide a full RAM init log, that has been captured using EHCI debug. diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index d8b73b3..208c1cb 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -1,7 +1,8 @@ # Frequency selection ## Introduction -This chapter explains the frequency selection done on Sandybride and Ivybridge. +This chapter explains the frequency selection done on Sandy Bridge and Ivy +Bridge memory initialization. ## Definitions ```eval_rst @@ -58,7 +59,7 @@ > **Note:** Ignoring the fuses might cause system instability ! -On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being +On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being read. coreboot reads those registers and honors the limit in case the Kconfig option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set. Power users that want to let their RAM run at DRAM's "stock" frequency need to @@ -84,7 +85,7 @@ By using this register it's possible to force a minimum operating frequency. ## Reference clock -While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also +While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also supports 100 MHz reference clock. The reference clock is multiplied by the DRAM multiplier to select the DRAM frequency (SCK) by the following formula: @@ -92,7 +93,7 @@ > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK. -## Sandy Bride's supported frequencies +## Sandy Bridge's supported frequencies ```eval_rst +------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | @@ -111,7 +112,7 @@ +------------+-----------+------------------+-------------------------+---------------+ ``` -## Ivybridge's supported frequencies +## Ivy Bridge's supported frequencies ```eval_rst +------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | @@ -144,7 +145,7 @@ > '1: since coreboot 4.6 ## Multiplier selection -coreboot select the maximum frequency to operate at by the following formula: +coreboot selects the maximum frequency to operate at by the following formula: ``` if devicetree's max_mem_clock_mhz > 0: freq_max := max_mem_clock_mhz diff --git a/Documentation/northbridge/intel/sandybridge/nri_read.md b/Documentation/northbridge/intel/sandybridge/nri_read.md index 0496657..f5c79ac 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_read.md +++ b/Documentation/northbridge/intel/sandybridge/nri_read.md @@ -2,7 +2,7 @@ ## Introduction -This chapter explains the read training sequence done on Sandy Bride and +This chapter explains the read training sequence done on Sandy Bridge and Ivy Bridge memory initialization. Read training is done to compensate the skew between DQS and SCK and to find diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 601157c..6249560 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1556,7 +1556,7 @@ *Width:* 16 Bit -*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0 +*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0 ```eval_rst +-----------+------------------------------------------------------------------+ @@ -2138,7 +2138,7 @@ | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] | +-----------+------------------------------------------------------------------+ | 8 | - 1: 100Mhz reference clock | -| | - 0: 133Mhz reference clock (IvyBridge only) | +| | - 0: 133Mhz reference clock (Ivy Bridge only) | +-----------+------------------------------------------------------------------+ | 31 | PLL busy | +-----------+------------------------------------------------------------------+ -- To view, visit https://review.coreboot.org/28231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a Gerrit-Change-Number: 28231 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: lib/fit_payload: Add coreboot tables support for FDT.
by build bot (Jenkins) (Code Review) 20 Aug '18

20 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28104 ) Change subject: lib/fit_payload: Add coreboot tables support for FDT. ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/#/c/28104/9/src/lib/fit_payload.c File src/lib/fit_payload.c: https://review.coreboot.org/#/c/28104/9/src/lib/fit_payload.c@113 PS9, Line 113: static const char *firmware_path[] = {"firmware", NULL}; static const char * array should probably be static const char * const https://review.coreboot.org/#/c/28104/9/src/lib/fit_payload.c@120 PS9, Line 120: static const char *coreboot_path[] = {"coreboot", NULL}; static const char * array should probably be static const char * const -- To view, visit https://review.coreboot.org/28104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977 Gerrit-Change-Number: 28104 Gerrit-PatchSet: 9 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 20 Aug 2018 09:48:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/pineview: Use i2c block read to fetch SPD
by build bot (Jenkins) (Code Review) 20 Aug '18

20 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28229 ) Change subject: nb/intel/pineview: Use i2c block read to fetch SPD ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28229/1/src/northbridge/intel/pineview/rami… File src/northbridge/intel/pineview/raminit.c: https://review.coreboot.org/#/c/28229/1/src/northbridge/intel/pineview/rami… PS1, Line 277: if (i2c_block_read(s->spd_map[i], 0, 64, s->dimms[i].spd_data) != 64) line over 80 characters -- To view, visit https://review.coreboot.org/28229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic23f39f1017010c89795e626f6a6f918f8bda17a Gerrit-Change-Number: 28229 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 20 Aug 2018 09:32:59 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/pineview: Use the correct address for the RCVEN strobe
by Arthur Heymans (Code Review) 20 Aug '18

20 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28230 Change subject: nb/intel/pineview: Use the correct address for the RCVEN strobe ...................................................................... nb/intel/pineview: Use the correct address for the RCVEN strobe When doing the receive enable training, the final mapping of the ranks is already done, so we can be sure that that address 0x00000000 there will always be a rank. Change-Id: I7ac017a8816fc9a47cef0695826a1c32f699f6f8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/28230/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index f1e0767..a050e06 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1875,7 +1875,9 @@ u8 minbytelanecoarse = 0xff; u8 bytelaneoffset; u8 maxbytelane = 8; - u32 strobeaddr = (rank_is_populated(s->dimms, 0, 0)) ? 0 : 2*128*1024*1024; + /* Since dra/drb is already set up we know that at address 0x00000000 + we will always find the first available rank */ + u32 strobeaddr = 0; u32 dqshighaddr; MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; -- To view, visit https://review.coreboot.org/28230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7ac017a8816fc9a47cef0695826a1c32f699f6f8 Gerrit-Change-Number: 28230 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit August 2018