coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

1 participants
1120 discussions

Change in coreboot[master]: soc/intel/apollolake: Fix logical vs. bitwise operator
by John Zhao (Code Review) 21 Aug '18

21 Aug '18

John Zhao has uploaded this change for review. ( https://review.coreboot.org/28261 Change subject: soc/intel/apollolake: Fix logical vs. bitwise operator ...................................................................... soc/intel/apollolake: Fix logical vs. bitwise operator src/soc/intel/apollolake/chip.c Apply bitwise operator instead of logical one. Found-by: Coverity Scan BRANCH=None TEST=Built & booted Yorp board. Change-Id: I36746b04dec889f53c8d7eeb3b1d8118eff1de42 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/28261/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 83a6baa..9b8cfd7 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -678,7 +678,7 @@ cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); reg = read32(cfg0); - if (!(reg && SW_IDPIN_EN_MASK)) + if (!(reg & SW_IDPIN_EN_MASK)) return; reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK); -- To view, visit https://review.coreboot.org/28261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I36746b04dec889f53c8d7eeb3b1d8118eff1de42 Gerrit-Change-Number: 28261 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com>

1 0

Change in coreboot[master]: google/chromeec: Add support for "base attached switch" device
by Dmitry Torokhov (Code Review) 21 Aug '18

21 Aug '18

Dmitry Torokhov has uploaded this change for review. ( https://review.coreboot.org/28260 Change subject: google/chromeec: Add support for "base attached switch" device ...................................................................... google/chromeec: Add support for "base attached switch" device On some detachables, the mere presence of attached base is not enough to determine whether the device is in tablet mode or not, so we introducing a new "switch" in EC, separate from "Tablet Mode" switch, to signal whether the base is attached or not. We also want the driver to be separate from cros_ec_keyb, so we create a new ACPI device, C(hrome)B(ase)A(ttached)S(witch), with HID GOOG0010, and guard it with EC_ENABLE_CBAS_DEVICE. Also enable this option on Nocturne. Change-Id: Id73a12f04a1a48f7fbd9365c2a501afadf3878fa Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> --- M src/ec/google/chromeec/acpi/cros_ec.asl M src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/28260/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index b246fe3..4699397 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -30,4 +30,13 @@ Name (_DDN, "EC MKBP Device") } #endif + +#ifdef EC_ENABLE_CBAS_DEVICE + Device (CBAS) + { + Name (_HID, "GOOG0010") + Name (_UID, 1) + Name (_DDN, "EC Base Switch Device") + } +#endif } diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h index 92c7467..7e16801 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h @@ -77,5 +77,6 @@ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ +#define EC_ENABLE_CBAS_DEVICE /* Enable "Base Attached Switch" device */ #endif /* __MAINBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/28260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id73a12f04a1a48f7fbd9365c2a501afadf3878fa Gerrit-Change-Number: 28260 Gerrit-PatchSet: 1 Gerrit-Owner: Dmitry Torokhov <dtor(a)chromium.org>

1 0

Change in coreboot[master]: soc/intel/apollolake: Fix typo in SW_IDPIN_EN_MASK check
by Furquan Shaikh (Code Review) 21 Aug '18

21 Aug '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/28259 ) Change subject: soc/intel/apollolake: Fix typo in SW_IDPIN_EN_MASK check ...................................................................... soc/intel/apollolake: Fix typo in SW_IDPIN_EN_MASK check This change fixes the check for SW_IDPIN_EN_MASK to use bitwise AND instead of logical AND. Reported by: Coverity CID #1395106 Change-Id: Ib3309eeb2f65f2578dc11a5b93ce9211cb482cb1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/28259/2 -- To view, visit https://review.coreboot.org/28259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib3309eeb2f65f2578dc11a5b93ce9211cb482cb1 Gerrit-Change-Number: 28259 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: soc/intel/apollolake: Fix typo in SW_IDPIN_EN_MASK check
by Furquan Shaikh (Code Review) 21 Aug '18

21 Aug '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28259 Change subject: soc/intel/apollolake: Fix typo in SW_IDPIN_EN_MASK check ...................................................................... soc/intel/apollolake: Fix typo in SW_IDPIN_EN_MASK check This change fixes the check for SW_IDPIN_EN_MASK to use bitwise AND instead of boolean AND. Reported by: Coverity CID #1395106 Change-Id: Ib3309eeb2f65f2578dc11a5b93ce9211cb482cb1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/28259/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 83a6baa..9b8cfd7 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -678,7 +678,7 @@ cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); reg = read32(cfg0); - if (!(reg && SW_IDPIN_EN_MASK)) + if (!(reg & SW_IDPIN_EN_MASK)) return; reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK); -- To view, visit https://review.coreboot.org/28259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib3309eeb2f65f2578dc11a5b93ce9211cb482cb1 Gerrit-Change-Number: 28259 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: mb/intel/dg43gt: Add documentation
by Arthur Heymans (Code Review) 21 Aug '18

21 Aug '18

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/28258 ) Change subject: mb/intel/dg43gt: Add documentation ...................................................................... mb/intel/dg43gt: Add documentation Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/mainboard/index.md A Documentation/mainboard/intel/dg43gt.md A Documentation/mainboard/intel/dg43gt_closeup.jpg A Documentation/mainboard/intel/dg43gt_full.jpg 4 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28258/2 -- To view, visit https://review.coreboot.org/28258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4 Gerrit-Change-Number: 28258 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: mb/intel/dg43gt: Add documentation
by Arthur Heymans (Code Review) 21 Aug '18

21 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28258 Change subject: mb/intel/dg43gt: Add documentation ...................................................................... mb/intel/dg43gt: Add documentation Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/mainboard/index.md A Documentation/mainboard/intel/dg43gt.md A Documentation/mainboard/intel/dg43gt_closeup.jpg A Documentation/mainboard/intel/dg43gt_full.jpg 4 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28258/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 6c75ea2..9301971 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -10,6 +10,10 @@ - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Intel + +- [DG43GT](intel/dg43gt.md) + ## Foxconn - [D41S](foxconn/d41s.md) diff --git a/Documentation/mainboard/intel/dg43gt.md b/Documentation/mainboard/intel/dg43gt.md new file mode 100644 index 0000000..ee970f0 --- /dev/null +++ b/Documentation/mainboard/intel/dg43gt.md @@ -0,0 +1,97 @@ +# Intel DG43GT + +This page describes how to run coreboot on the [Intel DG43GT] desktop. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | W25X32 | ++---------------------+------------+ +| Size | 4 MiB | ++---------------------+------------+ +| In circuit flashing | NO! | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. +Only the BIOS region can and needs to written to. + + # flashrom -p internal --ifd -i bios -w coreboot.rom --noverify + +### External programming + +ISP (in circuit programming) seems to be impossible on this board, which +is a property it shares wth many boards featuring the ICH10 southbridge. +**Recovering from a bad flash will require desoldering the flash!** +Desoldering the SPI flash can easily be done with a hot air station. +Apply some flux around the SPI flash, set the hot air station to 350-400°C +and after heating the chip up for a minute it should be possible to remove it. + +Having removed the flash chip you can reprogram and resolder it using a +soldering iron. +Another option would be to hook up a SPI flash (socket) to the SPI header, +for easier flash removing in the future (if you expect to be hacking on this +board). To do this you first need to solder the SPI header to the board. + +**NOTE: this header cannot be used for ISP either.** + +**NOTE2: Don't forget to connect the WP# and HOLD# pin on the SPI flash to 3V.** + +The layout of the header is: + +``` + +---+---+ + GND <- | x | x | -> SPI_CLK + +---+---+ + 3VSB <- | x | x | -> SPI_MISO + +---+---+ + | | x | -> SPI_MOSI + +---+---+ + SPI_CS# <-| x | x | -> SPI_CS# (again) + +---+---+ +``` + +**Picture of the board with the flash hooked on externally** +![][dg43gt_full] + +**Close up picture of the SPI flash pads and recovery header** +![][dg43gt_closeup] + +[dg43gt_full]: dg43gt_full.jpg +[dg43gt_closeup]: dg43gt_closeup.jpg + +## Technology + +```eval_rst ++------------------+---------------------------------------------------+ +| Northbridge | Intel G43 (called x4x in coreboot code) | ++------------------+---------------------------------------------------+ +| Southbridge | Intel ICH10 (called i82801jx in coreboot code) | ++------------------+---------------------------------------------------+ +| CPU (LGA775) | model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) | ++------------------+---------------------------------------------------+ +| SuperIO | Windond w83627dhg | ++------------------+---------------------------------------------------+ +| Coprocessor | Intel ME (optionnaly enabled) | ++------------------+---------------------------------------------------+ +| Clockgen (CK505) | SLG8XP549T | ++------------------+---------------------------------------------------+ +``` + +[Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/intel/dg43gt_closeup.jpg b/Documentation/mainboard/intel/dg43gt_closeup.jpg new file mode 100644 index 0000000..c747aa8 --- /dev/null +++ b/Documentation/mainboard/intel/dg43gt_closeup.jpg Binary files differ diff --git a/Documentation/mainboard/intel/dg43gt_full.jpg b/Documentation/mainboard/intel/dg43gt_full.jpg new file mode 100644 index 0000000..52f3808 --- /dev/null +++ b/Documentation/mainboard/intel/dg43gt_full.jpg Binary files differ -- To view, visit https://review.coreboot.org/28258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e9dc67e66f719d440679b11332e2c8a764024f4 Gerrit-Change-Number: 28258 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: x86/acpi: Update MADT table version
by Martin Roth (Code Review) 21 Aug '18

21 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28256 ) Change subject: x86/acpi: Update MADT table version ...................................................................... Patch Set 1: Is it worthwhile to do something to keep these in sync in the future? Maybe a function that both tables call to get their values? #define MADT 1 #define FADT 2 int get_fadt_madt_version (int table) { if (table == MADT) return 2; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ if (table == FADT) return ACPI_FADT_REV_ACPI_3_0; return -1; } -- To view, visit https://review.coreboot.org/28256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Gerrit-Change-Number: 28256 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 21 Aug 2018 19:57:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: x86/acpi: Update MADT table version
by Marc Jones (Code Review) 21 Aug '18

21 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28256 Change subject: x86/acpi: Update MADT table version ...................................................................... x86/acpi: Update MADT table version Update the MADT table version to sync with the FADT table version. All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0 and the MADT should be set to match. This error was found by running FWTS: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. The test report is a little confusing due to the revision index not matching the ACPI spec versions. BUG=b:112476331 TEST-Run FWTS Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/arch/x86/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28256/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 8d7579d..69e1e2f 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -218,7 +218,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_madt_t); - header->revision = 1; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ + header->revision = 2; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ madt->lapic_addr = LOCAL_APIC_ADDR; madt->flags = 0x1; /* PCAT_COMPAT */ -- To view, visit https://review.coreboot.org/28256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Gerrit-Change-Number: 28256 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

1 0

Change in libgfxinit[master]: gma pipe_setup: Work around a PFIT_CONTROL quirk on G45
by Arthur Heymans (Code Review) 21 Aug '18

21 Aug '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/28255 Change subject: gma pipe_setup: Work around a PFIT_CONTROL quirk on G45 ...................................................................... gma pipe_setup: Work around a PFIT_CONTROL quirk on G45 In legacy VGA mode pillarbox fails to display anything, so just always force 'auto' mode, which will have the output stretched to fullscreen. Change-Id: Ie7b7be06b5c5bd5569e8a6645dd9359660f7a51a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-pipe_setup.adb 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/55/28255/1 diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb index a45dfb2..cf35379 100644 --- a/common/hw-gfx-gma-pipe_setup.adb +++ b/common/hw-gfx-gma-pipe_setup.adb @@ -543,8 +543,15 @@ when Secondary => GMCH_PFIT_CONTROL_SELECT_PIPE_B, when others => 0); + -- Work around a quirk: + -- In legacy VGA mode Pillarbox fails to display anything so just force + -- 'auto' mode on all displays, which will the output stretched to + -- fullscreen . PF_Ctrl_Scaling : constant Word32 := - GMCH_PFIT_CONTROL_SCALING (Scaling_Type (Framebuffer, Mode)); + (if Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET then + GMCH_PFIT_CONTROL_SCALING (Uniform) + else + GMCH_PFIT_CONTROL_SCALING (Scaling_Type (Framebuffer, Mode))); In_Use : Boolean; begin -- To view, visit https://review.coreboot.org/28255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie7b7be06b5c5bd5569e8a6645dd9359660f7a51a Gerrit-Change-Number: 28255 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: drivers/spi/spi_flash: don't allocate unbounded stack memory
by Patrick Georgi (Code Review) 21 Aug '18

21 Aug '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/28254 Change subject: drivers/spi/spi_flash: don't allocate unbounded stack memory ...................................................................... drivers/spi/spi_flash: don't allocate unbounded stack memory This open-codes flash_cmd, but until the API is fixed for real, it uses xfer's existing scatter-gather ability to write command and data in one go. BUG=chromium:446201 TEST=emerge-coral coreboot succeeds Change-Id: Ic81b7c9f7e0f2647e59b81d61abd68d36051e578 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/drivers/spi/spi_flash.c 1 file changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28254/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index f271479..82333e9 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -82,24 +82,29 @@ return ret; } -/* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ -#pragma GCC diagnostic push -#if defined(__GNUC__) && !defined(__clang__) -#pragma GCC diagnostic ignored "-Wstack-usage=" -#endif int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) { - int ret; - u8 buff[cmd_len + data_len]; - memcpy(buff, cmd, cmd_len); - memcpy(buff + cmd_len, data, data_len); + int ret = 1; + struct spi_op vectors[] = { + [0] = { .dout = cmd, .bytesout = cmd_len, + .din = NULL, .bytesin = 0, }, + [1] = { .dout = data, .bytesout = data_len, + .din = NULL, .bytesin = 0, } + }; + size_t count = ARRAY_SIZE(vectors); - ret = do_spi_flash_cmd(spi, buff, cmd_len + data_len, NULL, 0); + if (spi_claim_bus(spi)) + return ret; + + if (spi_xfer_vector(spi, vectors, count) == 0) + ret = 0; + if (ret) { printk(BIOS_WARNING, "SF: Failed to send write command (%zu bytes): %d\n", data_len, ret); } + spi_release_bus(spi); return ret; } -- To view, visit https://review.coreboot.org/28254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic81b7c9f7e0f2647e59b81d61abd68d36051e578 Gerrit-Change-Number: 28254 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2018