coreboot-gerrit August 2018

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Change in coreboot[master]: google/kukui: Setup GPIOs for ChromeOS.
by Tristan Hsieh (Code Review) 21 Aug '18

21 Aug '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28250 Change subject: google/kukui: Setup GPIOs for ChromeOS. ...................................................................... google/kukui: Setup GPIOs for ChromeOS. Setup LID GPIO to boot depthchrage. Without this patch, flag_fetch(FLAG_LIDSW) in depthcharge will fail BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I0ec2c70c189a059219954e0384aaf98995285728 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/chromeos.c A src/mainboard/google/kukui/gpio.h 4 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28250/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 290be4c..aa6bf11 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += bootblock.c +bootblock-y += chromeos.c bootblock-y += memlayout.ld decompressor-y += memlayout.ld diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index d8b5c5a..fa51488 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -18,10 +18,14 @@ #include <soc/gpio.h> #include <soc/spi.h> +#include "gpio.h" + #define BOOTBLOCK_EN_L (GPIO(KPROW0)) void bootblock_mainboard_init(void) { + setup_chromeos_gpios(); + /* Turn on real eMMC. */ gpio_output(BOOTBLOCK_EN_L, 1); diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 7f9946a..3ed5c1c 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -15,9 +15,21 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <gpio.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(LID); +} void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {LID.id, ACTIVE_HIGH, -1, "lid"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h new file mode 100644 index 0000000..44610f4 --- /dev/null +++ b/src/mainboard/google/kukui/gpio.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GOOGLE_KUKUI_GPIO_H__ +#define __MAINBOARD_GOOGLE_KUKUI_GPIO_H__ + +#include <soc/gpio.h> + +#define LID GPIO(CAM_CLK2) + +void setup_chromeos_gpios(void); + +#endif -- To view, visit https://review.coreboot.org/28250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0ec2c70c189a059219954e0384aaf98995285728 Gerrit-Change-Number: 28250 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: src/mainboard: Add null pointer check
by Furquan Shaikh (Code Review) 21 Aug '18

21 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28235 ) Change subject: src/mainboard: Add null pointer check ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/28235/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28235/3//COMMIT_MSG@7 PS3, Line 7: src/mainboard mb/google/octopus -- To view, visit https://review.coreboot.org/28235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Gerrit-Change-Number: 28235 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 21 Aug 2018 03:20:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: lib/gpio.c: Validate num_gpio
by Richard Spiegel (Code Review) 21 Aug '18

21 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28249 Change subject: lib/gpio.c: Validate num_gpio ...................................................................... lib/gpio.c: Validate num_gpio In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return of an undefined value, as no for loop will be executed. Assert that it's not 0. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/lib/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28249/1 diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 0656dfb..482f62d 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -82,7 +82,7 @@ int index; int temp; char value[32]; - assert(num_gpio <= 32); + assert((num_gpio <= 32) && (num_gpio > 0)); /* Enable internal pull up */ for (index = 0; index < num_gpio; ++index) -- To view, visit https://review.coreboot.org/28249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80 Gerrit-Change-Number: 28249 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/intel/cannonlake: Change LPDDR4 to MEMCFG
by Lijian Zhao (Code Review) 20 Aug '18

20 Aug '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28248 Change subject: soc/intel/cannonlake: Change LPDDR4 to MEMCFG ...................................................................... soc/intel/cannonlake: Change LPDDR4 to MEMCFG Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/zoombini/Kconfig M src/mainboard/google/zoombini/memory.c M src/mainboard/google/zoombini/romstage.c M src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zoombini/variants/meowth/memory.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc R src/soc/intel/cannonlake/cnl_memcfg_init.c R src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 9 files changed, 35 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28248/1 diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig index d28f662..656d8b0 100644 --- a/src/mainboard/google/zoombini/Kconfig +++ b/src/mainboard/google/zoombini/Kconfig @@ -12,7 +12,7 @@ select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CANNONLAKE - select SOC_INTEL_CANNONLAKE_LPDDR4_INIT + select SOC_INTEL_CANNONLAKE_MEMCFG_INIT if BOARD_GOOGLE_BASEBOARD_ZOOMBINI diff --git a/src/mainboard/google/zoombini/memory.c b/src/mainboard/google/zoombini/memory.c index e1f5255..e8dae5a 100644 --- a/src/mainboard/google/zoombini/memory.c +++ b/src/mainboard/google/zoombini/memory.c @@ -17,9 +17,9 @@ #include <baseboard/gpio.h> #include <compiler.h> #include <gpio.h> -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> -static const struct lpddr4_cfg baseboard_lpddr4_cfg = { +static const struct cnl_mb_cfg baseboard_lpddr4_cfg = { .dq_map[LP4_CH0] = { /* * CLK0 goes to package 0 - Bytes[3:0], @@ -82,7 +82,7 @@ .ect = 0, }; -const struct lpddr4_cfg *__weak variant_lpddr4_config(void) +const struct cnl_mb_cfg *__weak variant_lpddr4_config(void) { return &baseboard_lpddr4_cfg; } diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c index 8e19177..4bd0ede 100644 --- a/src/mainboard/google/zoombini/romstage.c +++ b/src/mainboard/google/zoombini/romstage.c @@ -14,7 +14,7 @@ */ #include <baseboard/variants.h> -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -24,6 +24,6 @@ .spd_spec.spd_index = variant_memory_sku(), }; - cannonlake_lpddr4_init(&memupd->FspmConfig, + cannonlake_memcfg_init(&memupd->FspmConfig, variant_lpddr4_config(), &spd); } diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h index eab081d..eac0fee 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h @@ -17,7 +17,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> #include <soc/gpio.h> #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -35,7 +35,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); /* Return LPDDR4 configuration structure. */ -const struct lpddr4_cfg *variant_lpddr4_config(void); +const struct cnl_mb_cfg *variant_lpddr4_config(void); /* Return memory SKU for the board. */ size_t variant_memory_sku(void); diff --git a/src/mainboard/google/zoombini/variants/meowth/memory.c b/src/mainboard/google/zoombini/variants/meowth/memory.c index c72ffea..d672521 100644 --- a/src/mainboard/google/zoombini/variants/meowth/memory.c +++ b/src/mainboard/google/zoombini/variants/meowth/memory.c @@ -16,9 +16,9 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> #include <gpio.h> -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> -static const struct lpddr4_cfg meowth_lpddr4_cfg = { +static const struct cnl_mb_cfg meowth_lpddr4_cfg = { .dq_map[LP4_CH0] = { /* * CLK0 goes to package 0 - Bytes[3:0], @@ -86,7 +86,7 @@ .ect = 1, }; -const struct lpddr4_cfg *variant_lpddr4_config(void) +const struct cnl_mb_cfg *variant_lpddr4_config(void) { return &meowth_lpddr4_cfg; } diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index e6a2062..ef39706 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -184,7 +184,7 @@ int default 100 -config SOC_INTEL_CANNONLAKE_LPDDR4_INIT +config SOC_INTEL_CANNONLAKE_MEMCFG_INIT bool default n diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 013e86a..065d92b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -22,7 +22,7 @@ bootblock-y += p2sb.c bootblock-$(CONFIG_UART_DEBUG) += uart.c -romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c +romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c diff --git a/src/soc/intel/cannonlake/cnl_lpddr4_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c similarity index 79% rename from src/soc/intel/cannonlake/cnl_lpddr4_init.c rename to src/soc/intel/cannonlake/cnl_memcfg_init.c index ea8c410..b4353e3 100644 --- a/src/soc/intel/cannonlake/cnl_lpddr4_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -15,12 +15,12 @@ #include <assert.h> #include <console/console.h> #include <fsp/util.h> -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> #include <spd_bin.h> #include <string.h> -static void meminit_lpddr4(FSP_M_CONFIG *mem_cfg, - const struct lpddr4_cfg *board_cfg, +static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, + const struct cnl_mb_cfg *board_cfg, size_t spd_data_len, uintptr_t spd_data_ptr) { /* @@ -58,12 +58,12 @@ /* * Initialize default LPDDR4 settings using spd data contained in a buffer. */ -static void meminit_lpddr4_spd_data(FSP_M_CONFIG *mem_cfg, - const struct lpddr4_cfg *cnl_cfg, +static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, + const struct cnl_mb_cfg *cnl_cfg, size_t spd_data_len, uintptr_t spd_data_ptr) { assert(spd_data_ptr && spd_data_len); - meminit_lpddr4(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); + meminit_memcfg(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); } /* @@ -71,8 +71,8 @@ * spd_index. The spd_index is an index into the SPD_SOURCES array defined * in spd/Makefile.inc. */ -static void meminit_lpddr4_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, - const struct lpddr4_cfg *cnl_cfg, +static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, + const struct cnl_mb_cfg *cnl_cfg, int spd_index) { size_t spd_data_len; @@ -86,25 +86,23 @@ /* Memory leak is ok since we have memory mapped boot media */ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); - meminit_lpddr4_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); + meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); } -/* Initialize LPDDR4 settings for CannonLake */ -void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg, - const struct lpddr4_cfg *cnl_cfg, +/* Initialize onboard memory configurations for CannonLake */ +void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, + const struct cnl_mb_cfg *cnl_cfg, const struct spd_info *spd) { /* Early Command Training Enabled */ mem_cfg->ECT = cnl_cfg->ect; mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved; - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ if (spd->spd_by_index) { - meminit_lpddr4_cbfs_spd_index(mem_cfg, cnl_cfg, + meminit_cbfs_spd_index(mem_cfg, cnl_cfg, spd->spd_spec.spd_index); } else { - meminit_lpddr4_spd_data(mem_cfg, cnl_cfg, + meminit_spd_data(mem_cfg, cnl_cfg, spd->spd_spec.spd_data_ptr_info.spd_data_len, spd->spd_spec.spd_data_ptr_info.spd_data_ptr); } diff --git a/src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h similarity index 88% rename from src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h rename to src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index db1c3a5..eed714d 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_lpddr4_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_CANNONLAKE_LPDDR4_INIT_H_ -#define _SOC_CANNONLAKE_LPDDR4_INIT_H_ +#ifndef _SOC_CANNONLAKE_MEMCFG_INIT_H_ +#define _SOC_CANNONLAKE_MEMCFG_INIT_H_ #include <stddef.h> #include <stdint.h> @@ -24,7 +24,7 @@ #define DQ_BITS_PER_DQS 8 /* - * Number of LPDDR4 packages, where a "package" represents a 64-bit solution. + * Number of memory packages, where a "package" represents a 64-bit solution. */ #define LP4_NUM_PACKAGES 2 @@ -49,7 +49,7 @@ }; /* Board-specific lpddr4 dq mapping information */ -struct lpddr4_cfg { +struct cnl_mb_cfg { /* * For each channel, there are 3 sets of DQ byte mappings, * where each set has a package 0 and a package 1 value (package 0 @@ -97,10 +97,10 @@ }; /* - * Initialize default LPDDR4 settings for CannonLake. + * Initialize default memory configurations for CannonLake. */ -void cannonlake_lpddr4_init(FSP_M_CONFIG *mem_cfg, - const struct lpddr4_cfg *cnl_cfg, +void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, + const struct cnl_mb_cfg *cnl_cfg, const struct spd_info *spd); -#endif /* _SOC_CANNONLAKE_LPDDR4_INIT_H_ */ +#endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */ -- To view, visit https://review.coreboot.org/28248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Gerrit-Change-Number: 28248 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: src/mainboard: Add null pointer check
by John Zhao (Code Review) 20 Aug '18

20 Aug '18

Hello build bot (Jenkins), Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28235 to look at the new patch set (#3). Change subject: src/mainboard: Add null pointer check ...................................................................... src/mainboard: Add null pointer check src/mainboard/google/octopus/mainboard.c Found-by: klockwork Function dev_find_slot may return NULL, check before its usage. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/mainboard/google/octopus/mainboard.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28235/3 -- To view, visit https://review.coreboot.org/28235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Gerrit-Change-Number: 28235 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge/smihandler.c: Report pending wake event
by Richard Spiegel (Code Review) 20 Aug '18

20 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28247 Change subject: soc/amd/stoneyridge/smihandler.c: Report pending wake event ...................................................................... soc/amd/stoneyridge/smihandler.c: Report pending wake event There's a small window of opportunity when CPU is already in SMM but has not yet entered S3 for a wake event to happen, which would cause a failed S3 entry. Check for pending events at the very last moment possible, and if there are pending wake events report them. BUG=b:111100312 TEST=build and boot grunt. Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28247/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index ef24baa..f00ead6 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -122,7 +122,8 @@ static void sb_slp_typ_handler(void) { - uint32_t pm1cnt, pci_ctrl; + uint32_t pm1cnt, pci_ctrl, reg32; + uint16_t reg16; uint8_t slp_typ, rst_ctrl; /* Figure out SLP_TYP */ @@ -171,6 +172,33 @@ rst_ctrl |= SLPTYPE_CONTROL_EN; pm_write8(PM_RST_CTRL1, rst_ctrl); + /* + * Before the final command, check if there's pending wake + * event. Read enable first, so that reading the actual status + * is as close as possible to entering S3. The idea is to + * minimize the opportunity for a wake event to happen before + * actually entering S3. If there's a pending wake event, log + * it and continue normal path. S3 will fail and the wake event + * becomes a SCI. + */ + reg16 = inw(ACPI_PM1_EN); + reg32 = inl(ACPI_GPE0_EN); + if (IS_ENABLED(CONFIG_ELOG_GSMI)) { + if ((reg16 & inw(ACPI_PM1_STS)) || + (reg32 & inl(ACPI_GPE0_STS))) { + reg16 &= inw(ACPI_PM1_STS); + if (reg16) + elog_add_error( + ELOG_SLEEP_PENDING_PM1_WAKE, + (u32)reg16); + reg32 &= inl(ACPI_GPE0_STS); + if (reg32) + elog_add_error( + ELOG_SLEEP_PENDING_GPE0_WAKE, + reg32); + } + } /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */ + /* Reissue Pm1 write */ outl(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk()); hlt(); -- To view, visit https://review.coreboot.org/28247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a Gerrit-Change-Number: 28247 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: drivers/elog/elog.c: Create extended error event
by Richard Spiegel (Code Review) 20 Aug '18

20 Aug '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28246 Change subject: drivers/elog/elog.c: Create extended error event ...................................................................... drivers/elog/elog.c: Create extended error event For debug reasons, sometimes you not only want to log an error event, but also some extra information that would help debugging. Create an extended error reporting event with a dword complement, and define error events for failing to enter S3 due to pending wake event (one for pm1 and one for gpe0). BUG=b:111100312 TEST=Add a fake error event, build and boot grunt, see the event in eventlog.txt. Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/drivers/elog/elog.c M src/include/elog.h 2 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/28246/1 diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 6fc4053..124b659 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -933,6 +933,17 @@ return elog_add_event_raw(ELOG_TYPE_WAKE_SOURCE, &wake, sizeof(wake)); } +int elog_add_error(u8 type, u32 complement) +{ + struct elog_event_extended_error error = { + .error_type = type, + .error_complement = complement + }; + return elog_add_event_raw(ELOG_TYPE_EXTENDED_ERROR, + &error, + sizeof(error)); +} + /* Make sure elog_init() runs at least once to log System Boot event. */ static void elog_bs_init(void *unused) { elog_init(); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_bs_init, NULL); diff --git a/src/include/elog.h b/src/include/elog.h index 0776c36..3b4461b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -115,7 +115,11 @@ /* Sleep/Wake */ #define ELOG_TYPE_ACPI_ENTER 0x9d -/* Deep Sx wake variant is provided below - 0xad */ +/* + * Deep Sx wake variant is provided below - 0xad + * Sleep/wake errors log provided below - 0xb1 - 0x01/0x02 + */ + #define ELOG_TYPE_ACPI_WAKE 0x9e #define ELOG_TYPE_WAKE_SOURCE 0x9f #define ELOG_WAKE_SOURCE_PCIE 0x00 @@ -219,6 +223,16 @@ #define ELOG_TYPE_S0IX_ENTER 0xaf #define ELOG_TYPE_S0IX_EXIT 0xb0 +/* Extended errors */ +#define ELOG_TYPE_EXTENDED_ERROR 0xb1 +#define ELOG_SLEEP_PENDING_PM1_WAKE 0x01 +#define ELOG_SLEEP_PENDING_GPE0_WAKE 0x02 + +struct elog_event_extended_error { + u8 error_type; + u32 error_complement; +} __packed; + #if IS_ENABLED(CONFIG_ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); @@ -231,6 +245,7 @@ extern int elog_add_event_dword(u8 event_type, u32 data); extern int elog_add_event_wake(u8 source, u32 instance); extern int elog_smbios_write_type15(unsigned long *current, int handle); +extern int elog_add_error(u8 type, u32 complement); #else /* Stubs to help avoid littering sources with #if CONFIG_ELOG */ static inline int elog_init(void) { return -1; } @@ -246,6 +261,7 @@ int handle) { return 0; } +static inline int elog_add_error(u8 type, u32 complement) { return 0; } #endif extern u32 gsmi_exec(u8 command, u32 *param); -- To view, visit https://review.coreboot.org/28246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5 Gerrit-Change-Number: 28246 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Correct mainboard info
by Lijian Zhao (Code Review) 20 Aug '18

20 Aug '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28236 Change subject: mb/intel/coffeelake_rvp: Correct mainboard info ...................................................................... mb/intel/coffeelake_rvp: Correct mainboard info There's only DDR4 or LPDDR3 support for coffelake processor line, details can be found out on EDS #570805. BUG=N/A TEST=N/A Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig.name 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28236/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 093288b..f6e5041 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -1,6 +1,6 @@ comment "Coffeelake RVP" config BOARD_INTEL_COFFEELAKE_RVPU - bool "-> Coffeelake U LPDDR4 RVP" + bool "-> Coffeelake U DDR4 RVP" config BOARD_INTEL_COFFEELAKE_RVP11 - bool "-> Coffeelake H LPDDR4 RVP11" + bool "-> Coffeelake H DDR4 RVP11" -- To view, visit https://review.coreboot.org/28236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706 Gerrit-Change-Number: 28236 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: src/mainboard: Fix issues found by klockwork
by John Zhao (Code Review) 20 Aug '18

20 Aug '18

Hello Hannah Williams, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28235 to look at the new patch set (#2). Change subject: src/mainboard: Fix issues found by klockwork ...................................................................... src/mainboard: Fix issues found by klockwork src/mainboard/google/octopus/mainboard.c Function wifi_device_update: Check for NULL before using pointer. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/mainboard/google/octopus/mainboard.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28235/2 -- To view, visit https://review.coreboot.org/28235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Gerrit-Change-Number: 28235 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/mainboard: Fix issues found by klockwork
by John Zhao (Code Review) 20 Aug '18

20 Aug '18

John Zhao has uploaded this change for review. ( https://review.coreboot.org/28235 Change subject: src/mainboard: Fix issues found by klockwork ...................................................................... src/mainboard: Fix issues found by klockwork src/mainboard/google/octopus/mainboard.c Function wifi_device_update: Pointer dev returned from call dev_find_slot may be NULL and will be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/mainboard/google/octopus/mainboard.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28235/1 diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index 61d254e..6effa7c 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -169,7 +169,8 @@ devfn = PCH_DEVFN_PCIE1; dev = dev_find_slot(0, devfn); - dev->enabled = 0; + if (dev) + dev->enabled = 0; } void mainboard_devtree_update(struct device *dev) -- To view, visit https://review.coreboot.org/28235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Gerrit-Change-Number: 28235 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com>

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coreboot-gerrit August 2018