coreboot-gerrit August 2018

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Change in coreboot[master]: lib/nhtl: Use common function to set NHTL version
by Marc Jones (Code Review) 23 Aug '18

23 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28279 Change subject: lib/nhtl: Use common function to set NHTL version ...................................................................... lib/nhtl: Use common function to set NHTL version Set NHLT version with get_acpi_revision(NHTL) to keep all table versions in sync. Change-Id: I4ea9d511142e4ea68e651e58c2c985e739c032d9 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/lib/nhlt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28279/1 diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index f6135c7..5001c38 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -413,7 +413,7 @@ memset(header, 0, sizeof(acpi_header_t)); memcpy(header->signature, "NHLT", 4); write_le32(&header->length, sz); - write_le8(&header->revision, 5); + write_le8(&header->revision, get_acpi_table_revision(NHLT)); if (oem_id == NULL) oem_id = OEM_ID; -- To view, visit https://review.coreboot.org/28279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4ea9d511142e4ea68e651e58c2c985e739c032d9 Gerrit-Change-Number: 28279 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: intel: Use common HPET table revision function
by Marc Jones (Code Review) 23 Aug '18

23 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28278 Change subject: intel: Use common HPET table revision function ...................................................................... intel: Use common HPET table revision function Use get_acpi_table_revision(HPET) to keep all table versions in sync. Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/intel/lynxpoint/acpi.c 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/28278/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 31435f7..a43e6b6 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -147,7 +147,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_hpet_t); - header->revision = 1; + header->revision = get_acpi_table_revision(HPET); /* fill out HPET address */ addr->space_id = 0; /* Memory */ diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index af8e012..d826d43 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -200,7 +200,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_hpet_t); - header->revision = 1; + header->revision = get_acpi_table_revision(HPET); /* fill out HPET address */ addr->space_id = 0; /* Memory */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index f4dd545..97c8d5b 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -144,7 +144,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_hpet_t); - header->revision = 1; + header->revision = get_acpi_table_revision(HPET); /* fill out HPET address */ addr->space_id = 0; /* Memory */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 9b64edc..5d65477 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -125,7 +125,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_hpet_t); - header->revision = 1; + header->revision = get_acpi_table_revision(HPET); /* fill out HPET address */ addr->space_id = 0; /* Memory */ diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 2a02744..7f6a5ad 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -36,7 +36,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_hpet_t); - header->revision = 1; + header->revision = get_acpi_table_revision(HPET); /* fill out HPET address */ addr->space_id = 0; /* Memory */ -- To view, visit https://review.coreboot.org/28278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669 Gerrit-Change-Number: 28278 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: update all FADT version 3.0 to use the get tables function
by Marc Jones (Code Review) 23 Aug '18

23 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28277 Change subject: update all FADT version 3.0 to use the get tables function ...................................................................... update all FADT version 3.0 to use the get tables function Most FADT report using ACPIv3 FADT table. Using the get revision function keeps the table versions in sync. Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/beltino/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/google/slippy/fadt.c M src/mainboard/purism/librem_bdw/fadt.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/skylake/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/fsp_rangeley/acpi.c 17 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28277/1 diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 418d547..9e44b85 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -37,7 +37,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 4; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index dea67d0..c96ae68 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -24,7 +24,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/google/beltino/fadt.c b/src/mainboard/google/beltino/fadt.c index 486a343..806902d 100644 --- a/src/mainboard/google/beltino/fadt.c +++ b/src/mainboard/google/beltino/fadt.c @@ -27,7 +27,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index d62c28d..29e2d2a 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -24,7 +24,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index dea67d0..c96ae68 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -24,7 +24,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index b0fe9d6..4aa4ec6 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -23,7 +23,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c index fe86f56..8a04591 100644 --- a/src/mainboard/google/slippy/fadt.c +++ b/src/mainboard/google/slippy/fadt.c @@ -27,7 +27,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index 9cbcd3f..fbce9d7 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -23,7 +23,7 @@ memset(fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 7b4f07b..4094c38 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -77,7 +77,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index ae645a5..8fdaeee 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -110,7 +110,7 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; /* Use ACPI 3.0 revision. */ - fadt->header.revision = ACPI_FADT_REV_ACPI_3_0; + fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 748b6cf..f4dd545 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -191,7 +191,7 @@ /* FADT Header Structure */ memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 38b4d47..9b64edc 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -167,7 +167,7 @@ /* FADT Header Structure */ memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index cff610f..44096cd 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -241,7 +241,7 @@ const uint16_t pmbase = ACPI_BASE_ADDRESS; /* Use ACPI 3.0 revision */ - fadt->header.revision = ACPI_FADT_REV_ACPI_3_0; + fadt->header.revision = get_acpi_table_revision(FADT); fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index c1d9b72..1cb9875 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -49,7 +49,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index ad47ad7..59e61da 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -53,7 +53,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 84c6a1d..c2a3ff4 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -49,7 +49,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index 45f0558..ca711dc 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -48,7 +48,7 @@ /* FADT Header Structure */ memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = ACPI_FADT_REV_ACPI_3_0; + header->revision = get_acpi_table_revision(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); -- To view, visit https://review.coreboot.org/28277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Gerrit-Change-Number: 28277 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: x86/acpi: Add ACPI tablie revision function
by Marc Jones (Code Review) 23 Aug '18

23 Aug '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/28276 Change subject: x86/acpi: Add ACPI tablie revision function ...................................................................... x86/acpi: Add ACPI tablie revision function Use a single function to set ACPI table version. This allows us to keep revisions synced to the correct levels for coreboot. This is a partial fix for the bug: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 80 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28276/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 78eeaa7..6e3f4c9 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -218,7 +218,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_madt_t); - header->revision = 1; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ + header->revision = get_acpi_table_revision(MADT); madt->lapic_addr = LOCAL_APIC_ADDR; madt->flags = 0x1; /* PCAT_COMPAT */ @@ -246,7 +246,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_mcfg_t); - header->revision = 1; + header->revision = get_acpi_table_revision(MCFG); current = acpi_fill_mcfg(current); @@ -299,7 +299,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_tcpa_t); - header->revision = 2; + header->revision = get_acpi_table_revision(TCPA); tcpa->platform_class = 0; tcpa->laml = tcpa_log_len; @@ -339,7 +339,7 @@ memset((void *)ssdt, 0, sizeof(acpi_header_t)); memcpy(&ssdt->signature, "SSDT", 4); - ssdt->revision = 2; /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */ + ssdt->revision = get_acpi_table_revision(SSDT); memcpy(&ssdt->oem_id, OEM_ID, 6); memcpy(&ssdt->oem_table_id, oem_table_id, 8); ssdt->oem_revision = 42; @@ -410,7 +410,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_srat_t); - header->revision = 1; /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */ + header->revision = get_acpi_table_revision(SRAT); srat->resv = 1; /* Spec: Reserved to 1 for backwards compatibility. */ @@ -436,7 +436,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_dmar_t); - header->revision = 1; + header->revision = get_acpi_table_revision(DMAR); dmar->host_address_width = cpu_phys_address_size() - 1; dmar->flags = flags; @@ -569,7 +569,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_slit_t); - header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + header->revision = get_acpi_table_revision(SLIT); current = acpi_fill_slit(current); @@ -593,7 +593,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_hpet_t); - header->revision = 1; /* Currently 1. Table added in ACPI 2.0. */ + header->revision = get_acpi_table_revision(HPET); /* Fill out HPET address. */ addr->space_id = 0; /* Memory */ @@ -626,7 +626,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(struct acpi_vfct); - header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + header->revision = get_acpi_table_revision(VFCT); current = acpi_fill_vfct(device, vfct, current); @@ -651,7 +651,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_ivrs_t); - header->revision = IVRS_FORMAT_FIXED; + header->revision = get_acpi_table_revision(IVRS); current = acpi_fill_ivrs(ivrs, current); @@ -696,7 +696,7 @@ current = (uintptr_t)dbg2; memset(dbg2, 0, sizeof(acpi_dbg2_header_t)); header = &(dbg2->header); - header->revision = 0; + header->revision = get_acpi_table_revision(DBG2); memcpy(header->signature, "DBG2", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -807,7 +807,7 @@ facs->flags = 0; facs->x_firmware_waking_vector_l = 0; facs->x_firmware_waking_vector_h = 0; - facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */ + facs->version = get_acpi_table_revision(FACS); } static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id) @@ -821,7 +821,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_rsdt_t); - header->revision = 1; /* ACPI 1.0/2.0/3.0/4.0: 1 */ + header->revision = get_acpi_table_revision(RSDT); /* Entries are filled in later, we come with an empty set. */ @@ -840,7 +840,7 @@ memcpy(header->asl_compiler_id, ASLC, 4); header->length = sizeof(acpi_xsdt_t); - header->revision = 1; /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */ + header->revision = get_acpi_table_revision(XSDT); /* Entries are filled in later, we come with an empty set. */ @@ -870,7 +870,7 @@ rsdp->revision = 0; } else { rsdp->xsdt_address = (u64)(uintptr_t)xsdt; - rsdp->revision = 2; + rsdp->revision = get_acpi_table_revision(RSDP); } /* Calculate checksums. */ @@ -950,7 +950,7 @@ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); header->length += sizeof(acpi_hest_t); - header->revision = 1; + header->revision = get_acpi_table_revision(HEST); acpi_fill_hest(hest); @@ -966,7 +966,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 4; + header->revision = get_fadt_madt_version(FADT); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -1256,3 +1256,48 @@ { return -1; /* implemented by SOC */ } + +int get_acpi_table_revision(enum acpi_tables table) +{ + switch (table) { + case FADT: + return ACPI_FADT_REV_ACPI_3_0; + case MADT: /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ + return 1; + case MCFG: + return 1; + case TCPA: + return 2; + case SSDT: /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */ + return 2; + case SRAT: /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */ + return 1; /* TODO Should probably be upgraded to 2 */ + case DMAR: + return 1; + case SLIT: /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + return 1; + case HPET: /* Currently 1. Table added in ACPI 2.0. */ + return 1; + case VFCT: /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + return 1; + case IVRS: + return IVRS_FORMAT_FIXED; + case DBG2: + return 0; + case FACS: /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */ + return 1; + case RSDT: /* ACPI 1.0/2.0/3.0/4.0: 1 */ + return 1; + case XSDT: /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */ + return 1; + case RSDP: /* ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2. */ + return 2; + case HEST: + return 1; + case NHLT: + return 5; + default: + return -1; + } + return -1; +} diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 40fbd54..59c791d 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -76,6 +76,18 @@ COREBOOT_ACPI_ID_MAX = 0xFFFF, /* BOOTFFFF */ }; +/* Table 5-30 DESCRIPTION_HEADER Signatures for tables defined by ACPI 6.2a + * Additional tables mssing in 5-30: MADT, RSDP, VFCT, NHLT + */ +enum acpi_tables { + APIC, BERT, BGRT, CPEP, DSDT, ECDT, EINJ, ERST, FACP, FADT, FACS, + FPDT, GTDT, HEST, MSCT, MPST, NFIT, OEMX, PCCT, PMTT, PSDT, RASF, + RSDT, SBST, SDEV, SLIT, SRAT, SSDT, XSDT, BOOT, CSRT, DBG2, DBGP, + DMAR, DPPT, DRTM, ETDT, HPET, IBFT, IORT, IVRS, LPIT, MCFG, MCHI, + MSDM, SDEI, SLIC, SPCR, SPMI, STAO, TCPA, TPM2, WAET, WDAT, WDRT, + WPBT, WSMT, XENV, MADT, RSDP, VFCT, NHLT +}; + /* RSDP (Root System Description Pointer) */ typedef struct acpi_rsdp { char signature[8]; /* RSDP signature */ @@ -845,6 +857,12 @@ return ALIGN(current, 16); } +/* ACPI table revisions should match the revision of the ACPI spec + * supported. This function keeps the talbe versions synced. This could + * be made into a weak function if there is ever a need to override the + * coreboot default ACPI spec version supported. */ +int get_acpi_table_revision(enum acpi_tables table); + #endif // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__) #endif /* __ASM_ACPI_H */ -- To view, visit https://review.coreboot.org/28276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b Gerrit-Change-Number: 28276 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

1 0

Change in coreboot[master]: x86/acpi: Update MADT table version
by Marc Jones (Code Review) 23 Aug '18

23 Aug '18

Hello Marshall Dawson, Duncan Laurie, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28256 to look at the new patch set (#2). Change subject: x86/acpi: Update MADT table version ...................................................................... x86/acpi: Update MADT table version Update the MADT table version to sync with the FADT table version. All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0 and the MADT should be set to match. This error was found by running FWTS: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/arch/x86/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/28256/2 -- To view, visit https://review.coreboot.org/28256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Gerrit-Change-Number: 28256 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: nocturne: Set eMMC tuning param.
by Pratikkumar V Prajapati (Code Review) 23 Aug '18

23 Aug '18

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/28275 Change subject: nocturne: Set eMMC tuning param. ...................................................................... nocturne: Set eMMC tuning param. WIP. BUG=b:112718426,b:112690628 BRANCH=none TEST=TBD. Change-Id: If2665415cfe162a0a5061f72baad8b0ae37ee686 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28275/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index a6988fa..27358f9 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -47,6 +47,9 @@ register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" + register "EmmcHs400DllNeed" = "1" + register "ScsEmmcHs400RxStrobeDll1" = "0x09" + register "ScsEmmcHs400TxDataDll" = "0x0c" register "PttSwitch" = "0" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" -- To view, visit https://review.coreboot.org/28275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2665415cfe162a0a5061f72baad8b0ae37ee686 Gerrit-Change-Number: 28275 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

1 0

Change in coreboot[master]: skylake, kabylake: Add support to set eMMC tuning param from dev tree
by Pratikkumar V Prajapati (Code Review) 23 Aug '18

23 Aug '18

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/28274 Change subject: skylake,kabylake: Add support to set eMMC tuning param from dev tree ...................................................................... skylake,kabylake: Add support to set eMMC tuning param from dev tree Add support to set eMMC tuning params from the device tree so that it can be configured per board. BUG=b:112718426,b:112690628 BRANCH=none TEST=Build nocturne image and checked values passed in dev tree is set by FSP. Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28274/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index ec8b461..101ac61 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -288,6 +288,9 @@ u8 ScsEmmcEnabled; u8 ScsEmmcHs400Enabled; u8 ScsSdCardEnabled; + u8 EmmcHs400DllNeed; + u8 ScsEmmcHs400RxStrobeDll1; + u8 ScsEmmcHs400TxDataDll; u8 PttSwitch; u8 HeciTimeouts; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d5f5433..c2c0745 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -336,6 +336,15 @@ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; params->ScsSdCardEnabled = config->ScsSdCardEnabled; + if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { + params->PchScsEmmcHs400DllDataValid = + !!config->EmmcHs400DllNeed; + params->PchScsEmmcHs400RxStrobeDll1 = + config->ScsEmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = + config->ScsEmmcHs400TxDataDll; + } + /* If ISH is enabled, enable ISH elements */ dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) -- To view, visit https://review.coreboot.org/28274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385 Gerrit-Change-Number: 28274 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

1 0

Change in coreboot[master]: src/vendorcode/amd/agesa/f15tn: microcode update to version 0x600111F...
by Mike Banon (Code Review) 23 Aug '18

23 Aug '18

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/28273 Change subject: src/vendorcode/amd/agesa/f15tn: microcode update to version 0x600111F 2018-03-05 ...................................................................... src/vendorcode/amd/agesa/f15tn: microcode update to version 0x600111F 2018-03-05 This microcode update for CPU IDs 0x610F01/0x610F31 improves system stability: in particular, fixes Xen hardware virtualization freezes. Also it attempts to patch some Spectre-related security vulnerabilities. This new microcode has been tested by multiple coreboot community members and found working perfectly. Old version: 0x600110F [2012-01-11] replaced by New version: 0x600111F [2018-03-05] Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- M src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h D src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c A src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc 4 files changed, 408 insertions(+), 2,676 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28273/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h index f0d9194..bd00756 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h @@ -808,9 +808,9 @@ #define F15_TN_UCODE_0E #if AGESA_ENTRY_INIT_EARLY == TRUE - extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc []; + extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc []; #undef F15_TN_UCODE_10F - #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600110F_Enc, + #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc, #endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c deleted file mode 100644 index 80e60f6..0000000 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +++ /dev/null @@ -1,2673 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD F15Tn Microcode patch. - * - * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: CPU/Family/0x15/TN - * @e \$Revision: 64060 $ @e \$Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - - - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "cpuRegisters.h" -#include "cpuEarlyInit.h" -CODE_GROUP (G3_DXE) -RDATA_GROUP (G3_DXE) - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -// Encrypt Patch code 0600110F for 6101 and equivalent - -CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] = -{ - 0x12, - 0x20, - 0x11, - 0x01, - 0x0f, - 0x11, - 0x00, - 0x06, - 0x02, - 0x80, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x01, - 0x61, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0xd4, - 0x3d, - 0x97, - 0xf0, - 0xd2, - 0x1a, - 0xcf, - 0x44, - 0x1d, - 0x45, - 0x82, - 0x13, - 0xec, - 0xcd, - 0x52, - 0x24, - 0x2d, - 0x26, - 0x73, - 0x9f, - 0x0e, - 0x38, - 0x80, - 0x5b, - 0x02, - 0x6a, - 0xd3, - 0x80, - 0x97, - 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2018, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +// Encrypt Patch code 0600111F for 6101/6131 and equivalent + +CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc [IDS_PAD_4K] = +{ + 0x18, 0x20, 0x05, 0x03, 0x1f, 0x11, 0x00, 0x06, + 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xd0, 0xb7, 0x58, 0x1c, 0xca, 0xa2, 0xf2, 0x52, + 0x72, 0xa4, 0xe1, 0x1b, 0x37, 0xe0, 0x9f, 0xb3, + 0x58, 0xf4, 0x76, 0x85, 0x1a, 0x83, 0x4a, 0x89, + 0x78, 0x82, 0x4e, 0xf3, 0xa1, 0x6a, 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*---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc index 7d52cb6..e4b0424 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/Makefile.inc @@ -4,7 +4,7 @@ libagesa-y += F15TnInitEarlyTable.c libagesa-y += F15TnIoCstate.c libagesa-y += F15TnLogicalIdTables.c -libagesa-y += F15TnMicrocodePatch0600110F_Enc.c +libagesa-y += F15TnMicrocodePatch0600111F_Enc.c libagesa-y += F15TnMicrocodePatchTables.c libagesa-y += F15TnMsrTables.c libagesa-y += F15TnPciTables.c -- To view, visit https://review.coreboot.org/28273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ied5da0ff85abb63c2db2eeafd051b8e00916d961 Gerrit-Change-Number: 28273 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com>

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Change in coreboot[master]: x86/acpi: Update MADT table version
by Martin Roth (Code Review) 22 Aug '18

22 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28256 ) Change subject: x86/acpi: Update MADT table version ...................................................................... Patch Set 1: Did you want to just get this in and do that in a follow-on or update this patch? -- To view, visit https://review.coreboot.org/28256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Gerrit-Change-Number: 28256 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Aug 2018 16:38:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: x86/acpi: Update MADT table version
by Marc Jones (Code Review) 22 Aug '18

22 Aug '18

Marc Jones has posted comments on this change. ( https://review.coreboot.org/28256 ) Change subject: x86/acpi: Update MADT table version ...................................................................... Patch Set 1: > Patch Set 1: > > Is it worthwhile to do something to keep these in sync in the future? Maybe a function that both tables call to get their values? > > #define MADT 1 > #define FADT 2 > > int get_fadt_madt_version (int table) > { > if (table == MADT) > return 2; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ > if (table == FADT) > return ACPI_FADT_REV_ACPI_3_0; > return -1; I guess we should expand it to every table type revision. -- To view, visit https://review.coreboot.org/28256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Gerrit-Change-Number: 28256 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Aug 2018 16:18:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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