coreboot-gerrit August 2018

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Change in coreboot[master]: commonlib/timestamp_serialized: Add AGESA timestamp descriptions
by Richard Spiegel (Code Review) 22 Aug '18

22 Aug '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28271 ) Change subject: commonlib/timestamp_serialized: Add AGESA timestamp descriptions ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/28271/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28271/1//COMMIT_MSG@8 PS1, Line 8: Add an explanation of why this is needed? https://review.coreboot.org/#/c/28271/1/src/commonlib/include/commonlib/tim… File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/#/c/28271/1/src/commonlib/include/commonlib/tim… PS1, Line 263: 0x1100 Why magic numbers? All previous were part of a enum. You could use a enum here too, or you could use #define (more time consuming). As for names, TS_AGESA_xxx -- To view, visit https://review.coreboot.org/28271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib47112bdf9601bcd51b7ff7f84d948d5bb6537cf Gerrit-Change-Number: 28271 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Wed, 22 Aug 2018 16:07:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload/x86/exception: Add ability to handle user defined interrupts
by build bot (Jenkins) (Code Review) 22 Aug '18

22 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28100 ) Change subject: libpayload/x86/exception: Add ability to handle user defined interrupts ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/28100/7/payloads/libpayload/include/excepti… File payloads/libpayload/include/exception.h: https://review.coreboot.org/#/c/28100/7/payloads/libpayload/include/excepti… PS7, Line 43: void set_interrupt_handler(u8 vector, interrupt_handler); function definition argument 'interrupt_handler' should also have an identifier name -- To view, visit https://review.coreboot.org/28100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Gerrit-Change-Number: 28100 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 22 Aug 2018 15:52:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: commonlib/timestamp_serialized: Add AGESA timestamp descriptions
by Raul Rangel (Code Review) 22 Aug '18

22 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28271 Change subject: commonlib/timestamp_serialized: Add AGESA timestamp descriptions ...................................................................... commonlib/timestamp_serialized: Add AGESA timestamp descriptions BUG=b:64549506 TEST=tried cbmem -t on grunt Change-Id: Ib47112bdf9601bcd51b7ff7f84d948d5bb6537cf Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28271/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 304e43f..0b53cea 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -258,6 +258,102 @@ { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" }, { TS_FSP_AFTER_END_OF_FIRMWARE, "returning from FspNotify(EndOfFirmware)" }, + + /* AMD AGESA internal timestamps. See IdsPerf.h */ + { 0x1100, "BeginProcAmdInitEarly" }, + { 0x1101, "EndProcAmdInitEarly" }, + { 0x1102, "BeginAmdTopoInitialize" }, + { 0x1103, "EndAmdTopoInitialize" }, + { 0x1104, "BeginGnbInitAtEarlier" }, + { 0x1105, "EndGnbInitAtEarlier" }, + { 0x1106, "BeginAmdCpuEarly" }, + { 0x1107, "EndAmdCpuEarly" }, + { 0x1108, "BeginGnbInitAtEarly" }, + { 0x1109, "EndGnbInitAtEarly" }, + { 0x110A, "BeginProcAmdInitEnv" }, + { 0x110B, "EndProcAmdInitEnv" }, + { 0x110C, "BeginInitEnv" }, + { 0x110D, "EndInitEnv" }, + { 0x110E, "BeginGnbInitAtEnv" }, + { 0x110F, "EndGnbInitAtEnv" }, + { 0x1110, "BeginProcAmdInitLate" }, + { 0x1111, "EndProcAmdInitLate" }, + { 0x1112, "BeginCreatSystemTable" }, + { 0x1113, "EndCreatSystemTable" }, + { 0x1114, "BeginDispatchCpuFeaturesLate" }, + { 0x1115, "EndDispatchCpuFeaturesLate" }, + { 0x1116, "BeginAmdCpuLate" }, + { 0x1117, "EndAmdCpuLate" }, + { 0x1118, "BeginGnbInitAtLate" }, + { 0x1119, "EndGnbInitAtLate" }, + { 0x111A, "BeginProcAmdInitMid" }, + { 0x111B, "EndProcAmdInitMid" }, + { 0x111E, "BeginInitMid" }, + { 0x111F, "EndInitMid" }, + { 0x1120, "BeginGnbInitAtMid" }, + { 0x1121, "EndGnbInitAtMid" }, + { 0x1122, "BeginProcAmdInitPost" }, + { 0x1123, "EndProcAmdInitPost" }, + { 0x1124, "BeginGnbInitAtPost" }, + { 0x1125, "EndGnbInitAtPost" }, + { 0x1126, "BeginAmdMemAuto" }, + { 0x1127, "EndAmdMemAuto" }, + { 0x1128, "BeginAmdCpuPost" }, + { 0x1129, "EndAmdCpuPost" }, + { 0x112A, "BeginGnbInitAtPostAfterDram" }, + { 0x112B, "EndGnbInitAtPostAfterDram" }, + { 0x112C, "BeginProcAmdInitReset" }, + { 0x112D, "EndProcAmdInitReset" }, + { 0x112E, "BeginInitReset" }, + { 0x112F, "EndInitReset" }, + { 0x1130, "BeginHtInitReset" }, + { 0x1131, "EndHtInitReset" }, + { 0x1132, "BeginProcAmdInitResume" }, + { 0x1133, "EndProcAmdInitResume" }, + { 0x1134, "BeginAmdMemS3Resume" }, + { 0x1135, "EndAmdMemS3Resume" }, + { 0x1136, "BeginDispatchCpuFeaturesS3Resume" }, + { 0x1137, "EndDispatchCpuFeaturesS3Resume" }, + { 0x1138, "BeginSetCoresTscFreqSel" }, + { 0x1139, "EndSetCoresTscFreqSel" }, + { 0x113A, "BeginMemFMctMemClr_Init" }, + { 0x113B, "EndnMemFMctMemClr_Init" }, + { 0x113C, "BeginMemBeforeMemDataInit" }, + { 0x113D, "EndMemBeforeMemDataInit" }, + { 0x113E, "BeginProcAmdMemAuto" }, + { 0x113F, "EndProcAmdMemAuto" }, + { 0x1140, "BeginMemMFlowC32" }, + { 0x1141, "EndMemMFlowC32" }, + { 0x1142, "BeginMemInitializeMCT" }, + { 0x1143, "EndMemInitializeMCT" }, + { 0x1144, "BeginMemSystemMemoryMapping" }, + { 0x1145, "EndMemSystemMemoryMapping" }, + { 0x1146, "BeginMemDramTraining" }, + { 0x1147, "EndMemDramTraining" }, + { 0x1148, "BeginMemOtherTiming" }, + { 0x1149, "EndMemOtherTiming" }, + { 0x114A, "BeginMemUMAMemTyping" }, + { 0x114B, "EndMemUMAMemTyping" }, + { 0x114C, "BeginMemMemClr" }, + { 0x114D, "EndMemMemClr" }, + { 0x114E, "BeginMemMFlowTN" }, + { 0x114F, "EndMemMFlowTN" }, + { 0x1150, "BeginAgesaHookBeforeDramInit" }, + { 0x1151, "EndAgesaHookBeforeDramInit" }, + { 0x1152, "BeginProcMemDramTraining" }, + { 0x1153, "EndProcMemDramTraining" }, + { 0x1154, "BeginGnbInitAtRtb" }, + { 0x1155, "EndGnbInitAtRtb" }, + { 0x1156, "BeginGnbLoadScsData" }, + { 0x1157, "EndGnbLoadScsData" }, + { 0x1158, "BeginGnbPcieTraining" }, + { 0x1159, "EndGnbPcieTraining" }, + { 0x115A, "BeginDispatchCpuFeaturesInitRtb" }, + { 0x115B, "EndDispatchCpuFeaturesInitRtb" }, + { 0x115C, "BeginAmdCpuEarly" }, + { 0x115D, "EndAmdCpuEarly" }, + { 0x115E, "BeginAmdGnbMidLate" }, + { 0x115F, "EndAmdGnbMidLate" }, }; #endif -- To view, visit https://review.coreboot.org/28271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib47112bdf9601bcd51b7ff7f84d948d5bb6537cf Gerrit-Change-Number: 28271 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard
by Mario Scheithauer (Code Review) 22 Aug '18

22 Aug '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28270 Change subject: siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard ...................................................................... siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard For the 1st redesign of mc_apl1 mainboard some adjustments are necessary: - The FPGA is now connected directly via a PCIe Root Port - Internal Apollo Lake UARTs are now used - Adjusting GPIO settings Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb 2 files changed, 84 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28270/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 10eb3d3..02d0601 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -28,70 +28,70 @@ /* Southwest Community */ /* PCIE_WAKE[0:3]_N */ - PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* PCIE_WAKE0_N */ - PAD_CFG_NF(GPIO_206, UP_20K, DEEP, NF1), /* PCIE_WAKE1_N */ - PAD_CFG_NF(GPIO_207, UP_20K, DEEP, NF1), /* PCIE_WAKE2_N */ - PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1), /* PCIE_WAKE3_N */ + PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */ + PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */ + PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */ + PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */ /* EMMC interface. */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ - PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ - PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ - PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ - PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ - PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ - PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ - PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ - PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_157, NONE, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, NONE, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, NONE, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, NONE, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, NONE, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, NONE, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, NONE, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, NONE, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, NONE, DEEP, NF1), /* EMMC_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ /* SDIO -- unused */ PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ - PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), /* SDIO_D0 */ + PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ /* Configure SDIO to enable power gating. */ - PAD_CFG_GPI(GPIO_168, DN_20K, DEEP), /* SDIO_D1 */ - PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), /* SDIO_D2 */ - PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), /* SDIO_D3 */ - PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), /* SDIO_CMD */ + PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ /* SDCARD */ /* Pull down clock by 20K. */ PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ - PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ - PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ - PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ - PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + PAD_CFG_NF(GPIO_173, NONE, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, NONE, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, NONE, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, NONE, DEEP, NF1), /* SDCARD_D3 */ /* Card detect is active LOW with external pull up. */ - PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ - PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, NONE, DEEP, NF1), /* SDCARD_CMD */ /* CLK feedback, internal signal, needs 20K pull down. */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ - PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */ + PAD_CFG_GPI(GPIO_186, NONE, DEEP), /* SDCARD_LVL_WP */ /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */ /* SMBus */ - PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ - PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), /* SMB_DATA */ + PAD_CFG_GPI(SMB_ALERTB, NONE, DEEP), /* SMB_ALERT _N */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */ - PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ - PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ - PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ - PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ - PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */ - PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_GPI(LPC_CLKRUNB, NONE, DEEP), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ /* West Community */ /* I2C0 - I2C Level Shifter */ - PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ - PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ + PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */ /* I2C[1:7] -- unused */ PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */ @@ -122,10 +122,10 @@ PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ /* PCIE_CLKREQ[0:3]_N */ - PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPIO_210, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPIO_211, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPIO_212, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1), /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */ PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), @@ -136,10 +136,10 @@ PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), /* PMU Signals */ - PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ - PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */ PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ /* PMU_SLP_S0_N */ PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), @@ -156,25 +156,25 @@ PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */ PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */ /* DDI1 SDA and SCL - Display-Port */ - PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1), /* HV_DDI1_DDC_SDA */ - PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1), /* HV_DDI1_DDC_SCL */ + PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */ /* MIPI I2C -- unused */ PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */ PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */ /* Panel 0 control -- unused */ - PAD_CFG_GPI(GPIO_193, DN_20K, DEEP), /* PNL0_VDDEN */ - PAD_CFG_GPI(GPIO_194, DN_20K, DEEP), /* PNL0_BKLTEN */ - PAD_CFG_GPI(GPIO_195, DN_20K, DEEP), /* PNL0_BKLTCTL */ + PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */ /* Panel 1 control -- unused */ - PAD_CFG_NF(GPIO_196, DN_20K, DEEP, NF1), /* PNL1_VDDEN */ - PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1), /* PNL1_BKLTEN */ - PAD_CFG_NF(GPIO_198, DN_20K, DEEP, NF1), /* PNL1_BKLTCTL */ + PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ + PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ + PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ /* DDI[0:1]_HPD -- unused */ - PAD_CFG_GPI(GPIO_199, UP_20K, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ /* MDSI signals -- unused */ @@ -182,12 +182,12 @@ PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ /* USB overcurrent pins. */ - PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ - PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */ /* PMC SPI -- almost entirely unused. */ PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), - PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_NF(PMC_SPI_FS1, NONE, DEEP, NF2), /* XHPD_EDP_APL */ PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), @@ -195,16 +195,16 @@ /* PMIC Signals unused signals related to an old PMIC interface. */ PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ - PAD_CFG_GPI(PMIC_RESET_B, NONE, DEEP), /* PMIC_RESET_B */ - PAD_CFG_GPI(GPIO_213, DN_20K, DEEP), /* NFC_OUT_RESERVE */ - PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* NFC_EN */ + PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ + PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ + PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */ /* THERMTRIP_N */ PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), - PAD_CFG_GPO(PMIC_STDBY, 1, DEEP), /* unused */ - PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ - PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ - PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ + PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), /* unused */ + PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */ /* I2S1 -- unused */ PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ @@ -271,7 +271,7 @@ PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ - PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* GP_SSP_2_TXD */ + PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */ /* North Community */ @@ -296,8 +296,8 @@ PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */ PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */ - PAD_CFG_GPI(GPIO_18, UP_20K, DEEP), /* TRACE_2_CLK_VNN */ - PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* TRACE_2_DATA0_VNN */ + PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */ + PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */ PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */ PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */ PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */ @@ -311,8 +311,8 @@ PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */ PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */ - PAD_CFG_GPI(GPIO_31, DN_20K, DEEP), /* ISH_GPIO_13 */ - PAD_CFG_GPI(GPIO_32, DN_20K, DEEP), /* ISH_GPIO_14 */ + PAD_CFG_GPO(GPIO_31, 1, DEEP), /* ISH_GPIO_13 */ + PAD_CFG_GPI(GPIO_32, NONE, DEEP), /* ISH_GPIO_14 */ PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */ /* PWM[0:3] -- unused */ @@ -326,7 +326,7 @@ PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ - PAD_CFG_GPI(GPIO_42, UP_20K, DEEP), /* LPSS_UART1_RXD - unused */ + PAD_CFG_GPI(GPIO_42, NONE, DEEP), /* LPSS_UART1_RXD - unused */ PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */ PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ @@ -390,20 +390,20 @@ PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ /* SMBus */ - PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), /* SMB_DATA */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ - PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ /* LPC_CLKOUT1 - unused */ PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP), - PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ - PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ - PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ - PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ - PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */ - PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_GPI(LPC_CLKRUNB, NONE, DEEP), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ }; const struct pad_config *__weak diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 4d9c655..a273a59 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -8,7 +8,7 @@ # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "2" # FPGA register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" @@ -73,7 +73,7 @@ device pci 13.2 off end # - RP 4 - PCIe-A 2 device pci 13.3 off end # - RP 5 - PCIe-A 3 device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 off end # - RP 1 - PCIe-B 1 + device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 @@ -98,10 +98,10 @@ device pci 17.1 off end # - I2C 5 device pci 17.2 off end # - I2C 6 device pci 17.3 on end # - I2C 7 - device pci 18.0 off end # - UART 0 - device pci 18.1 off end # - UART 1 - device pci 18.2 off end # - UART 2 - device pci 18.3 off end # - UART 3 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 device pci 19.0 off end # - SPI 0 device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 -- To view, visit https://review.coreboot.org/28270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57 Gerrit-Change-Number: 28270 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: siemens/mc_apl1: Extend circuit life by clock gating and power gating
by Mario Scheithauer (Code Review) 22 Aug '18

22 Aug '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28268 to look at the new patch set (#2). Change subject: siemens/mc_apl1: Extend circuit life by clock gating and power gating ...................................................................... siemens/mc_apl1: Extend circuit life by clock gating and power gating The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/soc/intel/apollolake/include/soc/pcr_ids.h 4 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28268/2 -- To view, visit https://review.coreboot.org/28268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Gerrit-Change-Number: 28268 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl1: Move board specific things to mc_apl1 variant
by Mario Scheithauer (Code Review) 22 Aug '18

22 Aug '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28269 Change subject: siemens/mc_apl1: Move board specific things to mc_apl1 variant ...................................................................... siemens/mc_apl1: Move board specific things to mc_apl1 variant A FPGA is not necessarily available in further mc_apl1 variants. So we move the loading of the driver and the notify function to the mc_apl1 variant. Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/28269/1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 44b81dc..d0a7610 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -5,9 +5,7 @@ select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select USE_SIEMENS_HWILIB - select DRIVER_SIEMENS_NC_FPGA select APL_SKIP_SET_POWER_LIMITS - select NC_FPGA_NOTIFY_CB_READY source "src/mainboard/siemens/mc_apl1/variants/*/Kconfig" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index ae72d9e..ac10904 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -6,6 +6,8 @@ select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA select DRIVERS_UART_8250IO + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY config DEVICETREE string -- To view, visit https://review.coreboot.org/28269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268 Gerrit-Change-Number: 28269 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: siemens/mc_apl1: Extend circuit life by clock gating and power gating
by Mario Scheithauer (Code Review) 22 Aug '18

22 Aug '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28268 Change subject: siemens/mc_apl1: Extend circuit life by clock gating and power gating ...................................................................... siemens/mc_apl1: Extend circuit life by clock gating and power gating The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/soc/intel/apollolake/include/soc/pcr_ids.h 3 files changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28268/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 10eb3d3..3713683 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -84,7 +84,7 @@ PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ - PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ /* West Community */ @@ -402,7 +402,7 @@ PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ - PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ }; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index 540e322..739f6f4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -25,6 +25,11 @@ #include <baseboard/variants.h> #include <variant/ptn3460.h> +/* LPC PCR configuration */ +#define PCR_LPC_PRC 0x341c +#define PCR_LPC_CCE_EN 0xf +#define PCR_LPC_PCE_EN (9 < 8) + void variant_mainboard_final(void) { int status; @@ -39,14 +44,21 @@ else printk(BIOS_INFO, "LCD: Set up PTN was successful.\n"); - /* Enable additional I/O decoding range on LPC for COM 3 */ - lpc_open_pmio_window(0x3e8, 8); - /* * PIR6 register mapping for PCIe root ports * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# */ pcr_write16(PID_ITSS, 0x314c, 0x0321); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); } static void wait_for_legacy_dev(void *unused) diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h index f816693..878c45b 100644 --- a/src/soc/intel/apollolake/include/soc/pcr_ids.h +++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h @@ -31,6 +31,7 @@ #define PID_GPIO_N 0xC5 #define PID_ITSS 0xD0 #define PID_RTC 0xD1 +#define PID_LPC 0xD2 #define PID_AUNIT 0x4d #define PID_BUNIT 0x4c -- To view, visit https://review.coreboot.org/28268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Gerrit-Change-Number: 28268 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: device_tree/fit: Constify data structures
by Patrick Rudolph (Code Review) 22 Aug '18

22 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28267 Change subject: device_tree/fit: Constify data structures ...................................................................... device_tree/fit: Constify data structures Add const quailifier to arguments and elements. Add casts where necessary in cn81xx/soc. Tested on Cavium CN81xx EVB SFF. Change-Id: Id27966427fb97457fe883be32685d1397fb0781f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/device_tree.h M src/include/fit.h M src/lib/device_tree.c M src/lib/fit.c M src/soc/cavium/cn81xx/soc.c 5 files changed, 74 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28267/1 diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 7f725e4..ff7604a 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -50,7 +50,7 @@ struct fdt_property { const char *name; - void *data; + const void *data; uint32_t size; }; @@ -88,7 +88,7 @@ struct device_tree { - void *header; + const void *header; uint32_t header_size; struct list_node reserve_map; @@ -104,17 +104,18 @@ */ // Read the property, if any, at offset offset. -int fdt_next_property(void *blob, uint32_t offset, struct fdt_property *prop); +int fdt_next_property(const void *blob, uint32_t offset, + struct fdt_property *prop); // Read the name of the node, if any, at offset offset. -int fdt_node_name(void *blob, uint32_t offset, const char **name); +int fdt_node_name(const void *blob, uint32_t offset, const char **name); -void fdt_print_node(void *blob, uint32_t offset); -int fdt_skip_node(void *blob, uint32_t offset); +void fdt_print_node(const void *blob, uint32_t offset); +int fdt_skip_node(const void *blob, uint32_t offset); // Read a flattened device tree into a heirarchical structure which refers to // the contents of the flattened tree in place. Modifying the flat tree // invalidates the unflattened one. -struct device_tree *fdt_unflatten(void *blob); +struct device_tree *fdt_unflatten(const void *blob); @@ -123,12 +124,13 @@ */ // Figure out how big a device tree would be if it were flattened. -uint32_t dt_flat_size(struct device_tree *tree); +uint32_t dt_flat_size(const struct device_tree *tree); // Flatten a device tree into the buffer pointed to by dest. -void dt_flatten(struct device_tree *tree, void *dest); -void dt_print_node(struct device_tree_node *node); +void dt_flatten(const struct device_tree *tree, void *dest); +void dt_print_node(const struct device_tree_node *node); // Read #address-cells and #size-cells properties from a node. -void dt_read_cell_props(struct device_tree_node *node, u32 *addrcp, u32 *sizecp); +void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, + u32 *sizecp); // Look up or create a node relative to a parent node, through its path // represented as an array of strings. struct device_tree_node *dt_find_node(struct device_tree_node *parent, const char **path, @@ -148,24 +150,26 @@ struct device_tree_node *dt_find_prop_value(struct device_tree_node *parent, const char *name, void *data, size_t size); // Return the phandle -uint32_t dt_get_phandle(struct device_tree_node *node); +uint32_t dt_get_phandle(const struct device_tree_node *node); // Write src into *dest as a 'length'-byte big-endian integer. void dt_write_int(u8 *dest, u64 src, size_t length); // Delete a property void dt_delete_prop(struct device_tree_node *node, const char *name); // Add different kinds of properties to a node, or update existing ones. -void dt_add_bin_prop(struct device_tree_node *node, const char *name, void *data, - size_t size); -void dt_add_string_prop(struct device_tree_node *node, const char *name, char *str); +void dt_add_bin_prop(struct device_tree_node *node, const char *name, + const void *data, size_t size); +void dt_add_string_prop(struct device_tree_node *node, const char *name, + const char *str); void dt_add_u32_prop(struct device_tree_node *node, const char *name, u32 val); void dt_add_reg_prop(struct device_tree_node *node, u64 *addrs, u64 *sizes, int count, u32 addr_cells, u32 size_cells); int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path, void *data, size_t size, int create); -void dt_find_bin_prop(struct device_tree_node *node, const char *name, void **data, - size_t *size); -const char *dt_find_string_prop(struct device_tree_node *node, const char *name); +void dt_find_bin_prop(const struct device_tree_node *node, const char *name, + const void **data, size_t *size); +const char *dt_find_string_prop(const struct device_tree_node *node, + const char *name); /* * Fixups to apply to a kernel's device tree before booting it. diff --git a/src/include/fit.h b/src/include/fit.h index eb51b50..6e0667f 100644 --- a/src/include/fit.h +++ b/src/include/fit.h @@ -27,7 +27,7 @@ struct fit_image_node { const char *name; - void *data; + const void *data; uint32_t size; int compression; @@ -54,7 +54,7 @@ /* * Updates the cmdline in the devicetree. */ -void fit_update_chosen(struct device_tree *tree, char *cmd_line); +void fit_update_chosen(struct device_tree *tree, const char *cmd_line); /* * Add a compat string to the list of supported board ids. diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 00b36fd..8a81a0c 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -28,7 +28,8 @@ * Functions for picking apart flattened trees. */ -int fdt_next_property(void *blob, uint32_t offset, struct fdt_property *prop) +int fdt_next_property(const void *blob, uint32_t offset, + struct fdt_property *prop) { struct fdt_header *header = (struct fdt_header *)blob; uint32_t *ptr = (uint32_t *)(((uint8_t *)blob) + offset); @@ -52,7 +53,7 @@ return index * sizeof(uint32_t); } -int fdt_node_name(void *blob, uint32_t offset, const char **name) +int fdt_node_name(const void *blob, uint32_t offset, const char **name) { uint8_t *ptr = ((uint8_t *)blob) + offset; if (be32toh(*(uint32_t *)ptr) != FDT_TOKEN_BEGIN_NODE) @@ -76,7 +77,7 @@ printk(BIOS_DEBUG, " "); } -static void print_property(struct fdt_property *prop, int depth) +static void print_property(const struct fdt_property *prop, int depth) { print_indent(depth); printk(BIOS_DEBUG, "prop \"%s\" (%d bytes).\n", prop->name, prop->size); @@ -89,7 +90,7 @@ printk(BIOS_DEBUG, "\n"); } -static int print_flat_node(void *blob, uint32_t start_offset, int depth) +static int print_flat_node(const void *blob, uint32_t start_offset, int depth) { int offset = start_offset; const char *name; @@ -116,7 +117,7 @@ return offset - start_offset + sizeof(uint32_t); } -void fdt_print_node(void *blob, uint32_t offset) +void fdt_print_node(const void *blob, uint32_t offset) { print_flat_node(blob, offset, 0); } @@ -127,7 +128,7 @@ * A utility function to skip past nodes in flattened trees. */ -int fdt_skip_node(void *blob, uint32_t start_offset) +int fdt_skip_node(const void *blob, uint32_t start_offset) { int offset = start_offset; int size; @@ -171,7 +172,7 @@ return buf; } -static int fdt_unflatten_node(void *blob, uint32_t start_offset, +static int fdt_unflatten_node(const void *blob, uint32_t start_offset, struct device_tree_node **new_node) { struct list_node *last; @@ -216,12 +217,12 @@ return offset - start_offset + sizeof(uint32_t); } -static int fdt_unflatten_map_entry(void *blob, uint32_t offset, +static int fdt_unflatten_map_entry(const void *blob, uint32_t offset, struct device_tree_reserve_map_entry **new) { - uint64_t *ptr = (uint64_t *)(((uint8_t *)blob) + offset); - uint64_t start = be64toh(ptr[0]); - uint64_t size = be64toh(ptr[1]); + const uint64_t *ptr = (const uint64_t *)(((uint8_t *)blob) + offset); + const uint64_t start = be64toh(ptr[0]); + const uint64_t size = be64toh(ptr[1]); if (!size) return 0; @@ -237,10 +238,10 @@ return sizeof(uint64_t) * 2; } -struct device_tree *fdt_unflatten(void *blob) +struct device_tree *fdt_unflatten(const void *blob) { struct device_tree *tree = malloc(sizeof(*tree)); - struct fdt_header *header = (struct fdt_header *)blob; + const struct fdt_header *header = (const struct fdt_header *)blob; if (!tree) return NULL; memset(tree, 0, sizeof(*tree)); @@ -315,7 +316,7 @@ *struct_size += sizeof(uint32_t); } -uint32_t dt_flat_size(struct device_tree *tree) +uint32_t dt_flat_size(const struct device_tree *tree) { uint32_t size = tree->header_size; struct device_tree_reserve_map_entry *entry; @@ -377,8 +378,9 @@ *strings_start = dstrings; } -static void dt_flatten_node(struct device_tree_node *node, void **struct_start, - void *strings_base, void **strings_start) +static void dt_flatten_node(const struct device_tree_node *node, + void **struct_start, void *strings_base, + void **strings_start) { uint8_t *dstruct = (uint8_t *)*struct_start; uint8_t *dstrings = (uint8_t *)*strings_start; @@ -406,7 +408,7 @@ *strings_start = dstrings; } -void dt_flatten(struct device_tree *tree, void *start_dest) +void dt_flatten(const struct device_tree *tree, void *start_dest) { uint8_t *dest = (uint8_t *)start_dest; @@ -449,7 +451,7 @@ * Functions for printing a non-flattened device tree. */ -static void print_node(struct device_tree_node *node, int depth) +static void print_node(const struct device_tree_node *node, int depth) { print_indent(depth); printk(BIOS_DEBUG, "name = %s\n", node->name); @@ -463,7 +465,7 @@ print_node(child, depth + 1); } -void dt_print_node(struct device_tree_node *node) +void dt_print_node(const struct device_tree_node *node) { print_node(node, 0); } @@ -481,7 +483,8 @@ * @param addrcp Pointer to store #address-cells in, skipped if NULL. * @param sizecp Pointer to store #size-cells in, skipped if NULL. */ -void dt_read_cell_props(struct device_tree_node *node, u32 *addrcp, u32 *sizecp) +void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp, + u32 *sizecp) { struct device_tree_property *prop; list_for_each(prop, node->properties, list_node) { @@ -706,7 +709,7 @@ list_for_each(prop, parent->properties, list_node) { if (!strcmp(name, prop->prop.name)) { size_t bytes = prop->prop.size; - void *prop_data = prop->prop.data; + const void *prop_data = prop->prop.data; if (size != bytes) break; if (!memcmp(data, prop_data, size)) @@ -731,16 +734,16 @@ * @param node Pointer to node containing the phandle * @return Zero on error, the phandle on success */ -uint32_t dt_get_phandle(struct device_tree_node *node) +uint32_t dt_get_phandle(const struct device_tree_node *node) { - uint32_t *phandle; + const uint32_t *phandle; size_t len; - dt_find_bin_prop(node, "phandle", (void **)&phandle, &len); + dt_find_bin_prop(node, "phandle", (const void **)&phandle, &len); if (phandle != NULL && len == sizeof(*phandle)) return be32_to_cpu(*phandle); - dt_find_bin_prop(node, "linux,phandle", (void **)&phandle, &len); + dt_find_bin_prop(node, "linux,phandle", (const void **)&phandle, &len); if (phandle != NULL && len == sizeof(*phandle)) return be32_to_cpu(*phandle); @@ -789,7 +792,7 @@ * @param size The size of data in bytes. */ void dt_add_bin_prop(struct device_tree_node *node, const char *name, - void *data, size_t size) + const void *data, size_t size) { struct device_tree_property *prop; @@ -817,9 +820,10 @@ * @param name The name of the property. * @return The found string, or NULL. */ -const char *dt_find_string_prop(struct device_tree_node *node, const char *name) +const char *dt_find_string_prop(const struct device_tree_node *node, + const char *name) { - void *content; + const void *content; size_t size; dt_find_bin_prop(node, name, &content, &size); @@ -835,8 +839,8 @@ * @param data Pointer to return raw data blob in the property. * @param size Pointer to return the size of data in bytes. */ -void dt_find_bin_prop(struct device_tree_node *node, const char *name, - void **data, size_t *size) +void dt_find_bin_prop(const struct device_tree_node *node, const char *name, + const void **data, size_t *size) { struct device_tree_property *prop; @@ -860,7 +864,7 @@ * @param str The zero-terminated string to be stored in the property. */ void dt_add_string_prop(struct device_tree_node *node, const char *name, - char *str) + const char *str) { dt_add_bin_prop(node, name, str, strlen(str) + 1); } diff --git a/src/lib/fit.c b/src/lib/fit.c index fe8a82e..4393ae9 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -158,7 +158,7 @@ return NULL; } -static int fdt_find_compat(void *blob, uint32_t start_offset, +static int fdt_find_compat(const void *blob, uint32_t start_offset, struct fdt_property *prop) { int offset = start_offset; @@ -196,7 +196,7 @@ return -1; } -void fit_update_chosen(struct device_tree *tree, char *cmd_line) +void fit_update_chosen(struct device_tree *tree, const char *cmd_line) { const char *path[] = { "chosen", NULL }; struct device_tree_node *node; @@ -389,10 +389,12 @@ * @param fdt_blob Pointer to FDT * @param config The current config node to operate on */ -static void fit_update_compat(void *fdt_blob, struct fit_config_node *config) +static void fit_update_compat(const void *fdt_blob, + struct fit_config_node *config) { struct compat_string_entry *compat_node; - struct fdt_header *fdt_header = (struct fdt_header *)fdt_blob; + const struct fdt_header *fdt_header = + (const struct fdt_header *)fdt_blob; uint32_t fdt_offset = be32_to_cpu(fdt_header->structure_offset); size_t i = 0; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 9317fd9..e05e189 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -64,9 +64,9 @@ static void dt_platform_fixup_phy(struct device_tree_node *node, char *path, int64_t phy_address, bdk_qlm_modes_t qlm_mode) { - char *data = NULL; + const char *data = NULL; size_t size = 0; - dt_find_bin_prop(node, "qlm-mode", (void **)&data, &size); + dt_find_bin_prop(node, "qlm-mode", (const void **)&data, &size); if (!data || strncmp(data, path, 6) != 0) return; /* No key prefix match. */ @@ -127,10 +127,10 @@ static void dt_platform_fixup_mac(struct device_tree_node *node) { const char *name = "local-mac-address"; - u64 *localmac = NULL; + const u64 *localmac = NULL; size_t size = 0; - dt_find_bin_prop(node, name, (void **)&localmac, &size); + dt_find_bin_prop(node, name, (const void **)&localmac, &size); if (!localmac) return; @@ -150,8 +150,8 @@ if (*localmac) return; if (used_mac < num_free_mac_addresses) { - *localmac = next_free_mac_address + used_mac; - dt_add_bin_prop(node, name, (void *)&localmac, 6); + const u64 genmac = next_free_mac_address + used_mac; + dt_add_bin_prop(node, name, &genmac, 6); used_mac++; return; } @@ -232,9 +232,10 @@ __func__); continue; } - u32 *data = NULL; + const u32 *data = NULL; size_t size = 0; - dt_find_bin_prop(dt_node, "mmu-masters", (void **)&data, &size); + dt_find_bin_prop(dt_node, "mmu-masters", (const void **)&data, + &size); if (!size) { printk(BIOS_ERR, "%s: mmu-masters entry not found\n", __func__); -- To view, visit https://review.coreboot.org/28267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id27966427fb97457fe883be32685d1397fb0781f Gerrit-Change-Number: 28267 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: soc/cavium/cn81xx: Don't directly manipulate devicetree data
by Patrick Rudolph (Code Review) 22 Aug '18

22 Aug '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28266 Change subject: soc/cavium/cn81xx: Don't directly manipulate devicetree data ...................................................................... soc/cavium/cn81xx: Don't directly manipulate devicetree data As preparation to constify devicetree data, do it the right way. Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/soc.c 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28266/1 diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 9dbbcbf..9317fd9 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -240,12 +240,24 @@ __func__); continue; } + + u32 *data_cleaned = malloc(size); + if (!data_cleaned) + continue; + + size_t n = 0; + /* Remove phandle from mmu-masters list */ for (size_t j = 0; j < size / (sizeof(u32) * 2); j++) - if (be32_to_cpu(data[j * 2]) == phandle) { - data[j * 2] = 0; - data[j * 2 + 1] = 0; - break; + if (be32_to_cpu(data[j * 2]) != phandle) { + data_cleaned[n * 2] = data[j * 2]; + data_cleaned[n * 2 + 1] = data[j * 2 + 1]; + n++; } + + dt_add_bin_prop(dt_node, "mmu-masters", data_cleaned, + n * sizeof(u32) * 2); + + free(data_cleaned); } /* Remove QLM mode entries */ -- To view, visit https://review.coreboot.org/28266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Gerrit-Change-Number: 28266 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: drivers/net/atl1e: Add driver
by Arthur Heymans (Code Review) 22 Aug '18

22 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28265 to look at the new patch set (#3). Change subject: drivers/net/atl1e: Add driver ...................................................................... drivers/net/atl1e: Add driver Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/net/Kconfig M src/drivers/net/Makefile.inc A src/drivers/net/atl1e.c M src/mainboard/asus/p5qc/Kconfig 4 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28265/3 -- To view, visit https://review.coreboot.org/28265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f Gerrit-Change-Number: 28265 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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