coreboot-gerrit August 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sandybridge/raminit_common.c: fix printram statement
by Martin Roth (Code Review) 17 Aug '18

17 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28117 ) Change subject: sandybridge/raminit_common.c: fix printram statement ...................................................................... sandybridge/raminit_common.c: fix printram statement Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/28117 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 8 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d806066..a90b055 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -195,7 +195,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { struct cpuid_result cpures; - u32 cpu, stretch; + u32 addr, cpu, stretch; stretch = ctrl->ref_card_offset[channel]; /* ODT stretch: Delay ODT signal by stretch value. @@ -205,14 +205,17 @@ if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; - MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff, + addr = 0x401c + 0x400 * channel; + MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); - printram("OTHP Workaround [%x] = %x\n", addr, reg); + printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, + MCHBAR32(addr)); } else { // OTHP - MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff, + addr = 0x400c + 0x400 * channel; + MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); - printram("OTHP [%x] = %x\n", addr, reg); + printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } -- To view, visit https://review.coreboot.org/28117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Gerrit-Change-Number: 28117 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/grunt: Update TP/TS/H1 i2c timings
by Martin Roth (Code Review) 17 Aug '18

17 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28119 ) Change subject: google/grunt: Update TP/TS/H1 i2c timings ...................................................................... google/grunt: Update TP/TS/H1 i2c timings After adjustment on Careena EVT TP: 400.0 KHz TS: 396.8 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/28119 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 61476a2..513bd4e 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -32,22 +32,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, + .rise_time_ns = 45, .fall_time_ns = 4, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 117, - .fall_time_ns = 113, + .rise_time_ns = 67, + .fall_time_ns = 55, }" # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, + .rise_time_ns = 22, + .fall_time_ns = 19, }" device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/28119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Gerrit-Change-Number: 28119 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: x86/acpigen: Fix ACPI _ROM method
by Martin Roth (Code Review) 17 Aug '18

17 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28124 ) Change subject: x86/acpigen: Fix ACPI _ROM method ...................................................................... x86/acpigen: Fix ACPI _ROM method Fix the following Error: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 142 Line | AML source -------------------------------------------------------------------------------- 00139| 00140| Scope (\_SB.PCI0.IGFX) 00141| { 00142| Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00143| { 00144| OperationRegion (ROMS, SystemMemory, 0xCD520000, 0xFE00) 00145| Field (ROMS, AnyAcc, NoLock, Preserve) ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. Use the acpigen_write_method_serialized() to correct the error. BUG=b:112476331 TEST=Run FWTS. Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/28124 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/acpigen.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index f73ace2..e10d307 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1454,7 +1454,7 @@ ASSERT(length) /* Method (_ROM, 2, NotSerialized) */ - acpigen_write_method("_ROM", 2); + acpigen_write_method_serialized("_ROM", 2); /* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */ struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY, -- To view, visit https://review.coreboot.org/28124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Gerrit-Change-Number: 28124 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ec/google/chromeec: Fix ACPI FWTS error
by Martin Roth (Code Review) 17 Aug '18

17 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28123 ) Change subject: ec/google/chromeec: Fix ACPI FWTS error ...................................................................... ec/google/chromeec: Fix ACPI FWTS error Fix the following FWTS error: FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line 3038 Line | AML source -------------------------------------------------------------------------------- 03035| Return (One) 03036| } 03037| 03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query | ^ | Warning 3115: Not all control paths return a value (_Q09) 03039| { 03040| If (Acquire (PATM, 0x03E8)) 03041| { ================================================================================ ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths do not return a value. All control paths that return must return a value otherwise unexpected behaviour may occur. This error occurs because a branch on an conditional op-code returns a value and another does not, which is inconsistent behaviour. _Q09 is a reserved method and can't return a value. Change the logic so that no return is used and avoid this test error. BUG=b:112476331 TEST=Run FWTS. Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/28123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 12 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 94917dd..453a6d7 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -467,25 +467,23 @@ */ Method (_Q09, 0, NotSerialized) { - If (Acquire (^PATM, 1000)) { - Return () - } + If (LNot(Acquire (^PATM, 1000))) { + /* Read sensor ID for event */ + Store (^PATI, Local0) - /* Read sensor ID for event */ - Store (^PATI, Local0) - - /* When sensor ID returns 0xFF then no more events */ - While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) - { + /* When sensor ID returns 0xFF then no more events */ + While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) + { #ifdef HAVE_THERM_EVENT_HANDLER - \_SB.DPTF.TEVT (Local0) + \_SB.DPTF.TEVT (Local0) #endif - /* Keep reaading sensor ID for event */ - Store (^PATI, Local0) - } + /* Keep reaading sensor ID for event */ + Store (^PATI, Local0) + } - Release (^PATM) + Release (^PATM) + } } /* -- To view, visit https://review.coreboot.org/28123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Gerrit-Change-Number: 28123 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/kahlee: Fix ACPI method Not Serialized error
by Martin Roth (Code Review) 17 Aug '18

17 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28122 ) Change subject: mainboard/google/kahlee: Fix ACPI method Not Serialized error ...................................................................... mainboard/google/kahlee: Fix ACPI method Not Serialized error Fix the following failure from FWTS: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 131 Line | AML source -------------------------------------------------------------------------------- 00128| } 00129| } 00130| }) 00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00132| { 00133| Name (RBUF, ResourceTemplate () 00134| { ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. BUG=b:112476331 TEST= Run FWTS. Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/28122 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 28599a0..6bb41ae 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -31,7 +31,7 @@ } }) - Method (_CRS, 0x0, NotSerialized) { + Method (_CRS, 0x0, Serialized) { Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. -- To view, visit https://review.coreboot.org/28122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Gerrit-Change-Number: 28122 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Fix PCI ACPI _OSC methods
by Martin Roth (Code Review) 17 Aug '18

17 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28121 ) Change subject: Fix PCI ACPI _OSC methods ...................................................................... Fix PCI ACPI _OSC methods Fix the IASL build warnings: Object is not referenced (Name [CDW2] is within a method [_OSC]) Object is not referenced (Name [CDW3] is within a method [_OSC]) Remove the not referenced objects. They are not needed. BUG=b:112476331 TEST=IASL doesn't give the warning. Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/28121 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/northbridge/intel/i945/acpi/i945.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/fch.asl 5 files changed, 5 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 5a93238..79fb371 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -20,17 +20,13 @@ /* Operating System Capabilities Method */ Method (_OSC, 4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 0, CDW1) - CreateDWordField(Arg3, 4, CDW2) - CreateDWordField(Arg3, 8, CDW3) - /* Check for proper PCI/PCIe UUID */ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return(Arg3) } Else { + CreateDWordField(Arg3, 0, CDW1) Or(CDW1, 4, CDW1) // Unrecognized UUID, so set bit 2 to 1 Return(Arg3) } diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 2855b23..cdda503 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -22,17 +22,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index efd6a93..2bbaa25 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -20,17 +20,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 6f0826f..2dc3438 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -19,17 +19,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 2586dd4..b33a440 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -20,17 +20,13 @@ /* Operating System Capabilities Method */ Method(_OSC,4) { - // Create DWord-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3,0,CDW1) - CreateDWordField(Arg3,4,CDW2) - CreateDWordField(Arg3,8,CDW3) - /* Check for proper PCI/PCIe UUID */ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } Else { + CreateDWordField(Arg3,0,CDW1) Or(CDW1,4,CDW1) // Unrecognized UUID Return(Arg3) } -- To view, visit https://review.coreboot.org/28121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Gerrit-Change-Number: 28121 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: tint: introduce the new tint build system with checksum verification
by build bot (Jenkins) (Code Review) 17 Aug '18

17 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 7: (15 comments) https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… File payloads/external/tint/generate_core.sh: https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 38: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 40: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 54: FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 64: import_from_file $buildgcc $corescript "# Find all the required tools" "# Allow" last_line_disabled || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 70: import_from_file $buildgcc $corescript "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 86: sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 95: # Insert prepare_${package} function call between the unpack and patch operations line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/generate_cor… PS7, Line 99: sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… File payloads/external/tint/tintify_core.sh: https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 12: # <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 54: echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ]; then" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 55: echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 70: sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" $tintified line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 72: sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" $tintified line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 83: echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters https://review.coreboot.org/#/c/23856/7/payloads/external/tint/tintify_core… PS7, Line 87: echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters -- To view, visit https://review.coreboot.org/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 7 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Aug 2018 21:07:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Makefile.inc: Fix dependency tracking of fmap{_config.h, .desc}
by Elyes HAOUAS (Code Review) 17 Aug '18

17 Aug '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28198 ) Change subject: Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28198/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28198/1//COMMIT_MSG@16 PS1, Line 16: eee seemed ? -- To view, visit https://review.coreboot.org/28198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9 Gerrit-Change-Number: 28198 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 17 Aug 2018 18:47:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: arm64: Factor our common parts of romstage execution flow
by Julius Werner (Code Review) 17 Aug '18

17 Aug '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/28199 Change subject: arm64: Factor our common parts of romstage execution flow ...................................................................... arm64: Factor our common parts of romstage execution flow The romstage main() entry point on arm64 boards is usually in mainboard code, but there are a handful of lines that are always needed in there and not really mainboard specific (or chipset specific). We keep arguing every once in a while that this isn't ideal, so rather than arguing any longer let's just fix it. This patch moves the main() function into arch code with callbacks that the platform can hook into. (This approach can probably be expanded onto other architectures, so when that happens this file should move into src/lib.) Tested on Cheza and Kevin. I think the approach is straight-forward enough that we can take this without testing every board. (Note that in a few cases, this delays some platform-specific calls until after console_init() and exception_init()... since these functions don't really take that long, especially if there is no serial console configured, I don't expect this to cause any issues.) Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/Makefile.inc M src/arch/arm64/include/arch/stages.h A src/arch/arm64/romstage.c M src/mainboard/cavium/cn8100_sff_evb/romstage.c M src/mainboard/google/cheza/romstage.c M src/mainboard/google/gru/romstage.c M src/mainboard/google/kukui/romstage.c M src/mainboard/google/oak/romstage.c 8 files changed, 59 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/28199/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index e2c44eb4..6bb7196 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -107,6 +107,7 @@ romstage-y += memset.S romstage-y += memcpy.S romstage-y += memmove.S +romstage-y += romstage.c romstage-y += transition.c transition_asm.S rmodules_arm64-y += memset.S diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h index 9a88ea7..2d6d583 100644 --- a/src/arch/arm64/include/arch/stages.h +++ b/src/arch/arm64/include/arch/stages.h @@ -21,4 +21,11 @@ void stage_entry(void); +/* This function is the romstage platform entry point, and should contain all + chipset and mainboard setup until DRAM is initialized and accessible. */ +void platform_romstage_main(void); +/* This is an optional hook to run further chipset or mainboard code after DRAM + and associated support frameworks (like CBMEM) have been initialized. */ +void platform_romstage_postram(void); + #endif diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c new file mode 100644 index 0000000..8cdb16b --- /dev/null +++ b/src/arch/arm64/romstage.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/exception.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> +#include <program_loading.h> +#include <timestamp.h> + +__weak void platform_romstage_main(void) { /* no-op, for bring-up */ } +__weak void platform_romstage_postram(void) { /* no-op */ } + +void main(void) +{ + timestamp_add_now(TS_START_ROMSTAGE); + + console_init(); + exception_init(); + + platform_romstage_main(); + cbmem_initialize_empty(); + platform_romstage_postram(); + + run_ramstage(); +} diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index e8e5cd6..7bb53e3 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -14,34 +14,24 @@ * */ -#include <arch/exception.h> -#include <cbmem.h> -#include <romstage_handoff.h> +#include <arch/stages.h> #include <soc/sdram.h> #include <soc/timer.h> #include <soc/mmu.h> #include <stdlib.h> -#include <console/console.h> -#include <program_loading.h> #include <libbdk-hal/bdk-config.h> #include <string.h> extern const struct bdk_devicetree_key_value devtree[]; -void main(void) +void platform_romstage_main(void) { watchdog_poke(0); - console_init(); - exception_init(); - bdk_config_set_fdt(devtree); sdram_init(); soc_mmu_init(); watchdog_poke(0); - - cbmem_initialize_empty(); - run_ramstage(); } diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index c930016..ad85061 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -13,17 +13,8 @@ * GNU General Public License for more details. */ -#include <arch/exception.h> -#include <cbmem.h> -#include <halt.h> -#include <program_loading.h> -#include <console/console.h> -#include <timestamp.h> +#include <arch/stages.h> -void main(void) +void platform_romstage_main(void) { - console_init(); - exception_init(); - cbmem_initialize_empty(); - run_ramstage(); } diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 9f938f3..edf440d 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -14,24 +14,14 @@ * */ -#include <arch/cache.h> -#include <arch/cpu.h> -#include <arch/exception.h> #include <arch/mmu.h> -#include <cbfs.h> -#include <cbmem.h> -#include <gpio.h> -#include <console/console.h> +#include <arch/stages.h> #include <delay.h> -#include <program_loading.h> -#include <romstage_handoff.h> -#include <soc/addressmap.h> #include <soc/mmu_operations.h> #include <soc/tsadc.h> #include <soc/sdram.h> #include <symbols.h> #include <soc/usb.h> -#include <stdlib.h> #include "board.h" #include "pwm_regulator.h" @@ -70,11 +60,9 @@ reset_usb_otg1(); } -void main(void) +void platform_romstage_main(void) { - console_init(); tsadc_init(TSHUT_POL_HIGH); - exception_init(); /* Init DVS to conservative values. */ init_dvs_outputs(); @@ -87,6 +75,4 @@ mmu_config_range((void *)0, (uintptr_t)sdram_size_mb() * MiB, CACHED_MEM); mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); - cbmem_initialize_empty(); - run_ramstage(); } diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 342a0ba..9eeaa68 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -13,21 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/exception.h> -#include <console/console.h> -#include <program_loading.h> +#include <arch/stages.h> #include <soc/mmu_operations.h> -#include <timestamp.h> -void main(void) +void platform_romstage_main(void) { - timestamp_add_now(TS_START_ROMSTAGE); - - /* Init UART baudrate when PLL on. */ - console_init(); - exception_init(); - mtk_mmu_after_dram(); - - run_ramstage(); } diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index 9f5ce5f..754c40c 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -12,39 +12,21 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <arch/cache.h> -#include <arch/cpu.h> -#include <arch/exception.h> -#include <arch/io.h> -#include <arch/mmu.h> -#include <boardid.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <delay.h> -#include <program_loading.h> -#include <romstage_handoff.h> -#include <symbols.h> -#include <timer.h> -#include <timestamp.h> +#include <arch/stages.h> +#include <boardid.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6391.h> #include <soc/pll.h> #include <soc/rtc.h> +#include <timer.h> -void main(void) +void platform_romstage_main(void) { int stabilize_usec; struct stopwatch sw; - timestamp_add_now(TS_START_ROMSTAGE); - - /* init uart baudrate when pll on */ - console_init(); - exception_init(); - rtc_boot(); /* Raise CPU voltage to allow higher frequency */ @@ -64,9 +46,4 @@ mt_pll_raise_ca53_freq(1700 * MHz); mtk_mmu_after_dram(); - - /* should be called after memory init */ - cbmem_initialize_empty(); - - run_ramstage(); } -- To view, visit https://review.coreboot.org/28199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe Gerrit-Change-Number: 28199 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: Makefile.inc: Fix dependency tracking of fmap{_config.h, .desc}
by Nico Huber (Code Review) 17 Aug '18

17 Aug '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/28198 Change subject: Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} ...................................................................... Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} GNU make is too smart (or too stupid?) for empty recipes. In the case of empty recipes, GNU make doesn't consider the target as updated even if its prerequisites are. So if we told make to rebuild `build/romstage/ lib/cbfs.o` for instance, and the FMAP changed, it rerun the fmaptool recipe (as a prerequisite) but only considered `cbfs.o` to be updated by chance. Just not leaving the recipes empty seems to help here. I seeemed to remember that it wasn't that easy, but it fixes the issue for me... Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/28198/1 diff --git a/Makefile.inc b/Makefile.inc index 7ce2360..4eec58b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -950,7 +950,9 @@ # generated at the same time as fmap.fmap $(obj)/fmap_config.h: $(obj)/fmap.fmap + true $(obj)/fmap.desc: $(obj)/fmap.fmap + true $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) echo " FMAP $(FMAPTOOL) -h $(obj)/fmap_config.h $< $@" -- To view, visit https://review.coreboot.org/28198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9 Gerrit-Change-Number: 28198 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit August 2018