coreboot-gerrit August 2018

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Change in coreboot[master]: mb/google/eve: enable eist
by Matt Delco (Code Review) 15 Aug '18

15 Aug '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/28102 Change subject: mb/google/eve: enable eist ...................................................................... mb/google/eve: enable eist Enable Enhanced Intel SpeedStep (EIST) on eve. Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/28102/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 16bfc47..c1482c6 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -7,6 +7,8 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + register "eist_enable" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE -- To view, visit https://review.coreboot.org/28102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87 Gerrit-Change-Number: 28102 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: cpu/intel/common: add function to init cppc_config
by Matt Delco (Code Review) 15 Aug '18

15 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28068 to look at the new patch set (#4). Change subject: cpu/intel/common: add function to init cppc_config ...................................................................... cpu/intel/common: add function to init cppc_config This change adds a method to init a cppc_config structure in a way that should ideally work across Intel processors that support EIST. Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c 2 files changed, 188 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28068/4 -- To view, visit https://review.coreboot.org/28068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1 Gerrit-Change-Number: 28068 Gerrit-PatchSet: 4 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: src/{commonlib, lib}: Fix typo
by Martin Roth (Code Review) 15 Aug '18

15 Aug '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28097 ) Change subject: src/{commonlib,lib}: Fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Gerrit-Change-Number: 28097 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Aug 2018 18:38:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt: Remove BayHub EMMC driving strength override
by Martin Roth (Code Review) 15 Aug '18

15 Aug '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28084 ) Change subject: google/grunt: Remove BayHub EMMC driving strength override ...................................................................... google/grunt: Remove BayHub EMMC driving strength override Side effect was observed that after override BayHub EMMC driving strength to the max, EMMC CLK will be reduced to 51.x Mhz from 200 Mhz. This will cause OS installation fail on Samsung EMMC sku. BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/28084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 0 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index b1bd492..cf38b99 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -17,8 +17,6 @@ #include <baseboard/variants.h> #include <gpio.h> #include <variant/gpio.h> -#include <device/pci.h> -#include <drivers/generic/bayhub/bh720.h> uint8_t variant_board_sku(void) { @@ -37,26 +35,3 @@ gpio_set(GPIO_133, 0); } #endif - -void bh720_driving_strength(struct device *dev) -{ - u32 sdbar; - u32 bh720_pcr_data; - - sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - - /* Enable Memory Access Function */ - write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); - write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); - - /* Read current EMMC 1.8V CLK/DATA,CMD driving strength */ - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x40000304); - bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); - - /* set EMMC 1.8V CLK/DATA,CMD the max level */ - write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data | (BH720_PCR_CLK_DRV_MAX << 4) | - (BH720_PCR_DATA_CMD_DRV_MAX << 1)); - write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x80000304); -} -- To view, visit https://review.coreboot.org/28084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Gerrit-Change-Number: 28084 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: tint: introduce the new tint build system with checksum verification
by build bot (Jenkins) (Code Review) 15 Aug '18

15 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 4: (12 comments) https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… File payloads/external/tint/generate_core.sh: https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 38: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 40: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 54: FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 64: import_from_file $buildgcc $corescript "# Find all the required tools" "# Allow" last_line_disabled || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 70: import_from_file $buildgcc $corescript "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 86: sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 95: # Insert prepare_${package} function call between the unpack and patch operations line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/generate_cor… PS4, Line 99: sed -i -e "/\$TAR \$FLAGS \$(basename \$archive)/a prepare_\${package} || exit \"\$?\"" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/tintify_core… File payloads/external/tint/tintify_core.sh: https://review.coreboot.org/#/c/23856/4/payloads/external/tint/tintify_core… PS4, Line 42: echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ]; then" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/tintify_core… PS4, Line 43: echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/tintify_core… PS4, Line 61: echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters https://review.coreboot.org/#/c/23856/4/payloads/external/tint/tintify_core… PS4, Line 65: echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters -- To view, visit https://review.coreboot.org/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 4 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Aug 2018 18:19:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Makefile: Write .xcompile to $(obj)
by Raul Rangel (Code Review) 15 Aug '18

15 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28101 Change subject: Makefile: Write .xcompile to $(obj) ...................................................................... Makefile: Write .xcompile to $(obj) This file was being written to the root src directory. It is the only file being written to src while all others are being written to obj. I decided to leave .xcompile in the cleanup targets so any stale compies will get removed on clean. This is part of my incremental rebuild work. It saves a few targets from being rebuilt. BUG=b:112267918 TEST=ran emerge-grunt coreboot Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M Makefile M Makefile.inc 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/28101/1 diff --git a/Makefile b/Makefile index 1d4a488..ad4609d 100644 --- a/Makefile +++ b/Makefile @@ -142,18 +142,18 @@ # in addition to the dependency below, create the file if it doesn't exist # to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) + $(if $(wildcard $(obj)/.xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > $(obj)/.xcompile || rm -f $(obj)/.xcompile))) -.xcompile: util/xcompile/xcompile +$(obj)/.xcompile: util/xcompile/xcompile rm -f $@ $< $(XGCCPATH) > $@.tmp \mv -f $@.tmp $@ 2> /dev/null rm -f $@.tmp --include .xcompile +-include $(obj)/.xcompile ifneq ($(XCOMPILE_COMPLETE),1) -$(shell rm -f .xcompile) +$(shell rm -f $(obj)/.xcompile) $(error .xcompile deleted because it's invalid. \ Restarting the build should fix that, or explain the problem) endif diff --git a/Makefile.inc b/Makefile.inc index 7ce2360..6d60b6c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -464,7 +464,7 @@ ####################################################################### # generate build support files -$(obj)/build.h: .xcompile +$(obj)/build.h: $(obj)/.xcompile @printf " GEN build.h\n" rm -f $(obj)/build.h util/genbuild_h/genbuild_h.sh > $(obj)/build.ht -- To view, visit https://review.coreboot.org/28101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Gerrit-Change-Number: 28101 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: libpayload/x86/exception: Add ability to handle user defined interrupts
by Raul Rangel (Code Review) 15 Aug '18

15 Aug '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28100 Change subject: libpayload/x86/exception: Add ability to handle user defined interrupts ...................................................................... libpayload/x86/exception: Add ability to handle user defined interrupts I need to setup the APIC timer to fire interrupts. I would like to reuse the existing interrupt table. So I extended it to support user defined interrupts. I just added all 255 vectors so there wouldn't need to be any additional build time configuration. BUG=b:109749762 TEST=Wrote an interrupt handler and fired an APIC timer interrupt and verified that vector 32 was returned. Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/arch/x86/exception.c M payloads/libpayload/arch/x86/exception_asm.S 2 files changed, 34 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/28100/1 diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index b562660..c9ab6bf 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -161,7 +161,15 @@ void exception_dispatch(void) { u32 vec = exception_state->vector; - die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u", vec); + + /* Handle user defined vectors */ + if (vec >= 32 && vec <= 255) { + die_if(!hook || !hook(vec), + "Hook required to handle user defined vector %u\n", vec); + } + + die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u\n", + vec); if (hook && hook(vec)) return; diff --git a/payloads/libpayload/arch/x86/exception_asm.S b/payloads/libpayload/arch/x86/exception_asm.S index a8f9a1d..5bbe69e 100644 --- a/payloads/libpayload/arch/x86/exception_asm.S +++ b/payloads/libpayload/arch/x86/exception_asm.S @@ -68,6 +68,14 @@ jmp exception_common .endm + .altmacro + .macro user_defined_stubs from, to + stub \from + .if \to-\from + user_defined_stubs %(from+1),\to + .endif + .endm + stub 0 stub 1 stub 2 @@ -100,6 +108,11 @@ stub 29 stub_err 30 stub 31 + /* Split the macro so we avoid a stack overflow. */ + user_defined_stubs 32, 63 + user_defined_stubs 64, 127 + user_defined_stubs 128, 191 + user_defined_stubs 192, 255 exception_common: /* @@ -215,6 +228,14 @@ .long \target .endm + .altmacro + .macro user_defined_gates from, to + interrupt_gate exception_stub_\from + .if \to-\from + user_defined_gates %(from+1),\to + .endif + .endm + .align 8 .global idt idt: @@ -250,6 +271,10 @@ interrupt_gate exception_stub_29 interrupt_gate exception_stub_30 interrupt_gate exception_stub_31 + user_defined_gates 32, 63 + user_defined_gates 64, 127 + user_defined_gates 128, 191 + user_defined_gates 192, 255 idt_end: /* IDT pointer for use with lidt */ -- To view, visit https://review.coreboot.org/28100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c Gerrit-Change-Number: 28100 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: util/superiotool: Add Winbond W83667HG register dump
by build bot (Jenkins) (Code Review) 15 Aug '18

15 Aug '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28099 ) Change subject: util/superiotool: Add Winbond W83667HG register dump ...................................................................... Patch Set 1: (377 comments) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c File util/superiotool/winbond.c: https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@300 PS1, Line 300: {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@301 PS1, Line 301: 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@302 PS1, Line 302: {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@302 PS1, Line 302: {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@302 PS1, Line 302: {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@302 PS1, Line 302: {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@302 PS1, Line 302: {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@302 PS1, Line 302: {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, space required after that ',' (ctx:VxV) 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space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@303 PS1, Line 303: 0x00,0x00,0x7f,0x0a,0x08,0x00,MISC,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@303 PS1, Line 303: 0x00,0x00,0x7f,0x0a,0x08,0x00,MISC,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@303 PS1, Line 303: 0x00,0x00,0x7f,0x0a,0x08,0x00,MISC,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@303 PS1, Line 303: 0x00,0x00,0x7f,0x0a,0x08,0x00,MISC,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@303 PS1, Line 303: 0x00,0x00,0x7f,0x0a,0x08,0x00,MISC,EOT}}, space required after that close brace '}' https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@305 PS1, Line 305: {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@305 PS1, Line 305: {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@305 PS1, Line 305: {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@305 PS1, Line 305: {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@305 PS1, Line 305: {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@305 PS1, Line 305: {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, space required after that ',' (ctx:VxV) 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{0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@307 PS1, Line 307: {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@307 PS1, Line 307: {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@307 PS1, Line 307: {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@307 PS1, Line 307: {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@307 PS1, Line 307: {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@307 PS1, Line 307: {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@308 PS1, Line 308: EOT}}, space required after that close brace '}' https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@310 PS1, Line 310: {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@310 PS1, Line 310: {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@310 PS1, Line 310: {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@310 PS1, Line 310: {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, space required after that ',' (ctx:VxV) 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https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@365 PS1, Line 365: {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@366 PS1, Line 366: NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28099/1/util/superiotool/winbond.c@367 PS1, Line 367: NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, space required after that close brace '}' -- To view, visit https://review.coreboot.org/28099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0 Gerrit-Change-Number: 28099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Aug 2018 16:27:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/superiotool: Add Winbond W83667HG register dump
by Angel Pons (Code Review) 15 Aug '18

15 Aug '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28099 Change subject: util/superiotool: Add Winbond W83667HG register dump ...................................................................... util/superiotool: Add Winbond W83667HG register dump This SuperIO is supported by coreboot and used in two Asus boards. However, superiotool was lacking a register dump for this chip. Add the corresponding data form the datasheet into superiotool. The SuperIO's datasheet was obtained by requesting it to Nuvoton. Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/superiotool/winbond.c 1 file changed, 69 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/28099/1 diff --git a/util/superiotool/winbond.c b/util/superiotool/winbond.c index fce860d..571a2e0 100644 --- a/util/superiotool/winbond.c +++ b/util/superiotool/winbond.c @@ -296,7 +296,75 @@ {0x00,0x02,0xe8,0x03,0x00,EOT}}, {EOT}}}, {0xa51, "W83667HG", { - /* See also: http://lists.lm-sensors.org/pipermail/lm-sensors/2008-July/023683.html */ + {NOLDN, NULL, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0xb3,NANA,0xff,0x00,MISC,0x00,MISC,0xff,0x20, + 0x00,0x00,0x7f,0x0a,0x08,0x00,MISC,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, + EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, + EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x2, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x3, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}}, + {0x6, "Serial peripheral interface", + {0x30,0x62,0x63,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x7, "GPIO 6, GPIO 7, GPIO 8, GPIO 9", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xea,0xeb,0xec,0xed,0xee,0xf4,0xf5,0xf6,0xf7, + 0xf8,EOT}, + {0x18,0xff,0x00,0x00,0x00,0xef,0x00,0x00,0x00,0xff, + 0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,EOT}}, + {0x8, "WDTO#, GPIO 1", + {0x30,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xea,0xeb,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, + 0xf7,0xfe,EOT}, + {0x05,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00, + 0x00,0x00,EOT}}, + {0xa, "ACPI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9, + 0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,0xff,EOT}, + {0x01,0x00,0xff,0x00,0x00,0x02,0x1c,0x00,RSVD,0x00, + 0x7c,0x00,0x00,0x00,0x00,0x00,0x30,EOT}}, + {0xb, "Hardware monitor, SB-TSI", + {0x30,0x60,0x61,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0, + 0xf5,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC1, + 0x10,EOT}}, + {0xc, "PECI", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe8,0xe9,0xea, + 0xec,0xee,0xef,0xf1,0xf2,0xf3,0xfe,0xff,EOT}, + {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x00,RSVD,0x00, + 0x00,0x01,0x5a,0x48,0x50,0x10,0x80,0x01,EOT}}, + {0xd, "VID", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xec, + 0xed,0xee,0xef,0xf3,EOT}, + {0x00,0x00,NANA,NANA,0x07,RSVD,RSVD,RSVD,RSVD,0x01, + RSVD,0x88,0x00,0x04,EOT}}, + {0xf, "GPIO Push-Pull or Open-Drain selection", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9, + 0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9, + 0xfa,0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0xff,0xff,0xfd,0xff,0xf7,0xcb,0x3f,0xff,0xff,0x00, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, {0xb07, "W83627DHG-P/-PT", { {NOLDN, NULL, -- To view, visit https://review.coreboot.org/28099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0 Gerrit-Change-Number: 28099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp
by Charles Marslett (Code Review) 15 Aug '18

15 Aug '18

Charles Marslett has abandoned this change. ( https://review.coreboot.org/27681 ) Change subject: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp ...................................................................... Abandoned Duplicate of patch set 27619 -- To view, visit https://review.coreboot.org/27681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Gerrit-Change-Number: 27681 Gerrit-PatchSet: 3 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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