coreboot-gerrit March 2018

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Change in coreboot[master]: security/vboot: Add boot mode selection
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23756 ) Change subject: security/vboot: Add boot mode selection ...................................................................... Patch Set 24: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22587/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68135/ : SUCCESS -- To view, visit https://review.coreboot.org/23756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43d233d5a8766af2dd7f07cc0b64293a80d5d7d2 Gerrit-Change-Number: 23756 Gerrit-PatchSet: 24 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 01:37:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/x86/mp_init: Increase AP check-in timeout to 1second
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24965 ) Change subject: cpu/x86/mp_init: Increase AP check-in timeout to 1second ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22584/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68132/ : SUCCESS -- To view, visit https://review.coreboot.org/24965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff Gerrit-Change-Number: 24965 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 01:27:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: lib: Add delay.c to smm
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24963 ) Change subject: lib: Add delay.c to smm ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22585/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68134/ : SUCCESS -- To view, visit https://review.coreboot.org/24963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20 Gerrit-Change-Number: 24963 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 01:20:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block/smm: Add delay(configurable) before entering S5
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24964 ) Change subject: soc/intel/common/block/smm: Add delay(configurable) before entering S5 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22586/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68133/ : SUCCESS -- To view, visit https://review.coreboot.org/24964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Gerrit-Change-Number: 24964 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 01:16:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/x86/mp_init: Increase AP check-in timeout to 1second
by Furquan Shaikh (Code Review) 02 Mar '18

02 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/24965 Change subject: cpu/x86/mp_init: Increase AP check-in timeout to 1second ...................................................................... cpu/x86/mp_init: Increase AP check-in timeout to 1second Currently, the AP check-in timeout in bsp_do_flight_plan is set to 100ms. However, as the number of APs increases, contention could increase especially for resource like UART. This led to MP record timeout issues on KBL platform with 7 APs and serial-console enabled BIOS image. This change increases the timeout value to 1 second to be on the safer side and let APs check-in before continuing boot. BUG=b:74085891 TEST=Verified that MP record timeout is not observed anymore on Nami. Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/cpu/x86/mp_init.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/24965/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 92eb722..06e30b6 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -539,7 +539,12 @@ { int i; int ret = 0; - const int timeout_us = 100000; + /* + * Set timeout to wait for APs to a huge value (=1 second) since it + * could take a longer time for APs to check-in as the number of APs + * increases (contention for resources like UART also increases). + */ + const int timeout_us = 1000000; const int step_us = 100; int num_aps = mp_params->num_cpus - 1; -- To view, visit https://review.coreboot.org/24965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff Gerrit-Change-Number: 24965 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common/block/smm: Add delay(configurable) before entering S5
by Furquan Shaikh (Code Review) 02 Mar '18

02 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/24964 Change subject: soc/intel/common/block/smm: Add delay(configurable) before entering S5 ...................................................................... soc/intel/common/block/smm: Add delay(configurable) before entering S5 This change adds a configurable delay in milliseconds before SLP_EN is set in SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power button SMIs. On some platforms (Nami, Nautilus), it was observed that power button SMI triggered by EC was competing with the SLP SMI triggered by keyboard driver. Keyboard driver indicated power button press which resulted in depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power button press also causes the EC to send a pulse on PWRBTN# line, which is debounced for 16ms before an interrupt is triggered. This interrupt was generated after SLP_SMI is processed which resulted in the device waking back up from S5. This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay before SLP_EN is set for S5. This change should only affect CHROMEOS boards as the config option will be 0 in other cases. BUG=b:74083107 TEST=Verified that nami, nautilus do not wake back from S5 on power button press at dev mode screen. Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/24964/1 diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 0355780..909382e 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -7,3 +7,12 @@ bool help Intel Processor trap flag if it is supported + +config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS + int + default 100 if CHROMEOS + default 0 + help + Time in milliseconds that SLP_SMI for S5 waits for before + enabling sleep. This is required to avoid any race between + SLP_SMI and PWRBTN SMI. diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 81ff3eb..fc908c2 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#include <delay.h> #include <device/pci_def.h> #include <elog.h> #include <intelblocks/fast_spi.h> @@ -219,6 +220,10 @@ pmc_soc_restore_power_failure(); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); + + mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS); + pmc_clear_pm1_status(); + break; default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); -- To view, visit https://review.coreboot.org/24964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Gerrit-Change-Number: 24964 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: lib: Add delay.c to smm
by Furquan Shaikh (Code Review) 02 Mar '18

02 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/24963 Change subject: lib: Add delay.c to smm ...................................................................... lib: Add delay.c to smm BUG=b:74083107 Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/lib/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/24963/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 3ddf017..960b5cb 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -175,6 +175,7 @@ ramstage-y += boot_device.c smm-y += boot_device.c +smm-y += delay.c smm-y += fmap.c smm-y += cbfs.c memcmp.c smm-$(CONFIG_GENERIC_UDELAY) += timer.c -- To view, visit https://review.coreboot.org/24963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20 Gerrit-Change-Number: 24963 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: enable SAR power
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24962 ) Change subject: mainboard/google/zoombini/variants/meowth: enable SAR power ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22583/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68131/ : SUCCESS -- To view, visit https://review.coreboot.org/24962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72 Gerrit-Change-Number: 24962 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 00:28:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: enable SAR power
by Nick Vaccaro (Code Review) 02 Mar '18

02 Mar '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/24962 Change subject: mainboard/google/zoombini/variants/meowth: enable SAR power ...................................................................... mainboard/google/zoombini/variants/meowth: enable SAR power BUG=b:69011806 BRANCH=master TEST=none Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/zoombini/variants/meowth/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/24962/1 diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index 3e6b4a2..78cab5a 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -89,7 +89,7 @@ /* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* PCH_SAR1_INT_L */ /* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* PCH_SAR0_INT_L */ /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* GPP_C5_STRAP */ -/* SM1CLK */ PAD_CFG_GPO(GPP_C6, 0, DEEP), /* PCH_SAR_PWR_EN */ +/* SM1CLK */ PAD_CFG_GPO(GPP_C6, 1, DEEP), /* PCH_SAR_PWR_EN */ /* SM1DATA */ PAD_NC(GPP_C7, NONE), /* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART_PCH_RX_DEBUG_TX */ -- To view, visit https://review.coreboot.org/24962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72 Gerrit-Change-Number: 24962 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: mb/google/octopus: Add device tree settings
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23846 ) Change subject: mb/google/octopus: Add device tree settings ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22582/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68130/ : SUCCESS -- To view, visit https://review.coreboot.org/23846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Gerrit-Change-Number: 23846 Gerrit-PatchSet: 9 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 00:20:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018