coreboot-gerrit March 2018

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68129/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22581/ : SUCCESS -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 23:52:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68128/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22580/ : SUCCESS -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 23:39:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68127/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22579/ : SUCCESS -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 23:01:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Add gpio configs for communities
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23799 ) Change subject: mb/google/octopus: Add gpio configs for communities ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22578/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68126/ : SUCCESS -- To view, visit https://review.coreboot.org/23799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Gerrit-Change-Number: 23799 Gerrit-PatchSet: 10 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 22:56:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68125/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22577/ : SUCCESS -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 22:09:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by Philipp Deppenwiese (Code Review) 01 Mar '18

01 Mar '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24942 to look at the new patch set (#2). Change subject: WIP / lib: Add blob_provider interface ...................................................................... WIP / lib: Add blob_provider interface * Add automated functions for blob mapping and region device retrival. * Add hook function for region device access. * Provide defines for easy usage. * Add TPM measurements through hook function. Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/cpu/amd/microcode/microcode.c M src/cpu/intel/microcode/microcode.c M src/cpu/via/nano/update_ucode.c M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_1/vbt.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/drivers/siemens/nc_fpga/nc_fpga.c A src/include/blob_provider.h M src/lib/Makefile.inc A src/lib/blob_provider.c M src/lib/coreboot_table.c M src/lib/spd_bin.c M src/mainboard/amd/serengeti_cheetah/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/chell/spd/spd.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/lars/spd/spd.c M src/mainboard/google/link/romstage.c M src/mainboard/google/poppy/romstage.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/urara/boardid.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/intel/harcuvar/spd/spd.c M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/iwill/dk8_htx/acpi_tables.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/intel/common/mrc_cache.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/security/vboot/secdata_measurements.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/psp/psp.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/common/mma.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c M src/soc/intel/quark/romstage/romstage.c M src/soc/nvidia/tegra210/mtc.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/vendorcode/siemens/hwilib/hwilib.c M src/vendorcode/siemens/hwilib/hwilib.h 78 files changed, 622 insertions(+), 279 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/24942/2 -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68122/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22574/ : SUCCESS -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 20:52:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: WIP / lib: Add blob_provider interface
by Philipp Deppenwiese (Code Review) 01 Mar '18

01 Mar '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/24942 Change subject: WIP / lib: Add blob_provider interface ...................................................................... WIP / lib: Add blob_provider interface * Add automated functions for blob mapping and region device retrival. * Add hook function for region device access. * Provide defines for easy usage. * Add TPM measurements through hook function. Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Signed-off-by: zaolin <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/cpu/amd/microcode/microcode.c M src/cpu/intel/microcode/microcode.c M src/cpu/via/nano/update_ucode.c M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_1/vbt.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/drivers/siemens/nc_fpga/nc_fpga.c A src/include/blob_provider.h M src/lib/Makefile.inc A src/lib/blob_provider.c M src/lib/coreboot_table.c M src/lib/spd_bin.c M src/mainboard/amd/serengeti_cheetah/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/chell/spd/spd.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/lars/spd/spd.c M src/mainboard/google/link/romstage.c M src/mainboard/google/poppy/romstage.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/urara/boardid.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/intel/harcuvar/spd/spd.c M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/iwill/dk8_htx/acpi_tables.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/intel/common/mrc_cache.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/security/vboot/secdata_measurements.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/psp/psp.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/common/mma.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c M src/soc/intel/quark/romstage/romstage.c M src/soc/nvidia/tegra210/mtc.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/vendorcode/siemens/hwilib/hwilib.c M src/vendorcode/siemens/hwilib/hwilib.h 78 files changed, 619 insertions(+), 277 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/24942/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 601b6f0..e5e6483 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -47,6 +47,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> +#include <blob_provider.h> u8 acpi_checksum(u8 *table, u32 length) { @@ -1004,9 +1005,7 @@ if (fw) return fw; - dsdt_file = cbfs_boot_map_with_leak( - CONFIG_CBFS_PREFIX "/dsdt.aml", - CBFS_TYPE_RAW, &dsdt_size); + dsdt_file = blob_provide_map(BLOB_DATA_ACPI_DSDT, NULL, &dsdt_size); if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current; @@ -1019,8 +1018,7 @@ return current; } - slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic", - CBFS_TYPE_RAW, &slic_size); + slic_file = blob_provide_map(BLOB_DATA_ACPI_SLIC, NULL, &slic_size); if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index ec7e733..c7ec49e 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -203,7 +203,7 @@ spin_lock(romstage_microcode_cbfs_lock()); #endif #endif - + // TODO FIX ME BLOB ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 59c3b8a..a37a84e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -21,6 +21,7 @@ #if !defined(__ROMCC__) #include <cbfs.h> #include <console/console.h> +#include <blob_provider.h> #else #include <arch/cbfs.h> #endif @@ -131,9 +132,8 @@ ucode_updates = CBFS_SUBHEADER(microcode_file); microcode_len = ntohl(microcode_file->len); #else - ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE, - &microcode_len); + ucode_updates = + blob_provide_map(BLOB_DATA_MICROCODE, NULL, &microcode_len); if (ucode_updates == NULL) return NULL; #endif diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 9ff66e7..d2d93c2 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -21,6 +21,7 @@ #include <cpu/cpu.h> #include <arch/cpu.h> #include <cbfs.h> +#include <blob_provider.h> static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) { @@ -107,8 +108,7 @@ u32 *ucode_data; size_t ucode_len; - ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &ucode_len); + ucode_data = blob_provide_map(BLOB_DATA_MICROCODE, NULL, &ucode_len); /* Oops, did you forget to include the microcode ? */ if (ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index d9fac36..7630333 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -30,6 +30,7 @@ #include <pc80/i8254.h> #include <string.h> #include <vbe.h> +#include <blob_provider.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> @@ -270,9 +271,8 @@ vbe_set_mode(&mode_info); #if IS_ENABLED(CONFIG_BOOTSPLASH) struct jpeg_decdata *decdata; - unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); + unsigned char *jpeg = + blob_provide_map(BLOB_DATA_BOOTSPLASH, NULL, NULL); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 876df23..7f6f77e 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -58,6 +58,7 @@ #include "../../src/lib/jpeg.h" #include <vbe.h> +#include <blob_provider.h> // pointer to VBEInfoBuffer, set by vbe_prepare u8 *vbe_info_buffer = 0; @@ -745,9 +746,8 @@ * cares. */ // int imagesize = 1024*768*2; - unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); + unsigned char *jpeg = + blob_provide_map(BLOB_DATA_BOOTSPLASH, NULL, NULL); if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 21530a1..867acd7 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -149,6 +149,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + // TODO FIX ME BLOB pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( "pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM, NULL); diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index fdd2e6e..970e1ab 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -27,6 +27,8 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include <blob_provider.h> + #include "AMD.h" #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_OPENSOURCE) @@ -45,8 +47,7 @@ const void *agesa, *image; size_t file_size; - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); + agesa = blob_provide_map(BLOB_CODE_AMD_AGESA, NULL, &file_size); if (agesa == NULL) return; diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 906b356..2d08b17 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -27,6 +27,7 @@ #include <spi_flash.h> #include <lib.h> // hexdump #include "fsp_util.h" +#include <blob_provider.h> /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(void *p) { @@ -58,18 +59,12 @@ size_t region_size; if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) { - struct region_device rdev; - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - *mrc_region_ptr = rdev_mmap_full(&rdev); - return region_device_sz(&rdev); - } - *mrc_region_ptr = NULL; - return 0; + *mrc_region_ptr = blob_provide_map(BLOB_DATA_MRC_CACHE_REGION, + NULL, &region_size); + return region_size; } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); - + *mrc_region_ptr = + blob_provide_map(BLOB_DATA_MRC_CACHE, NULL, &region_size); return region_size; } } diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 92a4c91..6412541 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -20,6 +20,7 @@ #include <fsp/gop.h> #include <fsp/ramstage.h> #include <fsp/util.h> +#include <blob_provider.h> /* Reading VBT table from flash */ const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) @@ -31,7 +32,7 @@ } vbt; /* Locate the vbt file in cbfs */ - vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, &vbt_size); + vbt.data = blob_provide_map(BLOB_DATA_VGA_VBT, NULL, &vbt_size); if (!vbt.data) { printk(BIOS_INFO, "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 3dafa00..3a6c1ad 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,6 +34,7 @@ #include <security/vboot/vboot_common.h> #include <vb2_api.h> #include <fsp/memory_init.h> +#include <blob_provider.h> __attribute__((weak)) void mrc_cache_update_hash(const uint8_t *data, size_t size) @@ -359,21 +360,15 @@ { struct fsp_header hdr; enum cb_err status; - struct cbfsf file_desc; - struct region_device file_data; - const char *name = CONFIG_FSP_M_CBFS; + struct region_device fspm; struct memranges memmap; struct range_entry freeranges[2]; if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); - if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + if (blob_provide_rd(BLOB_CODE_INTEL_FSP_M, &fspm)) die("FSPM not available!\n"); - } - - cbfs_file_data(&file_data, &file_desc); /* Build up memory map of romstage address space including CAR. */ memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); @@ -382,9 +377,9 @@ memranges_insert(&memmap, (uintptr_t)_program, _program_size, 0); if (!IS_ENABLED(CONFIG_FSP_M_XIP)) - status = load_fspm_mem(&hdr, &file_data, &memmap); + status = load_fspm_mem(&hdr, &fspm, &memmap); else - status = load_fspm_xip(&hdr, &file_data); + status = load_fspm_xip(&hdr, &fspm); if (status != CB_SUCCESS) die("Loading FSPM failed!\n"); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index bda88d1..b268616 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -84,6 +84,7 @@ return; } + // TODO FIX ME BLOB if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); die("FSPS not available!\n"); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 6b3a999..c796ba5 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -18,24 +18,19 @@ #include <string.h> #include <timestamp.h> #include <cbfs.h> +#include <blob_provider.h> void fsp_temp_ram_exit(void) { struct fsp_header hdr; uint32_t status; temp_ram_exit_fn temp_ram_exit; - struct cbfsf file_desc; - struct region_device file_data; - const char *name = CONFIG_FSP_M_CBFS; + struct region_device fsps; - if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); - die("FSPM not available for CAR Exit!\n"); - } + if (blob_provide_rd(BLOB_CODE_INTEL_FSP_S, &fsps)) + die("FSPS not available!\n"); - cbfs_file_data(&file_data, &file_desc); - - if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + if (fsp_validate_component(&hdr, &fsps) != CB_SUCCESS) die("Invalid FSPM header!\n"); temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 928b403..83ad33e 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -28,6 +28,7 @@ #include <cbfs.h> #include <security/vboot/vbnv.h> #include <security/vboot/vbnv_layout.h> +#include <blob_provider.h> /* There's no way around this include guard. option_table.h is autogenerated */ #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) @@ -256,8 +257,7 @@ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct = cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + ct = blob_provide_map(BLOB_DATA_NVRAM_CMOS_LAYOUT, NULL, NULL); if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); @@ -359,8 +359,7 @@ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct = cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + ct = blob_provide_map(BLOB_DATA_NVRAM_CMOS_LAYOUT, NULL, NULL); if (!ct) { printk(BIOS_ERR, "cmos_layout.bin could not be found. " "Options are disabled\n"); diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index c5cd86c..5a86fd7 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -16,6 +16,7 @@ #include <arch/cbfs.h> #else #include <cbfs.h> +#include <blob_provider.h> #endif #include <pc80/mc146818rtc.h> #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) @@ -63,8 +64,8 @@ #ifdef __ROMCC__ walkcbfs("cmos.default"); #else - cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); + blob_provide_map(BLOB_DATA_NVRAM_CMOS_DEFAULT, NULL, + &length); #endif if (cmos_default) { int i; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 41b79a6..7f20a7f 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -118,7 +118,7 @@ set the FW_DONE bit before jumping to payload. */ nc_fpga_bar0 = bar0_ptr; /* Open hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return; /* Set up FAN controller and temperature monitor according to */ /* capability bits. */ diff --git a/src/include/blob_provider.h b/src/include/blob_provider.h new file mode 100644 index 0000000..a8a7fe4 --- /dev/null +++ b/src/include/blob_provider.h @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BLOB_PROVIDER_H_ +#define _BLOB_PROVIDER_H_ + +#include <types.h> +#include <stddef.h> +#include <cbfs.h> +#include <region.h> + +typedef struct { + uint32_t id; + const char *fmap_name; + const char *cbfs_name; + uint32_t cbfs_type; +} blob_locator; + +enum { + ID_DATA_BOOTSPLASH = 0, + ID_DATA_ACPI_SLIC = 1, + ID_DATA_ACPI_DSDT = 2, + ID_DATA_ACPI_SSDT = 3, + ID_DATA_MICROCODE = 4, + ID_DATA_MICROCODE_RMU = 5, + ID_DATA_MRC_CACHE = 6, + ID_DATA_VGA_VBT = 7, + ID_DATA_NVRAM_CMOS_LAYOUT = 8, + ID_DATA_NVRAM_CMOS_DEFAULT = 9, + ID_DATA_NVRAM_VPD = 10, + ID_DATA_SIEMENS_HWLIB = 11, + ID_DATA_SPD = 12, + ID_DATA_MAC = 13, + ID_DATA_AMD_S3NV = 14, + ID_DATA_MRC_CACHE_REGION = 15, + ID_DATA_NVRAM_VPD_RO_REGION = 16, + ID_CODE_AMD_AGESA = 51, + ID_CODE_AMD_AGESA_PRE_MEM = 52, + ID_CODE_AMD_AGESA_POST_MEM = 53, + ID_CODE_AMD_PSP = 54, + ID_CODE_INTEL_MRC = 55, + ID_CODE_INTEL_FSP_S = 56, + ID_CODE_INTEL_FSP_M = 57, + ID_CODE_INTEL_MMA = 58, + ID_CODE_NVIDIA_MTC = 59, + ID_CODE_QUALCOMM_CDT = 60, + ID_CODE_QUALCOMM_DDR = 61, + ID_CODE_QUALCOMM_TZ = 61, + ID_CODE_QUALCOMM_RPM = 63, +}; + +#define DATA_CODE_SPLIT 50 + +/********************************AUTO_MODE********************************/ + +/* Excluded blobs +VGA option roms +Intel NHLT blobs +*/ + +// Data Section +#define BLOB_DATA_BOOTSPLASH \ +((blob_locator) {.id = ID_DATA_BOOTSPLASH, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "bootsplash.jpg", \ + .cbfs_type = CBFS_TYPE_BOOTSPLASH}) +#define BLOB_DATA_ACPI_SLIC \ +((blob_locator) {.id = ID_DATA_ACPI_SLIC, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = CONFIG_CBFS_PREFIX "/slic", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_ACPI_DSDT \ +((blob_locator) {.id = ID_DATA_ACPI_DSDT, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = CONFIG_CBFS_PREFIX "/dsdt.aml", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_ACPI_SSDT \ +((blob_locator) {.id = ID_DATA_ACPI_SSDT, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = CONFIG_CBFS_PREFIX "/ssdt.aml", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_MICROCODE \ +((blob_locator) {.id = ID_DATA_MICROCODE, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "cpu_microcode_blob.bin", \ + .cbfs_type = CBFS_TYPE_MICROCODE}) +#define BLOB_DATA_MICROCODE_RMU \ +((blob_locator) {.id = ID_DATA_MICROCODE_RMU, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "rmu.bin", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_MRC_CACHE \ +((blob_locator) {.id = ID_DATA_MRC_CACHE, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "mrc.cache", \ + .cbfs_type = CBFS_TYPE_MRC_CACHE}) +#define BLOB_DATA_MRC_CACHE_REGION \ +((blob_locator) {.id = ID_DATA_MRC_CACHE, \ + .fmap_name = "RW_MRC_CACHE", \ + .cbfs_name = "", \ + .cbfs_type = NULL}) +#define BLOB_DATA_VGA_VBT \ +((blob_locator) {.id = ID_DATA_VGA_VBT, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "vbt.bin", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_NVRAM_CMOS_LAYOUT \ +((blob_locator) {.id = ID_DATA_NVRAM_CMOS_LAYOUT, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "cmos_layout.bin", \ + .cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT}) +#define BLOB_DATA_NVRAM_CMOS_DEFAULT \ +((blob_locator) {.id = ID_DATA_NVRAM_CMOS_DEFAULT, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "cmos.default", \ + .cbfs_type = CBFS_COMPONENT_CMOS_DEFAULT}) +#define BLOB_DATA_NVRAM_VPD \ +((blob_locator) {.id = ID_DATA_NVRAM_VPD, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "vpd.bin", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_NVRAM_VPD_RO_REGION \ +((blob_locator) {.id = ID_DATA_NVRAM_VPD_RO_REGION, \ + .fmap_name = "RO_VPD", \ + .cbfs_name = "", \ + .cbfs_type = NULL}) +#define BLOB_DATA_SIEMENS_HWLIB \ +((blob_locator) {.id = ID_DATA_SIEMENS_HWLIB, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "hwinfo.hex", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_SPD \ +((blob_locator) {.id = ID_DATA_SPD, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "spd.bin", \ + .cbfs_type = CBFS_TYPE_SPD}) +#define BLOB_DATA_MAC \ +((blob_locator) {.id = ID_DATA_MAC, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "macaddress", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_DATA_AMD_S3NV \ +((blob_locator) {.id = ID_DATA_AMD_S3NV, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "s3nv", \ + .cbfs_type = CBFS_TYPE_RAW}) + +// Code Section +#define BLOB_CODE_AMD_AGESA \ +((blob_locator) {.id = ID_CODE_AMD_AGESA, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "AGESA", \ + .cbfs_type = CBFS_TYPE_STAGE}) +#define BLOB_CODE_AMD_AGESA_PRE_MEM \ +((blob_locator) {.id = ID_CODE_AMD_AGESA_PRE_MEM, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "AGESA_PRE_MEM", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_AMD_AGESA_POST_MEM \ +((blob_locator) {.id = ID_CODE_AMD_AGESA_POST_MEM, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "AGESA_POST_MEM", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_AMD_PSP \ +((blob_locator) {.id = ID_CODE_AMD_PSP, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "smu_fw", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_INTEL_MRC \ +((blob_locator) {.id = ID_CODE_INTEL_MRC, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "mrc.bin", \ + .cbfs_type = CBFS_TYPE_MRC}) +#define BLOB_CODE_INTEL_FSP_S \ +((blob_locator) {.id = ID_CODE_INTEL_FSP_S, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "fsps.bin", \ + .cbfs_type = CBFS_TYPE_FSP}) +#define BLOB_CODE_INTEL_FSP_M \ +((blob_locator) {.id = ID_CODE_INTEL_FSP_M, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "fspm.bin", \ + .cbfs_type = CBFS_TYPE_FSP}) +#define BLOB_CODE_INTEL_MMA \ +((blob_locator) {.id = ID_CODE_INTEL_MMA, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "mma_test_metadata.bin", \ + .cbfs_type = CBFS_TYPE_MMA}) +#define BLOB_CODE_NVIDIA_MTC \ +((blob_locator) {.id = ID_CODE_NVIDIA_MTC, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "tegra_mtc.bin", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_QUALCOMM_CDT \ +((blob_locator) {.id = ID_CODE_QUALCOMM_CDT, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "cdt.mbn", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_QUALCOMM_DDR \ +((blob_locator) {.id = ID_CODE_QUALCOMM_DDR, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "ddr.mbn", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_QUALCOMM_TZ \ +((blob_locator) {.id = ID_CODE_QUALCOMM_TZ, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "tz.mbn", \ + .cbfs_type = CBFS_TYPE_RAW}) +#define BLOB_CODE_QUALCOMM_RPM \ +((blob_locator) {.id = ID_CODE_QUALCOMM_RPM, \ + .fmap_name = "COREBOOT", \ + .cbfs_name = "rpm.mbn", \ + .cbfs_type = CBFS_TYPE_RAW}) + +/* unused +#define BLOB_CODE_INTEL_FSP +{ .cbfs_name = "fsp.bin", .cbfs_type = CBFS_TYPE_FSP } +#define BLOB_CODE_INTEL_EFI +{ .cbfs_name = "", .cbfs_type = CBFS_TYPE_EFI } +*/ + +typedef uint32_t (*check_blob_header)(const struct region_device *data); + +void *blob_provide_map(blob_locator locator, check_blob_header check_header, + size_t *size); +uint32_t blob_provide_rd(blob_locator locator, struct region_device *data); + +/********************************AUTO_MODE********************************/ + +void *blob_provide_map_cli(const char *fmap_name, const char *cbfs_name, + uint32_t cbfs_type, size_t *size); +uint32_t blob_provide_rd_cli(const char *fmap_name, const char *cbfs_name, + uint32_t cbfs_type, struct region_device *data); + +uint32_t hook_region_device(uint32_t id, const char *fmap_name, + const char *cbfs_name, uint32_t cbfs_type, + const struct region_device *data); + +#endif /* _BLOB_PROVIDER_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d77884c..58b9bea 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -223,6 +223,12 @@ ramstage-y += reset.c smm-y += reset.c +bootblock-y += blob_provider.c +verstage-y += blob_provider.c +romstage-y += blob_provider.c +postcar-y += blob_provider.c +ramstage-y += blob_provider.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c diff --git a/src/lib/blob_provider.c b/src/lib/blob_provider.c new file mode 100644 index 0000000..88831fb --- /dev/null +++ b/src/lib/blob_provider.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <blob_provider.h> +#include <console/console.h> +#include <fmap.h> + +uint32_t __attribute__((weak)) +hook_region_device(uint32_t id, const char *fmap_name, const char *cbfs_name, + uint32_t cbfs_type, const struct region_device *data) +{ + return 0; +} + +void *blob_provide_map(blob_locator locator, check_blob_header check_header, + size_t *size) +{ + blob_locator CBFS_SEARCH = locator; + struct region_device data; + struct cbfsf file; + + // default initialize + if (size) + *size = 0; + + if (CBFS_SEARCH.id > DATA_CODE_SPLIT) { + printk(BIOS_ERR, "Can't use auto mmap function on code blob."); + return NULL; + } + + switch (CBFS_SEARCH.id) { + case ID_DATA_MRC_CACHE_REGION: + case ID_DATA_NVRAM_VPD_RO_REGION: + // Locate cbfs file in fmap region + if (fmap_locate_area_as_rdev(CBFS_SEARCH.fmap_name, &data)) { + printk(BIOS_ERR, "Could not locate FMAP partition %s\n", + CBFS_SEARCH.fmap_name); + return NULL; + } + break; + default: + // Locate cbfs file in fmap region + if (cbfs_locate_file_in_region(&file, CBFS_SEARCH.fmap_name, + CBFS_SEARCH.cbfs_name, + &CBFS_SEARCH.cbfs_type) < 0) { + printk(BIOS_ERR, + "Could not locate %s key in CBFS on FMAP " + "partition %s " + "with type %u\n", + CBFS_SEARCH.cbfs_name, CBFS_SEARCH.fmap_name, + CBFS_SEARCH.cbfs_type); + return NULL; + } + + cbfs_file_data(&data, &file); + } + + // check data header + if (check_header) { + if (!check_header(&data)) { + printk(BIOS_ERR, "Blob header check failed."); + return NULL; + } + } + + // Hook into mapping + if (hook_region_device(CBFS_SEARCH.id, CBFS_SEARCH.fmap_name, + CBFS_SEARCH.cbfs_name, CBFS_SEARCH.cbfs_type, + &data)) { + } + + if (size) + *size = region_device_sz(&data); + + // Unmap rd because entire SPI flash is MMAP, except SMM + void *region = rdev_mmap_full(&data); + rdev_munmap(&data, region); + + return region; +} + +uint32_t blob_provide_rd(blob_locator locator, struct region_device *data) +{ + blob_locator CBFS_SEARCH = locator; + struct cbfsf file; + + if (CBFS_SEARCH.id <= DATA_CODE_SPLIT) { + printk(BIOS_ERR, "Can't use auto rd function on data blob."); + return 1; + } + + switch (CBFS_SEARCH.id) { + } + + // Locate cbfs file in fmap region + if (cbfs_locate_file_in_region(&file, CBFS_SEARCH.fmap_name, + CBFS_SEARCH.cbfs_name, + &CBFS_SEARCH.cbfs_type) < 0) { + printk(BIOS_ERR, + "Could not locate %s key in CBFS on FMAP partition %s " + "with type %u\n", + CBFS_SEARCH.cbfs_name, CBFS_SEARCH.fmap_name, + CBFS_SEARCH.cbfs_type); + return 1; + } + + cbfs_file_data(data, &file); + + // Hook into mapping + if (hook_region_device(CBFS_SEARCH.id, CBFS_SEARCH.fmap_name, + CBFS_SEARCH.cbfs_name, CBFS_SEARCH.cbfs_type, + data)) { + return 1; + } + + return 0; +} diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index aeaff28..918c513 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -47,6 +47,7 @@ #include <cpu/x86/mtrr.h> #endif #include <commonlib/helpers.h> +#include <blob_provider.h> static struct lb_header *lb_table_init(unsigned long addr) { @@ -507,8 +508,7 @@ #if IS_ENABLED(CONFIG_USE_OPTION_TABLE) { struct cmos_option_table *option_table = - cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + blob_provide_map(BLOB_DATA_NVRAM_CMOS_LAYOUT, NULL, NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 79bda1e..7c85e7d 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -20,6 +20,7 @@ #include <string.h> #include <device/early_smbus.h> #include <device/dram/ddr3.h> +#include <blob_provider.h> static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; @@ -188,8 +189,7 @@ size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); if (spd_file_len < min_len) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 41e12eb..a04efb3 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -173,6 +173,7 @@ default: continue; } + // TODO FIX ME BLOB p = cbfs_boot_map_with_leak( file_name, CBFS_TYPE_RAW, &p_size); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 6911c36..5ca0718 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -162,6 +162,7 @@ /* HTX no io apic */ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } + // TODO FIX ME BLOB p = cbfs_boot_map_with_leak( file_name, CBFS_TYPE_RAW, &p_size); diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index 3388322..3b31310 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -29,6 +29,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> +#include <blob_provider.h> void pch_enable_lpc(void) { @@ -76,8 +77,7 @@ { void *spd_file; size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (spd_file && spd_file_len >= 1024) { int i; for (i = 0; i < 4; i++) diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 12c876e..003bddf 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 12c876e..003bddf 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 12c876e..003bddf 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index ac99f5c..3869ab5 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -25,6 +25,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -107,7 +108,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index dd632f3..2ea3988 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -24,6 +24,7 @@ #include <mainboard/google/auron/ec.h> #include <variant/gpio.h> #include <variant/spd.h> +#include <blob_provider.h> static void mainboard_print_spd_info(uint8_t spd[]) { @@ -102,7 +103,7 @@ spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 140c814..4fbd519 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -23,6 +23,7 @@ #include <fmap.h> #include <southbridge/intel/bd82x6x/pch.h> #include "onboard.h" +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -115,18 +116,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_provide_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + NULL, &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_provide_map(BLOB_DATA_NVRAM_VPD, NULL, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index a100981..b5e7fca 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -35,6 +35,7 @@ #include <device/pci.h> #include <ec/quanta/ene_kb3940q/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <blob_provider.h> static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -187,28 +188,13 @@ size_t search_length = -1; u16 io_base = 0; struct device *ethernet_dev = NULL; - void *vpd_file; if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - vpd_file = rdev_mmap_full(&rdev); - - if (vpd_file != NULL) { - search_length = region_device_sz(&rdev); - search_address = (uintptr_t)vpd_file; - } - } + search_address = blob_provide_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + NULL, &search_length); } else { - vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, - &search_length); - if (vpd_file) { - search_address = (unsigned long)vpd_file; - } else { - search_length = -1; - search_address = 0; - } + search_address = + blob_provide_map(BLOB_DATA_NVRAM_VPD, NULL, &search_length); } /* Initialize the Embedded Controller */ diff --git a/src/mainboard/google/chell/spd/spd.c b/src/mainboard/google/chell/spd/spd.c index 251b6de..664de16 100644 --- a/src/mainboard/google/chell/spd/spd.c +++ b/src/mainboard/google/chell/spd/spd.c @@ -22,6 +22,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "../gpio.h" #include "spd.h" @@ -95,8 +96,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index a3db2ed..5f8d708 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -27,6 +27,7 @@ #include <string.h> #include <spd_bin.h> #include "spd_util.h" +#include <blob_provider.h> __attribute__ ((weak)) uint8_t get_ramid(void) { @@ -66,8 +67,7 @@ int dual_channel = 0; /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index 2f365a7..58cea5e 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -22,6 +22,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "../gpio.h" #include "spd.h" @@ -98,8 +99,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 251b6de..664de16 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -22,6 +22,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "../gpio.h" #include "spd.h" @@ -95,8 +96,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index 59ed111..1d0ba5e 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <soc/pch.h> #include "onboard.h" +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -115,18 +116,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_provide_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + NULL, &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_provide_map(BLOB_DATA_NVRAM_VPD, NULL, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c index 106eb83..0e3bba3 100644 --- a/src/mainboard/google/lars/spd/spd.c +++ b/src/mainboard/google/lars/spd/spd.c @@ -20,6 +20,7 @@ #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include "spd.h" @@ -86,8 +87,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index bf05be9..2fd11a0 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -36,6 +36,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> +#include <blob_provider.h> #include <southbridge/intel/bd82x6x/chip.h> @@ -122,8 +123,7 @@ int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 6bb4076..3bfad3f 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <soc/romstage.h> #include <string.h> +#include <blob_provider.h> #include <fsp/soc_binding.h> @@ -122,8 +123,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 25fe859..567ba03 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -21,6 +21,7 @@ #include <soc/mrc_wrapper.h> #include <soc/romstage.h> #include <variant/variant.h> +#include <blob_provider.h> static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { @@ -71,8 +72,7 @@ }, }; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 3d08ad7..33594de 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <fmap.h> #include <variant/onboard.h> +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -114,18 +115,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_provide_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + NULL, &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_provide_map(BLOB_DATA_NVRAM_VPD, NULL, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index 07fe3d9..2ad76f3 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <fmap.h> #include <variant/onboard.h> +#include <blob_provider.h> static unsigned int search(char *p, u8 *a, unsigned int lengthp, unsigned int lengtha) @@ -114,18 +115,11 @@ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { - search_address = rdev_mmap_full(&rdev); - - if (search_address != NULL) - search_length = region_device_sz(&rdev); - } + search_address = blob_provide_map(BLOB_DATA_NVRAM_VPD_RO_REGION, + NULL, &search_length); } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = + blob_provide_map(BLOB_DATA_NVRAM_VPD, NULL, &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 81174db..b8744f1 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -26,6 +26,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <variant/gpio.h> #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -77,8 +78,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 132f586..3bc2ee3 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -26,6 +26,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <variant/gpio.h> #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -77,8 +78,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index bf21cbc..d2c6048 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -29,6 +29,7 @@ #include <variant/gpio.h> #include "../../onboard.h" #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -80,8 +81,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 5b6b254..b1ee977 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -28,6 +28,7 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <variant/gpio.h> #include "../../variant.h" +#include <blob_provider.h> const struct rcba_config_instruction rcba_config[] = { @@ -79,8 +80,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 9a6b64e..bc5398a 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -48,6 +48,7 @@ int i; size_t length; + // TODO BLOB file_contents = cbfs_boot_map_with_leak(board_id_file_name, CBFS_TYPE_RAW, &length); diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c index dbf786e..699d763 100644 --- a/src/mainboard/hp/revolve_810_g1/romstage.c +++ b/src/mainboard/hp/revolve_810_g1/romstage.c @@ -23,6 +23,7 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/hp/kbc1126/ec.h> +#include <blob_provider.h> void pch_enable_lpc(void) { @@ -79,8 +80,7 @@ { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index 37f4424..19fc74f 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -19,6 +19,7 @@ #include <cbfs.h> #include <console/console.h> #include <string.h> +#include <blob_provider.h> #include "spd.h" @@ -32,8 +33,7 @@ spd_index = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index a17b519..85c0b23 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -21,6 +21,7 @@ #include <soc/pei_wrapper.h> #include "boardid.h" #include "spd.h" +#include <blob_provider.h> void mainboard_fill_dq_map_data(void *dq_map_ptr) { @@ -83,8 +84,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e9818b3..07fc1ca 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -170,6 +170,7 @@ file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; } + // TODO blob p = cbfs_boot_map_with_leak( file_name, CBFS_TYPE_RAW, &p_size); diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 43a3d52..50bc613 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -32,6 +32,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "ec.h" +#include <blob_provider.h> #define SPD_LEN 256 @@ -115,8 +116,7 @@ spd_index, mainboard_spd_names[spd_index]); /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) die("SPD data not found."); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 5f7b82e..ddb2739 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -36,6 +36,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> +#include <blob_provider.h> void pch_enable_lpc(void) { @@ -75,8 +76,7 @@ size_t spd_file_len; printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index d2231aa..84bfc1b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -37,6 +37,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "option_table.h" +#include <blob_provider.h> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif @@ -157,8 +158,7 @@ break; } - spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_data = blob_provide_map(BLOB_DATA_SPD, NULL, &spd_file_len); if (!spd_data) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index fd19cd1..0866c96 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -90,7 +90,7 @@ mapping[i + 4] = buf[chain_len - i - 1]; /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return CB_ERR; /* Now try to find a valid MAC address in hwinfo for this mapping.*/ for (i = 0; i < MAX_NUM_MAPPINGS; i++) { @@ -159,7 +159,7 @@ struct stopwatch sw; /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return; /* Get legacy delay parameter from hwinfo. */ diff --git a/src/mainboard/siemens/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/ptn3460.c index 1877e8b..fb0c95a 100644 --- a/src/mainboard/siemens/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/ptn3460.c @@ -34,7 +34,7 @@ uint8_t edid_data[PTN_EDID_LEN]; int i; - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + if (!hwi_block || hwilib_find_blocks() != CB_SUCCESS) { printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); return 1; diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index ea525d4..c6f0ab3 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -197,7 +197,7 @@ mapping[i + 4] = buf[chain_len - i - 1]; /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return CB_ERR; /* Now try to find a valid MAC address in hwinfo for this mapping.*/ for (i = 0; i < MAX_NUM_MAPPINGS; i++) { diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index df08471..14d9778 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -46,7 +46,7 @@ uint32_t i; /* Open main hwinfo block */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + if (hwilib_find_blocks() != CB_SUCCESS) return CB_ERR; /* Get first MAC address from hwinfo. */ if (hwilib_get_field(Mac1, mac_adr, sizeof(mac_adr)) != sizeof(mac_adr)) diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 347bc9c..c2f3f9f 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -32,7 +32,7 @@ uint8_t edid_data[0x80]; uint8_t hwid[4], tcu31_hwid[4] = {7, 9, 2, 0}; - if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + if (!hwi_block || hwilib_find_blocks() != CB_SUCCESS) { printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", hwi_block); return 1; diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 15d949e..f466207 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -174,7 +174,7 @@ /* Get SPD data from hwinfo block and set up memory down */ /* parameters for FSP accordingly. */ - if (hwilib_find_blocks("hwinfo.hex")) { + if (hwilib_find_blocks()) { printk(BIOS_ERR, "HWInfo not found, use default timings for DDR3.\n"); return; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 4100b26..dc49795 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -31,6 +31,7 @@ #include <string.h> #include "mct_d.h" #include "mct_d_gcc.h" +#include <blob_provider.h> #include "s3utils.h" @@ -213,7 +214,7 @@ s3nv_file_offset = s3nv_offset - s3nv_file_offset; /* Map data structure in CBFS and restore settings */ - s3nv_cbfs_file_ptr = cbfs_boot_map_with_leak(S3NV_FILE_NAME, CBFS_TYPE_RAW, NULL); + s3nv_cbfs_file_ptr = blob_provide_map(BLOB_DATA_AMD_S3NV, NULL, NULL); if (!s3nv_cbfs_file_ptr) { printk(BIOS_DEBUG, "S3 state file could not be mapped: %s\n", S3NV_FILE_NAME); return NULL; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index d912317..d5897a4 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -24,6 +24,7 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> +#include <blob_provider.h> void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -293,14 +294,7 @@ const AMD_MODULE_HEADER* module; size_t file_size; - if (IS_ENABLED(CONFIG_VBOOT)) { - /* Use phys. location in flash and prevent vboot from searching cbmem */ - agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; - file_size = 0x100000; - } else { - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); - } + agesa = blob_provide_map(BLOB_CODE_AMD_AGESA, NULL, &file_size); if (!agesa) return NULL; diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index f692282..c265df4 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -64,16 +64,11 @@ *mrc_region_ptr = NULL; if (IS_ENABLED(CONFIG_CHROMEOS)) { - struct region_device rdev; - - if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { - region_size = region_device_sz(&rdev); - *mrc_region_ptr = rdev_mmap_full(&rdev); - } + *mrc_region_ptr = blob_provide_map(BLOB_DATA_MRC_CACHE_REGION, + NULL, &region_size); } else { - *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); + *mrc_region_ptr = + blob_provide_map(BLOB_DATA_MRC_CACHE, NULL, &region_size); } return region_size; } diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index f17a374..ed51aa1 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -32,6 +32,7 @@ #include "raminit.h" #include "pei_data.h" #include "haswell.h" +#include <blob_provider.h> void save_mrc_data(struct pei_data *pei_data) { @@ -141,8 +142,7 @@ pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = (unsigned long)cbfs_boot_map_with_leak("mrc.bin", - CBFS_TYPE_MRC, NULL); + entry = blob_provide_map(BLOB_CODE_INTEL_MRC, NULL, NULL); if (entry) { int rv; asm volatile ( diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 901a083..da4f46a 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -32,6 +32,7 @@ #include "pei_data.h" #include "sandybridge.h" #include <security/vboot/vboot_common.h> +#include <blob_provider.h> /* Management Engine is in the southbridge */ #include "southbridge/intel/bd82x6x/me.h" @@ -216,7 +217,7 @@ pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + entry = blob_provide_map(BLOB_CODE_INTEL_MRC, NULL, NULL); if (entry) { int rv; rv = entry (pei_data); diff --git a/src/security/vboot/secdata_measurements.c b/src/security/vboot/secdata_measurements.c index 9111ffa..84829bf 100644 --- a/src/security/vboot/secdata_measurements.c +++ b/src/security/vboot/secdata_measurements.c @@ -14,9 +14,10 @@ */ #include "antirollback.h" +#include <blob_provider.h> #include <cbfs.h> -#include <fmap.h> #include <console/console.h> +#include <fmap.h> #include <security/tpm/tspi.h> uint32_t vboot_measure_crtm(void) @@ -29,19 +30,17 @@ /* measure bootblock from RO */ struct cbfsf bootblock_data; - if (!cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL)) { + if (cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL) == + 0) { cbfs_file_data(prog_rdev(&bootblock), &bootblock_data); if (tpm_measure_region(TPM_BOOTBLOCK_PCR, prog_rdev(&bootblock), "bootblock")) { return VB2_ERROR_UNKNOWN; } - - printk(BIOS_INFO, "VBOOT: Couldn't measure %s into CRTM!", - "bootblock"); } else { struct region_device fmap; - if (!fmap_locate_area_as_rdev("BOOTBLOCK", &fmap)) { + if (fmap_locate_area_as_rdev("BOOTBLOCK", &fmap) == 0) { if (tpm_measure_region(TPM_BOOTBLOCK_PCR, &fmap, "bootblock")) { return VB2_ERROR_UNKNOWN; @@ -56,8 +55,8 @@ if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) { struct cbfsf romstage_data; /* measure verstage from RO */ - if (!cbfs_boot_locate(&romstage_data, prog_name(&romstage), - NULL)) { + if (cbfs_boot_locate(&romstage_data, prog_name(&romstage), + NULL) == 0) { cbfs_file_data(prog_rdev(&romstage), &romstage_data); if (tpm_measure_region(TPM_STAGE_ROMSTAGE_PCR, @@ -76,8 +75,8 @@ if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) { struct cbfsf verstage_data; /* measure verstage from RO */ - if (!cbfs_boot_locate(&verstage_data, prog_name(&verstage), - NULL)) { + if (cbfs_boot_locate(&verstage_data, prog_name(&verstage), + NULL) == 0) { cbfs_file_data(prog_rdev(&verstage), &verstage_data); if (tpm_measure_region(TPM_STAGE_VERSTAGE_PCR, @@ -146,3 +145,44 @@ break; } } + +uint32_t hook_region_device(uint32_t id, const char *fmap_name, + const char *cbfs_name, uint32_t cbfs_type, + const struct region_device *data) +{ + tpm_measure_region(TPM_STAGE_ROMSTAGE_PCR, data, cbfs_name); + /* + switch(id) { + case ID_DATA_BOOTSPLASH: + case ID_DATA_ACPI_SLIC: + case ID_DATA_ACPI_DSDT: + case ID_DATA_ACPI_SSDT: + case ID_DATA_MICROCODE: + case ID_DATA_MICROCODE_RMU: + case ID_DATA_MRC_CACHE: + case ID_DATA_VGA_VBT: + case ID_DATA_NVRAM_CMOS_LAYOUT: + case ID_DATA_NVRAM_CMOS_DEFAULT: + case ID_DATA_NVRAM_VPD: + case ID_DATA_SIEMENS_HWLIB: + case ID_DATA_SPD: + case ID_DATA_MAC: + case ID_DATA_AMD_S3NV: + case ID_CODE_AMD_AGESA: + case ID_CODE_AMD_AGESA_PRE_MEM: + case ID_CODE_AMD_AGESA_POST_MEM: + case ID_CODE_AMD_PSP: + case ID_CODE_INTEL_MRC: + case ID_CODE_INTEL_FSP_S: + case ID_CODE_INTEL_FSP_M: + case ID_CODE_INTEL_MMA: + case ID_CODE_NVIDIA_MTC: + case ID_CODE_QUALCOMM_CDT: + case ID_CODE_QUALCOMM_DDR: + case ID_CODE_QUALCOMM_TZ: + case ID_CODE_QUALCOMM_RPM: + break; + } + */ + return 0; +} diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index c05d4de..8eff384 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -143,6 +143,7 @@ GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo; pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; + // TODO FIX ME BLOB pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( "pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM, NULL); diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index a1a0e5b..db1d8ae 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -247,16 +247,14 @@ int psp_load_named_blob(int type, const char *name) { void *blob; - struct cbfsf cbfs_file; struct region_device rdev; int r; - if (cbfs_boot_locate(&cbfs_file, name, NULL)) { + if (blob_provide_rd(BLOB_CODE_AMD_PSP, &rdev)) { printk(BIOS_ERR, "BUG: Cannot locate blob for PSP loading\n"); return PSPSTS_INVALID_NAME; } - cbfs_file_data(&rdev, &cbfs_file); blob = rdev_mmap_full(&rdev); if (blob) { r = psp_load_blob(type, blob); diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 665dad2..2d6980e 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -36,6 +36,7 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/systemagent.h> +#include <blob_provider.h> /* * Find PEI executable in coreboot filesystem and execute it. @@ -78,7 +79,7 @@ } /* Determine if mrc.bin is in the cbfs. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + entry = blob_provide_map(BLOB_CODE_INTEL_MRC, NULL, NULL); if (entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 541a7b4..defd421 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/console.h> #include <soc/intel/common/mma.h> +#include <blob_provider.h> #define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" #define MMA_TEST_NAME_TAG "MMA_TEST_NAME" @@ -118,22 +119,15 @@ size_t mma_test_metadata_file_len; char test_filename[TEST_NAME_MAX_SIZE], test_param_filename[TEST_PARAM_MAX_SIZE]; - struct cbfsf metadata_fh, test_content_fh, test_param_fh; + struct cbfsf test_content_fh, test_param_fh; uint32_t mma_type = CBFS_TYPE_MMA; uint32_t efi_type = CBFS_TYPE_EFI; bool metadata_parse_flag = true; printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__); - if (cbfs_locate_file_in_region(&metadata_fh, MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, &mma_type)) { - printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", - MMA_TEST_METADATA_FILENAME); - return -1; - } - - mma_test_metadata = rdev_mmap_full(&metadata_fh.data); - mma_test_metadata_file_len = region_device_sz(&metadata_fh.data); + mma_test_metadata = blob_provide_map(BLOB_CODE_INTEL_MMA, NULL, + &mma_test_metadata_file_len); if (!mma_test_metadata || !mma_test_metadata_file_len) { printk(BIOS_DEBUG, "MMA: Failed to read %s\n", diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index a43504c..3495802 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -32,6 +32,7 @@ #include <soc/ramstage.h> #include <soc/fiamux.h> #include <spi-generic.h> +#include <blob_provider.h> static void pci_domain_set_resources(device_t dev) { @@ -104,8 +105,8 @@ const struct microcode *microcode_file; size_t microcode_len; - microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &microcode_len); + microcode_file = + blob_provider_map(BLOB_DATA_MICROCODE, NULL, &microcode_len); if ((microcode_file != NULL) && (microcode_len != 0)) { /* Update CPU Microcode patch base address/size */ diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 7a9e8f5..2339cb2 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -60,6 +60,7 @@ if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN)) { UpdData->MemDownEnable = 1; + // TODO FIX ME BLOB if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) UpdData->MemDownCh0Dimm0SpdPtr = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c5f59c6..8a79184 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -23,6 +23,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> +#include <blob_provider.h> static const struct reg_script clear_smi_and_wake_events_script[] = { /* Clear any SMI or wake events */ @@ -65,29 +66,5 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; - size_t fsize; - void *rmu_data; - uint32_t type; - - /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) - return NULL; - - /* Get the file size */ - fsize = region_device_sz(&fh.data); - if (rmu_file_len != NULL) - *rmu_file_len = fsize; - - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); - return rmu_data; + return blob_provide_map(BLOB_DATA_MICROCODE_RMU, NULL, rmu_file_len); } diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c index f71e5e8..f0ff969 100644 --- a/src/soc/nvidia/tegra210/mtc.c +++ b/src/soc/nvidia/tegra210/mtc.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <soc/mtc.h> #include <string.h> +#include <blob_provider.h> static size_t mtc_table_size; @@ -28,26 +29,23 @@ int tegra210_run_mtc(void) { ssize_t nread; - struct region_device fh; - struct cbfsf mtc_file; + struct region_device mtc_file; void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS; void *dvfs_table; size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc; - if (cbfs_boot_locate(&mtc_file, "tegra_mtc.bin", NULL)) { + if (blob_provide_rd(BLOB_CODE_NVIDIA_MTC, &mtc_file)) { printk(BIOS_ERR, "MTC file not found: tegra_mtc.bin\n"); return -1; } - cbfs_file_data(&fh, &mtc_file); - /* Read MTC file into predefined region. */ - nread = rdev_readat(&fh, mtc, 0, region_device_sz(&fh)); + nread = rdev_readat(&mtc_file, mtc, 0, region_device_sz(&mtc_file)); - if (nread != region_device_sz(&fh)) { + if (nread != region_device_sz(&mtc_file)) { printk(BIOS_ERR, "MTC bytes read (%zu) != file length(%zu)!\n", - nread, region_device_sz(&fh)); + nread, region_device_sz(&mtc_file)); return -1; } diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 77c0289..dae9563 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -25,6 +25,7 @@ #include <soc/iomap.h> #include <soc/soc_services.h> +#include <blob_provider.h> #include "mbn_header.h" @@ -33,14 +34,13 @@ uint8_t *cdt_ptr; /* pointer to CDT */ }; -static void *load_ipq_blob(const char *file_name) +static void *load_ipq_blob(blob_locator identifier) { struct mbn_header *blob_mbn; void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = blob_provide_map(identifier, NULL, &blob_size); if (!blob_mbn) return NULL; @@ -91,8 +91,8 @@ sbl_rw_ret_info_t (*(*ddr_init_function)(struct cdt_info *cdt_header)); - cdt = load_ipq_blob(CONFIG_CDT_MBN); - ddr_init_function = load_ipq_blob(CONFIG_DDR_MBN); + cdt = load_ipq_blob(BLOB_CODE_QUALCOMM_CDT); + ddr_init_function = load_ipq_blob(BLOB_CODE_QUALCOMM_DDR); if (!cdt || !ddr_init_function) { printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n", @@ -126,7 +126,7 @@ #else /* __PRE_RAM__ */ void start_tzbsp(void) { - void *tzbsp = load_ipq_blob(CONFIG_TZ_MBN); + void *tzbsp = load_ipq_blob(BLOB_CODE_QUALCOMM_TZ); if (!tzbsp) die("could not find or map TZBSP\n"); diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 5b19fc1..f3186e7 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -23,17 +23,17 @@ #include <soc/iomap.h> #include <soc/soc_services.h> +#include <blob_provider.h> #include "mbn_header.h" -static void *load_ipq_blob(const char *file_name) +static void *load_ipq_blob(blob_locator identifier) { struct mbn_header *blob_mbn; void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = blob_provide_map(identifier, NULL, &blob_size); if (!blob_mbn) return NULL; @@ -67,8 +67,8 @@ void *cdt; int (*ddr_init_function)(void *cdt_header); - cdt = load_ipq_blob("cdt.mbn"); - ddr_init_function = load_ipq_blob("ddr.mbn"); + cdt = load_ipq_blob(BLOB_CODE_QUALCOMM_CDT); + ddr_init_function = load_ipq_blob(BLOB_CODE_QUALCOMM_DDR); if (!cdt || !ddr_init_function) { printk(BIOS_ERR, "cdt: %p, ddr_init_function: %p\n", @@ -93,7 +93,7 @@ void start_tzbsp(void) { - void *tzbsp = load_ipq_blob("tz.mbn"); + void *tzbsp = load_ipq_blob(BLOB_CODE_QUALCOMM_TZ); if (!tzbsp) die("could not find or map TZBSP\n"); @@ -118,7 +118,7 @@ return; } - load_addr = (u32) load_ipq_blob("rpm.mbn"); + load_addr = (u32) load_ipq_blob(BLOB_CODE_QUALCOMM_RPM); if (!load_addr) die("could not find or map RPM code\n"); diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index f15937b..c139771 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -19,7 +19,7 @@ #include <arch/io.h> #include <arch/early_variables.h> #include "hwilib.h" - +#include <blob_provider.h> #define MAX_BLOCK_NUM 4 #define LEN_HIB 0x1fd @@ -463,7 +463,7 @@ * @param *hwi_filename Name of the cbfs-file to use. * @return CB_SUCCESS when no error, otherwise error code */ -enum cb_err hwilib_find_blocks (const char *hwi_filename) +enum cb_err hwilib_find_blocks () { uint8_t *ptr = NULL, *base = NULL; uint32_t next_offset = 1; @@ -471,13 +471,9 @@ uint16_t *all_blk_size_ptr = car_get_var_ptr(&all_blk_size[0]); size_t filesize = 0; - /* Check for a valid parameter */ - if (!hwi_filename) - return CB_ERR_ARG; - ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, &filesize); + ptr = blob_provide_map(BLOB_DATA_SIEMENS_HWLIB, NULL, &filesize); if (!ptr) { - printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", - hwi_filename); + printk(BIOS_ERR,"HWILIB: Missing file HWLIB in cbfs.\n"); return CB_ERR; } /* Ensure the block has the right magic */ diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index 6850f07..1297c6f 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -131,7 +131,7 @@ /* Use this function to find all supported blocks in cbfs. It must be called * once with a valid cbfs file name before hwilib_get_field() can be used. */ -enum cb_err hwilib_find_blocks (const char *hwi_filename); +enum cb_err hwilib_find_blocks (); /* Use this function to get fields out of supported info blocks * This function returns the number of copied bytes or 0 on error. -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: [WIP]mb/google/octopus: Add device tree settings
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23846 ) Change subject: [WIP]mb/google/octopus: Add device tree settings ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22569/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68117/ : SUCCESS -- To view, visit https://review.coreboot.org/23846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Gerrit-Change-Number: 23846 Gerrit-PatchSet: 8 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 20:31:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]mb/google/octopus: Add device tree settings
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23846 ) Change subject: [WIP]mb/google/octopus: Add device tree settings ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68116/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22568/ : SUCCESS -- To view, visit https://review.coreboot.org/23846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Gerrit-Change-Number: 23846 Gerrit-PatchSet: 7 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 19:52:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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