coreboot-gerrit March 2018

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Change in coreboot[master]: sb/intel/common: Fix conflicting OIC register definition
by Nico Huber (Code Review) 01 Mar '18

01 Mar '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/24924 Change subject: sb/intel/common: Fix conflicting OIC register definition ...................................................................... sb/intel/common: Fix conflicting OIC register definition Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/cougar_canyon2/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/common/rcba.h 9 files changed, 17 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/24924/1 diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index a300ff6..ebcba84 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -96,9 +96,9 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 544bb4a..a1bbe34 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -104,9 +104,9 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); } static uint8_t *locate_spd(void) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 3b7c242..12c1114 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -95,9 +95,9 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index ffa2157..4f7f869 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -101,9 +101,9 @@ DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 96c22ea..47f7ea5 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -158,9 +158,9 @@ DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index d7ed435..ce17068 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -103,9 +103,9 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); } static const uint8_t *locate_spd(void) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 265530c..1b5d2ae 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -112,9 +112,9 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); } static void setup_sio_gpios(void) diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 990ff0d..9ce9dc9 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -60,9 +60,9 @@ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ - RCBA16(OIC) = 0x0100; + RCBA16(EOIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void) RCBA16(EOIC); } void diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 1399fde..ad8285a 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -147,6 +147,7 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */ +#define EOIC 0x31fe /* 16bit */ #define OIC 0x31ff /* 8bit */ #define DIR_ROUTE(x, a, b, c, d) \ -- To view, visit https://review.coreboot.org/24924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Gerrit-Change-Number: 24924 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/denverton_ns: Add UART legacy mode with FSP traces
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23623 ) Change subject: soc/intel/denverton_ns: Add UART legacy mode with FSP traces ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68099/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22555/ : SUCCESS -- To view, visit https://review.coreboot.org/23623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538 Gerrit-Change-Number: 23623 Gerrit-PatchSet: 4 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: FEI WANG <wangfei.jimei(a)gmail.com> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 09:14:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/reef/sand: Override USB2 phy settings
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23879 ) Change subject: mb/google/reef/sand: Override USB2 phy settings ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68098/ : SUCCESS -- To view, visit https://review.coreboot.org/23879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769 Gerrit-Change-Number: 23879 Gerrit-PatchSet: 2 Gerrit-Owner: Katherine Hsieh <Katherine.Hsieh(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 07:22:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/nautilus: Modify the XTDV = 210 due to different OSC from P...
by Andy Yeh (Code Review) 01 Mar '18

01 Mar '18

Andy Yeh has posted comments on this change. ( https://review.coreboot.org/24910 ) Change subject: mb/google/nautilus: Modify the XTDV = 210 due to different OSC from Poppy ...................................................................... Patch Set 2: added Rizwan and Raj for Intel review first. Please help check and let me know if any questions. -- To view, visit https://review.coreboot.org/24910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a Gerrit-Change-Number: 24910 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Yeh <andy.yeh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Yeh Gerrit-Comment-Date: Thu, 01 Mar 2018 07:05:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/nautilus: Modify the XTDV = 210 due to different OSC from P...
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24910 ) Change subject: mb/google/nautilus: Modify the XTDV = 210 due to different OSC from Poppy ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68097/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22554/ : SUCCESS -- To view, visit https://review.coreboot.org/24910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a Gerrit-Change-Number: 24910 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Yeh <andy.yeh(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 06:49:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/nautilus: Modify the XTDV = 210 due to different OSC from P...
by Andy Yeh (Code Review) 01 Mar '18

01 Mar '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/24910 to look at the new patch set (#2). Change subject: mb/google/nautilus: Modify the XTDV = 210 due to different OSC from Poppy ...................................................................... mb/google/nautilus: Modify the XTDV = 210 due to different OSC from Poppy It is to change MCLK output in 19.2Mhz (currently 23.04Mhz) because nautilus uses different OSC for TI PMIC. According to PMIC datasheet (tps68470), the MCLK for camera depends on the frequency of OSC. In poppy, the frequency of OSC is 20 MHz, the PLL_REF_CLK = 20M / [XTDV (170) + 30] = 100kHz. If we want to keep the PLL_REF_CLK in nautilus with 24 MHz OSC, we should change XDTV to 210. BUG=b:73987684 TEST: Verified the MIPI camera fps on DUT board. TODO: OEM tries to fix OSC on next build. Then this patch shall be reverted. Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a Signed-off-by: Andy Yeh <andy.yeh(a)intel.com> --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/24910/2 -- To view, visit https://review.coreboot.org/24910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a Gerrit-Change-Number: 24910 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Yeh <andy.yeh(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/zoombini/variant/meowth: enable speed shift
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24902 ) Change subject: mainboard/google/zoombini/variant/meowth: enable speed shift ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68096/ : SUCCESS -- To view, visit https://review.coreboot.org/24902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd Gerrit-Change-Number: 24902 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 02:53:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] mb/google/zoombini/variants/meowth: Enable NVMe
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23208 ) Change subject: [WIP] mb/google/zoombini/variants/meowth: Enable NVMe ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68095/ : SUCCESS -- To view, visit https://review.coreboot.org/23208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Gerrit-Change-Number: 23208 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 00:31:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: enable NVMe
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23208 ) Change subject: mainboard/google/zoombini/variants/meowth: enable NVMe ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68094/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22553/ : SUCCESS -- To view, visit https://review.coreboot.org/23208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Gerrit-Change-Number: 23208 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 00:04:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018