coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/zoombini/variants/meowth: Enable NVMe
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23208 ) Change subject: mb/google/zoombini/variants/meowth: Enable NVMe ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68115/ : SUCCESS -- To view, visit https://review.coreboot.org/23208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Gerrit-Change-Number: 23208 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 19:43:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/apollolake: Enable ThunderPeak wifi card
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24932 ) Change subject: soc/intel/apollolake: Enable ThunderPeak wifi card ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68114/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22567/ : SUCCESS -- To view, visit https://review.coreboot.org/24932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c Gerrit-Change-Number: 24932 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 19:40:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/glkrvp: Enable ThunderPeak wifi card
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24931 ) Change subject: mb/intel/glkrvp: Enable ThunderPeak wifi card ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68113/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22566/ : SUCCESS -- To view, visit https://review.coreboot.org/24931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2 Gerrit-Change-Number: 24931 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 19:31:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/apollolake: Enable ThunderPeak wifi card
by Roy Mingi Park (Code Review) 01 Mar '18

01 Mar '18

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/24932 Change subject: soc/intel/apollolake: Enable ThunderPeak wifi card ...................................................................... soc/intel/apollolake: Enable ThunderPeak wifi card This enables ThunderPeak WiFi card on M.2. TEST=Verify wlan card shows up in lspci Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- A src/soc/intel/apollolake/acpi/pcie_glk.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/chip.c 3 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/24932/1 diff --git a/src/soc/intel/apollolake/acpi/pcie_glk.asl b/src/soc/intel/apollolake/acpi/pcie_glk.asl new file mode 100644 index 0000000..32a7d71 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pcie_glk.asl @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (RP02) +{ + Name (_ADR, 0x140001) + Name (_DDN, "PCIe-B 0") + Name (PDST, 0) /* present Detect status */ + + /* lowest D-state supported by + * PCIe root port during S0 state + */ + Name (_S0W, 4) + + /* Dynamic Opregion needed to access registers + * when the controller is in D3 cold + */ + OperationRegion (PX01, PCI_Config, 0x00, 0xFF) + Field (PX01, AnyAcc, NoLock, Preserve) + { + Offset(0x5A), + , 6, + PDS, 1, /* 6, Presence detect Change */ + Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0xF4), /* BLKPLLEN */ + , 10, + BPLL, 1, + } + + OperationRegion (PX02, PCI_Config, 0x338, 0x4) + Field (PX02, AnyAcc, NoLock, Preserve) + { + , 26, + BDQA, 1 /* BLKDQDA */ + } + + PowerResource (PXP, 0, 0) + { + /* Define the PowerResource for PCIe slot */ + Method (_STA, 0, Serialized) + { + Store (PDS, PDST) + If (LEqual (PDS, 1)) { + Return (0xf) + } Else { + Return (0) + } + } + + Method (_ON, 0, Serialized) + { + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* Enter this condition if device + * is connected + */ + + /* De-assert PERST */ + \_SB.PCI0.PRAS (\PRT0) + + Store (0, BDQA) /* Set BLKDQDA to 0 */ + Store (0, BPLL) /* Set BLKPLLEN to 0 */ + + /* Set L23_Rdy to Detect Transition + * (L23R2DT) + */ + Store (1, L23R) + Sleep (16) + Store (0, Local0) + + /* Delay for transition Detect + * and link to train + */ + While (L23R) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + } /* End PDS condition check */ + } + + Method (_OFF, 0, Serialized) + { + /* Set L23_Rdy Entry Request (L23ER) */ + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* enter this condition if device + * is connected + */ + Store (1, L23E) + Sleep (16) + Store (0, Local0) + While (L23E) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + Store (1, BDQA) /* Set BLKDQDA to 1 */ + Store (1, BPLL) /* Set BLKPLLEN to 1 */ + + /* Assert PERST */ + \_SB.PCI0.PRDA (\PRT0) + } /* End PDS condition check */ + } /* End of Method_OFF */ + } /* End PXP */ + + Name(_PR0, Package() { PXP }) + Name(_PR3, Package() { PXP }) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b8f9b7..d93234e 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -28,7 +28,11 @@ } /* PCIE device */ +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#include "pcie_glk.asl" +#else #include "pcie.asl" +#endif /* LPSS device */ #include "lpss.asl" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 53ffdb9..76e860f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -502,6 +502,7 @@ struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) { silconfig->Gmm = 0; + silconfig->PcieRpSelectableDeemphasis[1] = 0; } void __attribute__((weak)) mainboard_devtree_update(struct device *dev) -- To view, visit https://review.coreboot.org/24932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c Gerrit-Change-Number: 24932 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>

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Change in coreboot[master]: mb/intel/glkrvp: Enable ThunderPeak wifi card
by Roy Mingi Park (Code Review) 01 Mar '18

01 Mar '18

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/24931 Change subject: mb/intel/glkrvp: Enable ThunderPeak wifi card ...................................................................... mb/intel/glkrvp: Enable ThunderPeak wifi card This enables ThunderPeak WiFi card on M.2. TEST=Verify wlan card shows up in lspci Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/24931/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 45badcd..d16b88d 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -9,13 +9,13 @@ register "pcie_rp1_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "1" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" # GPIO for PERST_0 # If the Board has PERST_0 signal, assign the GPIO # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_PRT0_UDEF" + register "prt0_gpio" = "GPIO_163" # GPIO for SD card detect register "sdcard_cd_gpio" = "GPIO_186" @@ -123,9 +123,9 @@ device pci 12.0 on end # - SATA device pci 13.0 off end # - PCIe-A 0 Slot 1 device pci 13.1 off end # - PCIe-A 1 - device pci 13.2 on end # - PCIe-A 2 Onboard Lan + device pci 13.2 off end # - PCIe-A 2 Onboard Lan device pci 13.3 off end # - PCIe-A 3 - device pci 14.0 off end # - PCIe-B 0 Slot2 + device pci 14.0 off end # - PCIe-B 0 Slot2 device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT) device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 0646bcf..9737355 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -151,9 +151,9 @@ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ0_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ1_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ2_B*/ + PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* unused */ PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/ PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/ PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/ -- To view, visit https://review.coreboot.org/24931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2 Gerrit-Change-Number: 24931 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>

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Change in coreboot[master]: mb/google/zoombini/variants/meowth: Enable NVMe
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23208 ) Change subject: mb/google/zoombini/variants/meowth: Enable NVMe ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68112/ : SUCCESS -- To view, visit https://review.coreboot.org/23208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Gerrit-Change-Number: 23208 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 19:05:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Add ST/CZ SMBus device id
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24930 ) Change subject: soc/amd/stoneyridge: Add ST/CZ SMBus device id ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68111/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22565/ : SUCCESS -- To view, visit https://review.coreboot.org/24930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Gerrit-Change-Number: 24930 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 18:45:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Add ST/CZ SMBus device id
by build bot (Jenkins) (Code Review) 01 Mar '18

01 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24930 ) Change subject: soc/amd/stoneyridge: Add ST/CZ SMBus device id ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68110/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22564/ : SUCCESS -- To view, visit https://review.coreboot.org/24930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Gerrit-Change-Number: 24930 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Mar 2018 18:40:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Add ST/CZ SMBus device id
by Martin Roth (Code Review) 01 Mar '18

01 Mar '18

Martin Roth has uploaded a new patch set (#2). ( https://review.coreboot.org/24930 ) Change subject: soc/amd/stoneyridge: Add ST/CZ SMBus device id ...................................................................... soc/amd/stoneyridge: Add ST/CZ SMBus device id The SMBus PCI device ID for Stoney wasn't updated when the code was pulled over from hudson. This means that the IOAPIC wasn't being initialized in coreboot. BUG=b:74070580 TEST=Boot Grunt, see IOAPIC init messages in console. Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/include/device/pci_ids.h M src/soc/amd/stoneyridge/sm.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/24930/2 -- To view, visit https://review.coreboot.org/24930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Gerrit-Change-Number: 24930 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add ST/CZ SMBus device id
by Martin Roth (Code Review) 01 Mar '18

01 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/24930 Change subject: soc/amd/stoneyridge: Add ST/CZ SMBus device id ...................................................................... soc/amd/stoneyridge: Add ST/CZ SMBus device id The SMBus PCI device ID for Stoney wasn't updated when the code was pulled over from hudson. This means that the IOAPIC wasn't being initialized in coreboot. BUG=b:74070580 TEST=Boot Grunt, see IOAPIC init messages in console. Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/include/device/pci_ids.h M src/soc/amd/stoneyridge/sm.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/24930/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 16ca1a9..cbdaca1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -442,6 +442,8 @@ #define PCI_DEVICE_ID_AMD_CZ_USB_0 0x7907 #define PCI_DEVICE_ID_AMD_CZ_USB_1 0x7908 #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 +#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B + #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 9456cbf..ca593ce 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -120,8 +120,9 @@ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; + static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_SM, + .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, }; -- To view, visit https://review.coreboot.org/24930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Gerrit-Change-Number: 24930 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit March 2018