Change in coreboot[master]: sb/intel/common: Fix conflicting OIC register definition

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/24924

Change subject: sb/intel/common: Fix conflicting OIC register definition
......................................................................

sb/intel/common: Fix conflicting OIC register definition

Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).

This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.

Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber 
---
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/cougar_canyon2/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/common/rcba.h
9 files changed, 17 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/24924/1

diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index a300ff6..ebcba84 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -96,9 +96,9 @@
    DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);

/* Disable unused devices (board specific) */
    reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 544bb4a..a1bbe34 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -104,9 +104,9 @@
    DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }

static uint8_t *locate_spd(void)
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 3b7c242..12c1114 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -95,9 +95,9 @@
    DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);

/* Disable unused devices (board specific) */
    reg32 = RCBA32(FD);
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index ffa2157..4f7f869 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -101,9 +101,9 @@
    DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);

/* Disable unused devices (board specific) */
    reg32 = RCBA32(FD);
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 96c22ea..47f7ea5 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -158,9 +158,9 @@
    DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);

/* Disable unused devices (board specific) */
    reg32 = RCBA32(FD);
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index d7ed435..ce17068 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -103,9 +103,9 @@
    DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }

static const uint8_t *locate_spd(void)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 265530c..1b5d2ae 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -112,9 +112,9 @@
    DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }

static void setup_sio_gpios(void)
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index 990ff0d..9ce9dc9 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -60,9 +60,9 @@
    DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);

/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
    /* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }

void
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
index 1399fde..ad8285a 100644
--- a/src/southbridge/intel/common/rcba.h
+++ b/src/southbridge/intel/common/rcba.h
@@ -147,6 +147,7 @@
 #define D20IR		0x3160	/* 16bit */
 #define D19IR		0x3168	/* 16bit */

+#define EOIC		0x31fe	/* 16bit */
 #define OIC		0x31ff	/*  8bit */

#define DIR_ROUTE(x, a, b, c, d) \