coreboot-gerrit March 2018

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Change in coreboot[master]: mb/google/poppy: Allow use of optional secondary SPD
by Furquan Shaikh (Code Review) 02 Mar '18

02 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/24972 Change subject: mb/google/poppy: Allow use of optional secondary SPD ...................................................................... mb/google/poppy: Allow use of optional secondary SPD This change adds support for variants to use secondary SPD if required. This enables a variant to have different types of memory supported using the same image. BUG=b:73514687 Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/spd/Makefile.inc M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h 3 files changed, 36 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/24972/1 diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 6bb4076..f9b23e5 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -110,20 +110,21 @@ } } -static uintptr_t mainboard_get_spd_data(enum memory_type type) +static uintptr_t mainboard_get_spd_data(enum memory_type type, bool use_sec_spd) { char *spd_file; size_t spd_file_len; int spd_index; const size_t spd_len = spd_info[type].len; + const char *spd_bin = use_sec_spd ? "sec-spd.bin" : "spd.bin"; spd_index = variant_memory_sku(); assert(spd_index >= 0); printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) die("SPD data not found."); @@ -160,7 +161,7 @@ p.rcomp_resistor_size); memcpy(&mem_cfg->RcompTarget, p.rcomp_target, p.rcomp_target_size); - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type); + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(p.type, p.use_sec_spd); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = spd_info[p.type].len; } diff --git a/src/mainboard/google/poppy/spd/Makefile.inc b/src/mainboard/google/poppy/spd/Makefile.inc index 30e632d..1aaa6eb 100644 --- a/src/mainboard/google/poppy/spd/Makefile.inc +++ b/src/mainboard/google/poppy/spd/Makefile.inc @@ -1,5 +1,20 @@ SPD_BIN = $(obj)/spd.bin +SEC_SPD_BIN = $(obj)/sec-spd.bin + +define gen_spd_bin + for f in $2; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $1 +endef + +define add_spd_to_cbfs + $(eval cbfs-files-y += $1) + $(eval $1-file := $2) + $(eval $1-type := spd) +endef ifeq ($(SPD_SOURCES),) SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) @@ -7,14 +22,20 @@ SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) endif -# Include spd ROM data +# Include SPD ROM data $(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ + $(call gen_spd_bin, $@, $+) -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +$(call add_spd_to_cbfs, spd.bin, $(SPD_BIN)) + +# Add optional secondary SPD ROM data if present +ifneq ($(SEC_SPD_SOURCES),) + +SEC_SPD_DEPS := $(foreach f, $(SEC_SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +$(SEC_SPD_BIN): $(SEC_SPD_DEPS) + $(call gen_spd_bin, $@, $+) + +$(call add_spd_to_cbfs, sec-spd.bin, $(SEC_SPD_BIN)) + +endif diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index c88b99a..3cf11f6 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -45,6 +45,7 @@ size_t rcomp_resistor_size; const void *rcomp_target; size_t rcomp_target_size; + bool use_sec_spd; }; void variant_memory_params(struct memory_params *p); -- To view, visit https://review.coreboot.org/24972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Gerrit-Change-Number: 24972 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/octopus: Add device tree settings
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23846 ) Change subject: mb/google/octopus: Add device tree settings ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22608/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68156/ : SUCCESS -- To view, visit https://review.coreboot.org/23846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Gerrit-Change-Number: 23846 Gerrit-PatchSet: 11 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 20:40:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Add device tree settings
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23846 ) Change subject: mb/google/octopus: Add device tree settings ...................................................................... Patch Set 10: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68155/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22607/ : SUCCESS -- To view, visit https://review.coreboot.org/23846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Gerrit-Change-Number: 23846 Gerrit-PatchSet: 10 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 19:44:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Fizz: Check HDMI HPD and DisplayPort HPD
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23816 ) Change subject: Fizz: Check HDMI HPD and DisplayPort HPD ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22606/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68154/ : SUCCESS -- To view, visit https://review.coreboot.org/23816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Gerrit-Change-Number: 23816 Gerrit-PatchSet: 5 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 19:08:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Fizz: Check HDMI HPD and DisplayPort HPD
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23816 ) Change subject: Fizz: Check HDMI HPD and DisplayPort HPD ...................................................................... Patch Set 4: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68153/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22605/ : SUCCESS -- To view, visit https://review.coreboot.org/23816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Gerrit-Change-Number: 23816 Gerrit-PatchSet: 4 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 19:04:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Fizz: Check HDMI HPD and DisplayPort HPD
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23816 ) Change subject: Fizz: Check HDMI HPD and DisplayPort HPD ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68152/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22604/ : SUCCESS -- To view, visit https://review.coreboot.org/23816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Gerrit-Change-Number: 23816 Gerrit-PatchSet: 3 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 18:35:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/nautilus: Configure PLL reference clock for 24 MHz OSC input
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24910 ) Change subject: mb/google/nautilus: Configure PLL reference clock for 24 MHz OSC input ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22602/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68150/ : SUCCESS -- To view, visit https://review.coreboot.org/24910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a Gerrit-Change-Number: 24910 Gerrit-PatchSet: 3 Gerrit-Owner: Andy Yeh <andy.yeh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Andy Yeh Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 15:24:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Add ASUS Maximus IV GENE-Z
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24971 ) Change subject: mainboard: Add ASUS Maximus IV GENE-Z ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22601/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68149/ : SUCCESS -- To view, visit https://review.coreboot.org/24971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Gerrit-Change-Number: 24971 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 14:44:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Add ASUS Maximus IV GENE-Z
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24971 ) Change subject: mainboard: Add ASUS Maximus IV GENE-Z ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22600/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68148/ : SUCCESS -- To view, visit https://review.coreboot.org/24971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Gerrit-Change-Number: 24971 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 10:58:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Add ASUS Maximus IV GENE-Z
by Tristan Corrick (Code Review) 02 Mar '18

02 Mar '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/24971 Change subject: mainboard: Add ASUS Maximus IV GENE-Z ...................................................................... mainboard: Add ASUS Maximus IV GENE-Z Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with kernel 4.9. This code is based on the output of autoport. Working: - S3 suspend/resume - USB - Gigabit Ethernet - integrated graphics - PCIe - SATA - eSATA - PS/2 port (only a mouse has been tested) - hardware monitor - onboard audio - front panel audio - native raminit (2 x 4GB + 2 x 8GB, DDR3-1333) - native graphics init with libgfxinit - EHCI debug. The debug port is the port closest to the HDMI port. - flashrom, using the internal programmer. Tested with coreboot, untested with the vendor firmware. - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been tested with values different from the default. Untested: - VGA BIOS for graphics init - PCIe graphics - S/PDIF audio Not working: - "clear CMOS" button The CPUTIN sensor on the Super I/O is not connected. The PECI agent is likely connected instead to give CPU temperature readings. However, there does not appear to be enough information in the publicly available datasheets to fully set up the PECI agent. As a result, there is currently no accurate, automatic fan control via the Super I/O. Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- A src/mainboard/asus/maximus_iv_gene-z/Kconfig A src/mainboard/asus/maximus_iv_gene-z/Kconfig.name A src/mainboard/asus/maximus_iv_gene-z/Makefile.inc A src/mainboard/asus/maximus_iv_gene-z/acpi/ec.asl A src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl A src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl A src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c A src/mainboard/asus/maximus_iv_gene-z/board_info.txt A src/mainboard/asus/maximus_iv_gene-z/cmos.default A src/mainboard/asus/maximus_iv_gene-z/cmos.layout A src/mainboard/asus/maximus_iv_gene-z/devicetree.cb A src/mainboard/asus/maximus_iv_gene-z/dsdt.asl A src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads A src/mainboard/asus/maximus_iv_gene-z/gpio.c A src/mainboard/asus/maximus_iv_gene-z/hda_verb.c A src/mainboard/asus/maximus_iv_gene-z/mainboard.c A src/mainboard/asus/maximus_iv_gene-z/romstage.c 17 files changed, 772 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/24971/1 diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig b/src/mainboard/asus/maximus_iv_gene-z/Kconfig new file mode 100644 index 0000000..eacf92e --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig @@ -0,0 +1,67 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_MAXIMUS_IV_GENE_Z + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA1155 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config HAVE_IFD_BIN + bool + default n + +config MAINBOARD_DIR + string + default asus/maximus_iv_gene-z + +config MAINBOARD_PART_NUMBER + string + default "Maximus IV GENE-Z" + +config VGA_BIOS_ID + string + default "8086,0112" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x844d + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +endif diff --git a/src/mainboard/asus/maximus_iv_gene-z/Kconfig.name b/src/mainboard/asus/maximus_iv_gene-z/Kconfig.name new file mode 100644 index 0000000..303c37f --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_MAXIMUS_IV_GENE_Z + bool "Maximus IV GENE-Z" diff --git a/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc new file mode 100644 index 0000000..f81e828 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/ec.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/ec.asl diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl new file mode 100644 index 0000000..adaf51a --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl new file mode 100644 index 0000000..ab41034 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c new file mode 100644 index 0000000..1a584e0 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/asus/maximus_iv_gene-z/board_info.txt b/src/mainboard/asus/maximus_iv_gene-z/board_info.txt new file mode 100644 index 0000000..f21e0da --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/ROG-Republic-Of-Gamers/MAXIMUS_IV_GENEZ/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.default b/src/mainboard/asus/maximus_iv_gene-z/cmos.default new file mode 100644 index 0000000..b94014e --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Spew +gfx_uma_size=64M +hyper_threading=Enable +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout new file mode 100644 index 0000000..9eca23e --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +412 3 e 7 gfx_uma_size + +# coreboot config options: cpu +415 1 e 2 hyper_threading + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb new file mode 100644 index 0000000..1864a7f --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017–2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1043 0x844d inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics + device pci 02.0 on end # VGA controller + + chip southbridge/intel/bd82x6x + register "c2_latency" = "101" + register "gen1_dec" = "0x00000295" # Super I/O HWM + register "p_cnt_throttling_supported" = "1" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x849c + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on # HD audio controller + subsystemid 0x1043 0x84dc + end + device pci 1c.0 on end # PCIe port #1 + device pci 1c.1 off end # PCIe port #2 + device pci 1c.2 off end # PCIe port #3 + device pci 1c.3 off end # PCIe port #4 + device pci 1c.4 on end # PCIe port #5 + device pci 1c.5 on end # PCIe port #6 + device pci 1c.6 on end # PCIe port #7 + device pci 1c.7 off end # PCIe port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0x0200 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl new file mode 100644 index 0000000..60cbde3 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, /* DSDT Revision: ACPI v3.0 */ + "COREv4", /* OEM ID */ + "COREBOOT", /* OEM Table ID */ + 0x20171231 /* OEM Revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) + { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads b/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads new file mode 100644 index 0000000..a8b0a47 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/maximus_iv_gene-z/gpio.c b/src/mainboard/asus/maximus_iv_gene-z/gpio.c new file mode 100644 index 0000000..5a2aabe --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/gpio.c @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c new file mode 100644 index 0000000..3b8eeff --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0889, /* Realtek ALC889 */ + 0x10ec0889, /* Subsystem ID */ + 15, /* Number of entries */ + AZALIA_SUBVENDOR(0x0, 0x10ec0889), + AZALIA_PIN_CFG(0x0, 0x11, 0x414471f0), + AZALIA_PIN_CFG(0x0, 0x12, 0x59a3112e), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0x0, 0x15, 0x01011014), + AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0x0, 0x17, 0x01012012), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19020), + AZALIA_PIN_CFG(0x0, 0x1a, 0x01813040), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214050), + AZALIA_PIN_CFG(0x0, 0x1c, 0x9993114f), + AZALIA_PIN_CFG(0x0, 0x1d, 0x59f00190), + AZALIA_PIN_CFG(0x0, 0x1e, 0x014471f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x41c451f0), + + 0x80862805, /* Intel CougarPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/maximus_iv_gene-z/mainboard.c b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c new file mode 100644 index 0000000..4335086 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c new file mode 100644 index 0000000..75f9972 --- /dev/null +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017–2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/dram/ddr3.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void pch_enable_lpc(void) +{ + pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + static const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/24971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Gerrit-Change-Number: 24971 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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coreboot-gerrit March 2018