coreboot-gerrit March 2018

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Change in coreboot[master]: soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode
by Matt DeVillier (Code Review) 05 Mar '18

05 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24988 Change subject: soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode ...................................................................... soc/intel/braswell: add ACPI for eMMC/SD devices in PCI mode Allows eMMC in PCI mode to be seen/used by Windows. Test: boot Windows installer on google/edgar, observe internal eMMC storage available for installation when eMMC in PCI (vs ACPI) mode. Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/acpi/scc.asl 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/24988/1 diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 95f2244..128edc5 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -77,6 +77,44 @@ } } +Device (PEMC) +{ + Name (_ADR, 0x00100000) // _ADR: Address + + OperationRegion (SDIO, PCI_Config, 0x84, 0x04) + Field (SDIO, WordAcc, NoLock, Preserve) + { + Offset (0x01), + PMEE, 1, + , 6, + PMES, 1 + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\C0EN, 1)) { + Return (0x0) + } + Else + { + Return (0xF) + } + } + + Method (_DSW, 3, NotSerialized) + { + } + + Device (CARD) + { + Name (_ADR, 0x08) + Method (_RMV, 0, NotSerialized) + { + Return (Zero) + } + } +} + Device (SDIO) { Name (_HID, "INT33BB") -- To view, visit https://review.coreboot.org/24988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446 Gerrit-Change-Number: 24988 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/braswell: add LPEA resources to southcluster.asl
by Matt DeVillier (Code Review) 05 Mar '18

05 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24987 Change subject: soc/intel/braswell: add LPEA resources to southcluster.asl ...................................................................... soc/intel/braswell: add LPEA resources to southcluster.asl The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources per Inte'sl CHT Tianocore reference code. Test: boot Windows on google/edgar, observe LPEA device working properly. Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/acpi/southcluster.asl 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/24987/1 diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 19a58d1..f7e3168 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -153,6 +153,12 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) + /* LPEA Memory Region (0x20000000-0x201FFFFF) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x20000000, 0x201FFFFF, 0x00000000, + 0x00200000,,, LMEM) + /* PCI Memory Region (Top of memory-0xfeafffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -166,6 +172,23 @@ 0x00005000,,, TPMR) }) + /* Update LPEA resource area */ + CreateDWordField (MCRS, LMEM._MIN, LMIN) + CreateDWordField (MCRS, LMEM._MAX, LMAX) + CreateDWordField (MCRS, LMEM._LEN, LLEN) + If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One))) + { + Store (LPFW, LMIN) + Store (Add (LMIN, 0x001FFFFF), LMAX) + Store (0x00200000, LLEN) + } + Else + { + Store (Zero, LMIN) + Store (Zero, LMAX) + Store (Zero, LLEN) + } + /* Update PCI resource area */ CreateDwordField(MCRS, PMEM._MIN, PMIN) CreateDwordField(MCRS, PMEM._MAX, PMAX) -- To view, visit https://review.coreboot.org/24987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da Gerrit-Change-Number: 24987 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/braswell: fix PCI resoruce PMAX/PLEN values
by Matt DeVillier (Code Review) 05 Mar '18

05 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24985 Change subject: soc/intel/braswell: fix PCI resoruce PMAX/PLEN values ...................................................................... soc/intel/braswell: fix PCI resoruce PMAX/PLEN values Without PMAX correctly set, the calculation for PLEN is incorrect, leading to a Windows BSOD on boot. Correct PMAX using code from Baytrail SoC, setting PMAX to (CONFIG_MMCONF_BASE_ADDRESS - 1). Test: boot Windows on google/edgar without BSOD. Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/acpi/southcluster.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/24985/1 diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 7617662..19a58d1 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -173,6 +173,7 @@ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) + Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) Return (MCRS) -- To view, visit https://review.coreboot.org/24985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83 Gerrit-Change-Number: 24985 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/braswell: increase LPEA fw allocation to 2MiB
by Matt DeVillier (Code Review) 05 Mar '18

05 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24986 Change subject: soc/intel/braswell: increase LPEA fw allocation to 2MiB ...................................................................... soc/intel/braswell: increase LPEA fw allocation to 2MiB Increase memory allocated for the LPEA firmware from 1MiB to 2MiB to match Intel CHT reference code and fix Windows functionality. Test: boot Windows on google/edgar, observe no error in Device Manager for LPEA audio device due to BAR2 resource allocation. Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/acpi/lpe.asl M src/soc/intel/braswell/lpe.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/24986/1 diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index 6dd73ab..145e608 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -26,7 +26,7 @@ { Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) - Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) + Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2) Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) { LPE_DMA0_IRQ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 58b5a8d..8ec944b 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -38,7 +38,7 @@ * address. Just take 1MiB @ 512MiB. */ #define FIRMWARE_PHYS_BASE (512 << 20) -#define FIRMWARE_PHYS_LENGTH (1 << 20) +#define FIRMWARE_PHYS_LENGTH (2 << 20) #define FIRMWARE_PCI_REG_BASE 0xa8 #define FIRMWARE_PCI_REG_LENGTH 0xac #define FIRMWARE_REG_BASE_C0 0x144000 -- To view, visit https://review.coreboot.org/24986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097 Gerrit-Change-Number: 24986 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: WIP / lib: Add blob_provider interface
by build bot (Jenkins) (Code Review) 05 Mar '18

05 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24942 ) Change subject: WIP / lib: Add blob_provider interface ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68205/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22654/ : SUCCESS -- To view, visit https://review.coreboot.org/24942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f161f680cb36fa6481a8bce6cf233263a828bf7 Gerrit-Change-Number: 24942 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Mar 2018 23:18:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/chromeec: Fix check for UHEPI support
by build bot (Jenkins) (Code Review) 04 Mar '18

04 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24982 ) Change subject: ec/chromeec: Fix check for UHEPI support ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68204/ : SUCCESS -- To view, visit https://review.coreboot.org/24982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7846efb340bc1546b074e8502daf906c444bd146 Gerrit-Change-Number: 24982 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Mar 2018 18:06:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/haswell; sb/intel/lynxpoint: Enable VT-d and X2APIC
by build bot (Jenkins) (Code Review) 04 Mar '18

04 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24983 ) Change subject: nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22652/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68202/ : SUCCESS -- To view, visit https://review.coreboot.org/24983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Gerrit-Change-Number: 24983 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Mar 2018 08:12:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/haswell: Generate ACPI DMAR table
by build bot (Jenkins) (Code Review) 04 Mar '18

04 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24984 ) Change subject: nb/intel/haswell: Generate ACPI DMAR table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22653/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68203/ : SUCCESS -- To view, visit https://review.coreboot.org/24984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc Gerrit-Change-Number: 24984 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Mar 2018 08:10:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/haswell: Generate ACPI DMAR table
by Matt DeVillier (Code Review) 04 Mar '18

04 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24984 Change subject: nb/intel/haswell: Generate ACPI DMAR table ...................................................................... nb/intel/haswell: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c 3 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/24984/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index e032948..9d76ba8 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "haswell.h" +#include <southbridge/intel/lynxpoint/pch.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -69,3 +70,59 @@ return current; } + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; + const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; + + /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ + if (igfx_dev && igfx_dev->enabled && gfxvtbar + && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + /* VTVC0BAR has to be set, enabled, and in 32-bit space */ + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_drhd_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long northbridge_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 97ee363..5f1530a 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -230,6 +230,14 @@ void report_platform_info(void); #endif /* !__SMM__ */ +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#include <device/device.h> + +struct acpi_rsdp; +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, struct acpi_rsdp *rsdp); +#endif + #endif #endif #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 93e711d..bbf1604 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -85,6 +85,7 @@ .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .write_acpi_tables = northbridge_write_acpi_tables, }; static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) -- To view, visit https://review.coreboot.org/24984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc Gerrit-Change-Number: 24984 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: nb/intel/haswell; sb/intel/lynxpoint: Enable VT-d and X2APIC
by Matt DeVillier (Code Review) 04 Mar '18

04 Mar '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24983 Change subject: nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC ...................................................................... nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 5 files changed, 81 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/24983/1 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index a2b0f7f..663812a 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -94,11 +94,39 @@ MCHBAR32(0x5418) = reg32; } +static void haswell_setup_iommu(void) +{ + const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + + if (capid0_a & VTD_DISABLE) + return; + + /* setup BARs: zeroize top 32 bits; set enable bit */ + MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; + MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; + MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; + + /* set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */ + u32 reg32; + reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); + write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), + reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); + /* clear SPCAPCTRL */ + reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; + /* set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */ + write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), + reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); +} + void haswell_early_initialization(int chipset_type) { /* Setup all BARs required for early PCIe and raminit */ haswell_setup_bars(); + /* Setup IOMMU BARs */ + haswell_setup_iommu(); + /* Device Enable: IGD and Mini-HD Audio */ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index b7954e8..97ee363 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -35,6 +35,12 @@ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define GFXVT_BASE_ADDRESS 0xfed90000ULL +#define GFXVT_BASE_SIZE 0x1000 + +#define VTVC0_BASE_ADDRESS 0xfed91000ULL +#define VTVC0_BASE_SIZE 0x1000 + #include <southbridge/intel/lynxpoint/pch.h> /* Everything below this line is ignored in the DSDT */ @@ -88,6 +94,16 @@ #define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) +#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ +#define DMAR_LCKDN (1 << 31) +#define SPCAPCTRL (1 << 25) +#define L3HIT2PEND_DIS (1 << 20) +#define PRSCAPDIS (1 << 2) +#define GLBIOTLBINV (1 << 1) +#define GLBCTXTINV (1 << 0) + /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */ @@ -107,6 +123,8 @@ #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) #define BIOS_RESET_CPL 0x5da8 /* 8bit */ +#define GFXVTBAR 0x5400 +#define VTVC0BAR 0x5410 /* Some power MSRs are also represented in MCHBAR */ #define MCH_PKG_POWER_LIMIT_LO 0x59a0 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 32be916..93e711d 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -289,7 +289,7 @@ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(device_t dev, int *resource_cnt) { unsigned long base_k, size_k; unsigned long touud_k; @@ -331,7 +331,7 @@ * The resource index starts low and should not meet or exceed * PCI_BASE_ADDRESS_0. */ - index = 0; + index = *resource_cnt; /* 0 - > 0xa0000 */ base_k = 0; @@ -379,18 +379,31 @@ CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif + *resource_cnt = index; } static void mc_read_resources(device_t dev) { + int index = 0; + const bool vtd_capable = + !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + /* Read standard PCI resources. */ pci_dev_read_resources(dev); /* Add all fixed MMIO resources. */ mc_add_fixed_mmio_resources(dev); + /* Add VT-d MMIO resources if capable */ + if (vtd_capable) { + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, + GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, + VTVC0_BASE_SIZE / KiB); + } + /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); + mc_add_dram_resources(dev, &index); } static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a5c2351..03a77d9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -51,6 +51,10 @@ { u32 reg32; + /* Assign unique bus/dev/fn for I/O APIC */ + pci_write_config16(dev, LPC_IBDF, + PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); + /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); @@ -396,9 +400,15 @@ RCBA32_OR(0x33c8, (1 << 15)); } -static void enable_hpet(void) +static void enable_hpet(struct device *const dev) { u32 reg32; + size_t i; + + /* Assign unique bus/dev/fn for each HPET */ + for (i = 0; i < 8; ++i) + pci_write_config16(dev, LPC_HnBDF(i), + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); @@ -570,7 +580,7 @@ isa_dma_init(); /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); + enable_hpet(dev); setup_i8259(); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index af9e954..f14a339 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -282,6 +282,8 @@ #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ +#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ +#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -670,6 +672,11 @@ #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0) +#define PCH_IOAPIC_PCI_BUS 250 +#define PCH_IOAPIC_PCI_SLOT 31 +#define PCH_HPET_PCI_BUS 250 +#define PCH_HPET_PCI_SLOT 15 + /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) -- To view, visit https://review.coreboot.org/24983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Gerrit-Change-Number: 24983 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit March 2018