coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Remove MCFG constants
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24975 ) Change subject: soc/intel/skylake: Remove MCFG constants ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22615/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68165/ : SUCCESS -- To view, visit https://review.coreboot.org/24975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Gerrit-Change-Number: 24975 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 23:14:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/fizz: Skip FSP init for UART 0
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24973 ) Change subject: mb/google/fizz: Skip FSP init for UART 0 ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/68163/ : SUCCESS -- To view, visit https://review.coreboot.org/24973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Gerrit-Change-Number: 24973 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 23:13:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: Fix MCFG end bus number
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24974 ) Change subject: soc/intel: Fix MCFG end bus number ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22616/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68164/ : SUCCESS -- To view, visit https://review.coreboot.org/24974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Gerrit-Change-Number: 24974 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 23:11:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Remove MCFG constants
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24975 ) Change subject: soc/intel/skylake: Remove MCFG constants ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22614/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68162/ : SUCCESS -- To view, visit https://review.coreboot.org/24975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Gerrit-Change-Number: 24975 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 23:06:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: Fix MCFG end bus number
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24974 ) Change subject: soc/intel: Fix MCFG end bus number ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22613/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68161/ : SUCCESS -- To view, visit https://review.coreboot.org/24974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Gerrit-Change-Number: 24974 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 23:04:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/fizz: Skip FSP init for UART 0
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24973 ) Change subject: mb/google/fizz: Skip FSP init for UART 0 ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68160/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22612/ : SUCCESS -- To view, visit https://review.coreboot.org/24973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Gerrit-Change-Number: 24973 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 23:00:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Remove MCFG constants
by Duncan Laurie (Code Review) 02 Mar '18

02 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/24975 Change subject: soc/intel/skylake: Remove MCFG constants ...................................................................... soc/intel/skylake: Remove MCFG constants The MMCONF base address and length are set in Kconfig so it does not need to be redefined by the SOC as the code can just use the Kconfig variable directly. Tested on a fizz board to ensure MCFG is still created properly. Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/iomap.h 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/24975/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 202d686..2e0d87a 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -210,7 +210,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); return current; } diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 0a573ac..ac0c78b 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -22,9 +22,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -- To view, visit https://review.coreboot.org/24975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Gerrit-Change-Number: 24975 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel: Fix MCFG end bus number
by Duncan Laurie (Code Review) 02 Mar '18

02 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/24974 Change subject: soc/intel: Fix MCFG end bus number ...................................................................... soc/intel: Fix MCFG end bus number The ACPI MCFG table is generated with a static end bus number of 255, which expects that the reserved range in E820 is 256MB. However the actual MCFG range is configurable with Kconfig, so these two values may not match when the OS tries to determine the range: PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!) acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Instead of forcing the end bus number to be 255 use the Kconfig value to set it based on the current configuration. Tested on a fizz device to ensure that the kernel no longer complains: PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/skylake/acpi.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/24974/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 3db96a0..bf4003d 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -36,7 +36,7 @@ /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ current += acpi_create_mcfg_mmconfig((void *)current, CONFIG_MMCONF_BASE_ADDRESS, 0, 0, - 255); + (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); return current; } diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6e1a886..202d686 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -210,7 +210,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + MCFG_BASE_ADDRESS, 0, 0, + (CONFIG_SA_PCIEX_LENGTH >> 20) - 1); return current; } -- To view, visit https://review.coreboot.org/24974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Gerrit-Change-Number: 24974 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: mb/google/fizz: Skip FSP init for UART 0
by Duncan Laurie (Code Review) 02 Mar '18

02 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/24973 Change subject: mb/google/fizz: Skip FSP init for UART 0 ...................................................................... mb/google/fizz: Skip FSP init for UART 0 The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. Coreboot it setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device. The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots. Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/24973/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 5eeb03c..e7654cf 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -304,7 +304,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" -- To view, visit https://review.coreboot.org/24973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Gerrit-Change-Number: 24973 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: mb/google/poppy: Allow use of optional secondary SPD
by build bot (Jenkins) (Code Review) 02 Mar '18

02 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/24972 ) Change subject: mb/google/poppy: Allow use of optional secondary SPD ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/68159/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22611/ : SUCCESS -- To view, visit https://review.coreboot.org/24972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Gerrit-Change-Number: 24972 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Mar 2018 22:50:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018