Change in coreboot[master]: soc/intel/braswell: fix PCI resoruce PMAX/PLEN values

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24985

Change subject: soc/intel/braswell: fix PCI resoruce PMAX/PLEN values
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soc/intel/braswell: fix PCI resoruce PMAX/PLEN values

Without PMAX correctly set, the calculation for PLEN is incorrect,
leading to a Windows BSOD on boot.  Correct PMAX using code from
Baytrail SoC, setting PMAX to (CONFIG_MMCONF_BASE_ADDRESS - 1).

Test: boot Windows on google/edgar without BSOD.

Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/braswell/acpi/southcluster.asl
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/24985/1

diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 7617662..19a58d1 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -173,6 +173,7 @@

/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
    Store (\TOLM, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
    Add (Subtract (PMAX, PMIN), 1, PLEN)

Return (MCRS)