coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/stoneyridge: Add TPM Configuration
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25027 ) Change subject: soc/amd/stoneyridge: Add TPM Configuration ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22796/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68362/ : SUCCESS -- To view, visit https://review.coreboot.org/25027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 Gerrit-Change-Number: 25027 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 23:04:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Function to Enable ACPI MMIO
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25025 ) Change subject: soc/amd/stoneyridge: Function to Enable ACPI MMIO ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22794/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68360/ : SUCCESS -- To view, visit https://review.coreboot.org/25025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 Gerrit-Change-Number: 25025 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 23:00:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Add TPM Configuration
by Garrett Kirkendall (Code Review) 07 Mar '18

07 Mar '18

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25027 Change subject: soc/amd/stoneyridge: Add TPM Configuration ...................................................................... soc/amd/stoneyridge: Add TPM Configuration * Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy TPM IO 0x7f-0x7e and 0xef-0xee * Modify sb_tpm_decode_spi to additionally call sb_tpm_decode. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 Signed-off-by: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25027/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cccdf97..0483340 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -186,6 +186,11 @@ #define LPC_MISC_CONTROL_BITS 0x78 #define LPC_NOHOG BIT(0) + +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + #define LPC_WIDEIO2_GENERIC_PORT 0x90 /* @@ -357,6 +362,7 @@ void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void sb_set_readspeed(u16 norm, u16 fast); +void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 367c565..adb3fde 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -470,8 +470,34 @@ & ~SPI_READ_MODE_MASK) | mode); } +/* + * Enable FCH to decode TPM associated Memory and IO regions + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + */ +void sb_tpm_decode(void) +{ + /* Enable TPM decoding to FCH */ + u32 value = pci_read_config32(SOC_LPC_DEV, + LPC_TRUSTED_PLATFORM_MODULE); + value |= (TPM_12_EN | TPM_LEGACY_EN); + pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); +} + +/* + * Enable FCH to decode TPM associated Memory and IO regions to SPI + * + * This would be used if TPM is connectd to SPI bus like Kahlee. + * Assumes SPI address space is already configured via a call to sb_spibase(). + */ void sb_tpm_decode_spi(void) { + /* Enable TPM decoding to FCH */ + sb_tpm_decode(); + + /* Route TPM accesses to SPI */ u32 spibase = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase -- To view, visit https://review.coreboot.org/25027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 Gerrit-Change-Number: 25027 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Support I2C device enable
by Garrett Kirkendall (Code Review) 07 Mar '18

07 Mar '18

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25026 Change subject: soc/amd/stoneyridge: Support I2C device enable ...................................................................... soc/amd/stoneyridge: Support I2C device enable Add function to enable the stoneyridge four I2C engines. This is in preparation of moving the AGESA calls out of the bootblock. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826 Signed-off-by: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25026/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 88403e6..cccdf97 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -344,6 +344,7 @@ void sb_enable_rom(void); void configure_stoneyridge_uart(void); +void configure_stoneyridge_i2c(void); void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); void sb_enable(device_t dev); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c591c69..367c565 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -320,6 +320,26 @@ } while (!status); } +void configure_stoneyridge_i2c(void) +{ + bool status; + + /* Power on the I2C devices */ + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0); + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1); + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2); + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3); + + /* Wait for the I2C devices to indicate power and clock OK */ + do { + udelay(100); + status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); + status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); + status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); + status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + } while (!status); +} + void sb_pci_port80(void) { u8 byte; -- To view, visit https://review.coreboot.org/25026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826 Gerrit-Change-Number: 25026 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Function to Enable ACPI MMIO
by Garrett Kirkendall (Code Review) 07 Mar '18

07 Mar '18

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25025 Change subject: soc/amd/stoneyridge: Function to Enable ACPI MMIO ...................................................................... soc/amd/stoneyridge: Function to Enable ACPI MMIO * Add definitions for needed registers in southbridge.h * Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to 0xfed81ffff. Will be called by a later commit. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build boot Grunt Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 Signed-off-by: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25025/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index acdaa8a..88403e6 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -32,6 +32,8 @@ #define PSP_MAILBOX_BAR_EN 0x10 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_ISA_CONTROL 0x04 +#define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_STPCLK_RETRY BIT(24) @@ -349,6 +351,7 @@ void southbridge_init(void *chip_info); void sb_lpc_port80(void); void sb_lpc_decode(void); +void sb_acpi_mmio_decode(void); void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 57bd3f0..c591c69 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -367,6 +367,18 @@ pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); } +void sb_acpi_mmio_decode(void) +{ + uint8_t byte; + + /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ + outb(PM_ISA_CONTROL, PM_INDEX); + byte = inb(PM_DATA); + byte |= MMIO_EN; + outb(PM_ISA_CONTROL, PM_INDEX); + outb(byte, PM_DATA); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; -- To view, visit https://review.coreboot.org/25025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 Gerrit-Change-Number: 25025 Gerrit-PatchSet: 1 Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com>

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Change in coreboot[master]: mb/google/octopus: Add gpio configs for communities
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23799 ) Change subject: mb/google/octopus: Add gpio configs for communities ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22793/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68359/ : SUCCESS -- To view, visit https://review.coreboot.org/23799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Gerrit-Change-Number: 23799 Gerrit-PatchSet: 14 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 22:55:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Timestamps: Add option to print timestamps to debug console
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25024 ) Change subject: Timestamps: Add option to print timestamps to debug console ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22791/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68357/ : SUCCESS -- To view, visit https://review.coreboot.org/25024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie6e6a4877fefec45fb987ceae7d42de6ce768159 Gerrit-Change-Number: 25024 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 22:50:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/octopus: Add gpio configs for communities
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23799 ) Change subject: mb/google/octopus: Add gpio configs for communities ...................................................................... Patch Set 13: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/68358/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22792/ : SUCCESS -- To view, visit https://review.coreboot.org/23799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Gerrit-Change-Number: 23799 Gerrit-PatchSet: 13 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 22:49:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Timestamps: Add option to print timestamps to debug console
by Martin Roth (Code Review) 07 Mar '18

07 Mar '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/25024 Change subject: Timestamps: Add option to print timestamps to debug console ...................................................................... Timestamps: Add option to print timestamps to debug console Prints the timestamp name and value to the debug console if enabled in Kconfig. Change-Id: Ie6e6a4877fefec45fb987ceae7d42de6ce768159 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/Kconfig M src/lib/timestamp.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/25024/1 diff --git a/src/Kconfig b/src/Kconfig index 692a5b7..99a704d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -185,6 +185,13 @@ Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process. +config TIMESTAMPS_ON_CONSOLE + bool "Print the timestamp values on the console" + default n + depends on COLLECT_TIMESTAMPS + help + Print the timestamps to the debug console if enabled at level spew. + config USE_BLOBS bool "Allow use of binary-only repository" help diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 149b8b8..5a575a5 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -154,6 +154,19 @@ return ts_table; } +static const char *ts_name_unknown = "Unknown timestamp ID"; +static const char *timestamp_name(enum timestamp_id id) +{ + int i; + + for (i = 0; i < sizeof(timestamp_ids)/sizeof(timestamp_ids[0]); i++) { + if (timestamp_ids[i].id == id) + return timestamp_ids[i].name; + } + + return ts_name_unknown; +} + static void timestamp_add_table_entry(struct timestamp_table *ts_table, enum timestamp_id id, uint64_t ts_time) { @@ -166,6 +179,10 @@ tse->entry_id = id; tse->entry_stamp = ts_time - ts_table->base_time; + if (IS_ENABLED(CONFIG_TIMESTAMPS_ON_CONSOLE)) + printk(BIOS_SPEW, "%s: %ld\n", timestamp_name(id), + (unsigned long)ts_time); + if (ts_table->num_entries == ts_table->max_entries) printk(BIOS_ERR, "ERROR: Timestamp table full\n"); } -- To view, visit https://review.coreboot.org/25024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie6e6a4877fefec45fb987ceae7d42de6ce768159 Gerrit-Change-Number: 25024 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: google/scarlet: Adjust K&D power sequence from software
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25023 ) Change subject: google/scarlet: Adjust K&D power sequence from software ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22790/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68356/ : SUCCESS -- To view, visit https://review.coreboot.org/25023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6 Gerrit-Change-Number: 25023 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Matthias Kaehlcke <mka(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 21:42:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit March 2018