coreboot-gerrit March 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add memory detection logic
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25000 ) Change subject: mb/google/poppy/variants/nami: Add memory detection logic ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22783/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68349/ : SUCCESS -- To view, visit https://review.coreboot.org/25000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Gerrit-Change-Number: 25000 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 19:02:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: timestamps: Add timestamps around the vbios load & init
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25018 ) Change subject: timestamps: Add timestamps around the vbios load & init ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22782/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68348/ : SUCCESS -- To view, visit https://review.coreboot.org/25018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e Gerrit-Change-Number: 25018 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 18:04:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add memory detection logic
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25000 ) Change subject: mb/google/poppy/variants/nami: Add memory detection logic ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22781/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68347/ : SUCCESS -- To view, visit https://review.coreboot.org/25000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Gerrit-Change-Number: 25000 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 17:31:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25021 ) Change subject: mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22780/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68346/ : SUCCESS -- To view, visit https://review.coreboot.org/25021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35 Gerrit-Change-Number: 25021 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 17:24:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1
by Daniel Kurtz (Code Review) 07 Mar '18

07 Mar '18

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/25021 to review the following change. Change subject: mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1 ...................................................................... mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1 This #define tells superio.asl to add a "PNP0501" "Plug and Play 16550A-compatible COM port" entry to kahlee's ACPI tables. The EC on kahlee boards do not provide a "Serial Port 1" that should be exposed via ACPI to the OS. In fact, this entry confuses the kernel and in some cases can cause it to try to redirect output to a non existing port. BUG=b:74200887 TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and "earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel command line, and with an image with serial console enabled. => System boots with (kernel) serial console enabled, starting from 0.00 (earlycon), with no gaps in its output, and serial console also allows logging in. Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35 Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/25021/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h index 16b2669..e93c2dd 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h @@ -67,6 +67,5 @@ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -#define SIO_EC_ENABLE_COM1 /* Enable Serial Port 1 */ #endif -- To view, visit https://review.coreboot.org/25021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35 Gerrit-Change-Number: 25021 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org>

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Change in coreboot[master]: [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25020 ) Change subject: [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22779/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68345/ : SUCCESS -- To view, visit https://review.coreboot.org/25020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic265afc2b27c261ebdde42337c9dcc7c1ccc84f3 Gerrit-Change-Number: 25020 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 16:38:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1
by Nico Huber (Code Review) 07 Mar '18

07 Mar '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25020 Change subject: [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1 ...................................................................... [UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1 LPB1 in NVS is never set by coreboot. Drop this copy-pasta and see if it's less confusing for the OS. Change-Id: Ic265afc2b27c261ebdde42337c9dcc7c1ccc84f3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/braswell/acpi/device_nvs.asl M src/soc/intel/braswell/acpi/lpe.asl M src/soc/intel/braswell/include/soc/device_nvs.h M src/soc/intel/braswell/lpe.c 4 files changed, 3 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/25020/1 diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index 0d4bc3c..d67e71f 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -75,7 +75,7 @@ C0B1, 32, /* MMC BAR1 */ C1B1, 32, /* SDIO BAR1 */ C2B1, 32, /* SD Card BAR1 */ -LPB1, 32, /* LPE BAR1 */ +RSV1, 32, /* reserved */ /* Extra */ diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index 145e608..c1369b0 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -20,12 +20,10 @@ Name (_CID, "808622A8") Name (_UID, 1) Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8") - Name (_PR0, Package () { PLPE }) Name (RBUF, ResourceTemplate() { Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) - Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2) Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) { @@ -59,10 +57,6 @@ CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) Store (\LPB0, BAS0) - /* Update BAR1 from NVS */ - CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) - Store (\LPB1, BAS1) - /* Update LPE FW from NVS */ CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) Store (\LPFW, BAS2) @@ -84,31 +78,4 @@ Return (0x0) } } - - OperationRegion (KEYS, SystemMemory, LPB1, 0x100) - Field (KEYS, DWordAcc, NoLock, WriteAsZeros) - { - Offset (0x84), - PSAT, 32, - } - - PowerResource (PLPE, 0, 0) - { - Method (_STA) - { - Return (1) - } - - Method (_OFF) - { - Or (PSAT, 0x00000003, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - - Method (_ON) - { - And (PSAT, 0xfffffffc, PSAT) - Or (PSAT, 0x00000000, PSAT) - } - } } diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 268655e..a97ac54 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -56,7 +56,7 @@ /* BAR 0 */ u32 lpss_bar1[14]; u32 scc_bar1[3]; - u32 lpe_bar1; + u32 reserved1; /* Extra */ u32 lpe_fw; /* LPE Firmware */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 8ec944b..b65c158 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -75,10 +75,8 @@ return; } - /* Save BAR0, BAR1, and firmware base to ACPI NVS */ + /* Save BAR0 and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */ - /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */ assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ -- To view, visit https://review.coreboot.org/25020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic265afc2b27c261ebdde42337c9dcc7c1ccc84f3 Gerrit-Change-Number: 25020 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: smbios: Extend Baseboard (or Module) Information (type2)
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23842 ) Change subject: smbios: Extend Baseboard (or Module) Information (type2) ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22777/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68344/ : SUCCESS -- To view, visit https://review.coreboot.org/23842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9fe1c4fe70c66f8a7fcc75b93672421ae808bf1b Gerrit-Change-Number: 23842 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 15:37:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/scaleway/tagada: Implement console loglevel override using bmcInfo
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23814 ) Change subject: mb/scaleway/tagada: Implement console loglevel override using bmcInfo ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22774/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68341/ : SUCCESS -- To view, visit https://review.coreboot.org/23814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0093cfafe7eaa4a4381e67c9b871fdf28abc470d Gerrit-Change-Number: 23814 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 07 Mar 2018 15:07:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/scaleway/tagada: populate smbios information
by build bot (Jenkins) (Code Review) 07 Mar '18

07 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23843 ) Change subject: mb/scaleway/tagada: populate smbios information ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/22778/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/68343/ : SUCCESS -- To view, visit https://review.coreboot.org/23843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053 Gerrit-Change-Number: 23843 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Mar 2018 15:04:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit March 2018