coreboot-gerrit December 2018

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Change in ...coreboot[master]: src/northbridge: Get rid of device_t
by build bot (Jenkins) (Code Review) 05 Dec '18

05 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30046 ) Change subject: src/northbridge: Get rid of device_t ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30046/2/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/30046/2/src/northbridge/amd/amdmct/mct_ddr3… PS2, Line 152: static uint32_t read_amd_dct_index_register_dct(struct device *dev, uint8_t node, line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Gerrit-Change-Number: 30046 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Dec 2018 10:46:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/northbridge: Get rid of device_t
by build bot (Jenkins) (Code Review) 05 Dec '18

05 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30046 ) Change subject: src/northbridge: Get rid of device_t ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30046/1/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/30046/1/src/northbridge/amd/amdmct/mct_ddr3… PS1, Line 152: static uint32_t read_amd_dct_index_register_dct(struct device *dev, uint8_t node, line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Gerrit-Change-Number: 30046 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Dec 2018 10:05:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Get rid of device_t
by HAOUAS Elyes (Code Review) 05 Dec '18

05 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30047 Change subject: src: Get rid of device_t ...................................................................... src: Get rid of device_t Use of device_t is deprecated. Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/arch/pci_ops.h M src/arch/arm64/include/arch/pci_ops.h M src/arch/mips/include/arch/pci_ops.h M src/arch/x86/include/arch/io.h M src/device/pci_early.c M src/include/device/device.h M src/include/device/pci_ops.h M src/include/device/smbus.h M src/include/reg_script.h M src/lib/reg_script.c 10 files changed, 87 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30047/1 diff --git a/src/arch/arm/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h index 2e2661b..533ad80 100644 --- a/src/arch/arm/include/arch/pci_ops.h +++ b/src/arch/arm/include/arch/pci_ops.h @@ -21,9 +21,6 @@ typedef u32 pci_devfn_t; #ifdef __SIMPLE_DEVICE__ -// FIXME: Use of device_t is deprecated -typedef pci_devfn_t device_t; - u8 pci_read_config8(pci_devfn_t dev, unsigned int where); u16 pci_read_config16(pci_devfn_t dev, unsigned int where); u32 pci_read_config32(pci_devfn_t dev, unsigned int where); diff --git a/src/arch/arm64/include/arch/pci_ops.h b/src/arch/arm64/include/arch/pci_ops.h index e6d5206..32e7601 100644 --- a/src/arch/arm64/include/arch/pci_ops.h +++ b/src/arch/arm64/include/arch/pci_ops.h @@ -21,9 +21,6 @@ typedef u32 pci_devfn_t; #ifdef __SIMPLE_DEVICE__ -// FIXME: Use of device_t is deprecated -typedef pci_devfn_t device_t; - u8 pci_read_config8(pci_devfn_t dev, unsigned int where); u16 pci_read_config16(pci_devfn_t dev, unsigned int where); u32 pci_read_config32(pci_devfn_t dev, unsigned int where); diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h index 5fef126..f57befa 100644 --- a/src/arch/mips/include/arch/pci_ops.h +++ b/src/arch/mips/include/arch/pci_ops.h @@ -21,9 +21,6 @@ typedef u32 pci_devfn_t; #ifdef __SIMPLE_DEVICE__ -// FIXME: Use of device_t is deprecated -typedef pci_devfn_t device_t; - u8 pci_read_config8(pci_devfn_t dev, unsigned int where); u16 pci_read_config16(pci_devfn_t dev, unsigned int where); u32 pci_read_config32(pci_devfn_t dev, unsigned int where); diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 1b0fdb0..f47973e 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -18,8 +18,6 @@ #include <stdint.h> #include <rules.h> -/* FIXME: Sources for romstage still use device_t. */ -/* Use pci_devfn_t or pnp_devfn_t instead */ typedef u32 pci_devfn_t; typedef u32 pnp_devfn_t; @@ -256,10 +254,6 @@ #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -/* FIXME: Sources for romstage still use device_t. */ -/* Use pci_devfn_t or pnp_devfn_t instead */ -typedef u32 device_t; - /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write * memory above 4G, We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 6baebe0..ff481bc 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -13,14 +13,12 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> #include <delay.h> -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; @@ -68,12 +66,16 @@ { return pci_find_next_capability(dev, cap, 0); } -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ #if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) -static void pci_bridge_reset_secondary(device_t p2p_bridge) +#ifdef __SIMPLE_DEVICE__ +static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) +#else +static void pci_bridge_reset_secondary(struct device *p2p_bridge) +#endif { u16 reg16; @@ -90,7 +92,11 @@ pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); } -static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +#ifdef __SIMPLE_DEVICE__ +static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary) +#else +static void pci_bridge_set_secondary(struct device *p2p_bridge, u8 secondary) +#endif { /* Disable config transaction forwarding. */ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); @@ -100,7 +106,11 @@ pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); } -static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +#ifdef __SIMPLE_DEVICE__ +static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size) +#else +static void pci_bridge_set_mmio(struct device *p2p_bridge, u32 base, u32 size) +#endif { u16 reg16; diff --git a/src/include/device/device.h b/src/include/device/device.h index 6713c94..c2f8ece 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -14,14 +14,9 @@ #include <rules.h> #include <device/resource.h> #include <device/path.h> - -struct device; - -#ifndef __SIMPLE_DEVICE__ -typedef struct device *device_t; -#endif #include <arch/io.h> +struct device; struct pci_operations; struct pci_bus_operations; struct i2c_bus_operations; diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 5e60e8d..54284f5 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -15,33 +15,49 @@ #endif -/* - * Use device_t here as the functions are to be used with either - * __SIMPLE_DEVICE__ defined or undefined. - */ +#ifdef __SIMPLE_DEVICE__ static __always_inline -void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +void pci_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) +#else +static __always_inline +void pci_or_config8(struct device *dev, unsigned int where, u8 ormask) +#endif { u8 value = pci_read_config8(dev, where); pci_write_config8(dev, where, value | ormask); } +#ifdef __SIMPLE_DEVICE__ static __always_inline -void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +void pci_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) +#else +static __always_inline +void pci_or_config16(struct device *dev, unsigned int where, u16 ormask) +#endif { u16 value = pci_read_config16(dev, where); pci_write_config16(dev, where, value | ormask); } +#ifdef __SIMPLE_DEVICE__ static __always_inline -void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +void pci_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) +#else +static __always_inline +void pci_or_config32(struct device *dev, unsigned int where, u32 ormask) +#endif { u32 value = pci_read_config32(dev, where); pci_write_config32(dev, where, value | ormask); } +#ifdef __SIMPLE_DEVICE__ static __always_inline -void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +void pci_update_config8(pci_devfn_t dev, int reg, u8 mask, u8 or) +#else +static __always_inline +void pci_update_config8(struct device *dev, int reg, u8 mask, u8 or) +#endif { u8 reg8; @@ -51,8 +67,13 @@ pci_write_config8(dev, reg, reg8); } +#ifdef __SIMPLE_DEVICE__ static __always_inline -void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +void pci_update_config16(pci_devfn_t dev, int reg, u16 mask, u16 or) +#else +static __always_inline +void pci_update_config16(struct device *dev, int reg, u16 mask, u16 or) +#endif { u16 reg16; @@ -62,8 +83,13 @@ pci_write_config16(dev, reg, reg16); } +#ifdef __SIMPLE_DEVICE__ static __always_inline -void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +void pci_update_config32(pci_devfn_t dev, int reg, u32 mask, u32 or) +#else +static __always_inline +void pci_update_config32(struct device *dev, int reg, u32 mask, u32 or) +#endif { u32 reg32; diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 639e938..621300d 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -51,9 +51,13 @@ return i2c_dev_writeb_at(dev, addr, val); } -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); -int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); - +#ifdef __SIMPLE_DEVICE__ +int smbus_block_read(pci_devfn_t dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(pci_devfn_t dev, u8 cmd, u8 bytes, const u8 *buffer); +#else +int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); +#endif #if IS_ENABLED(CONFIG_SMBUS_HAS_AUX_CHANNELS) void smbus_switch_to_channel(uint8_t channel_number); uint8_t smbus_get_current_channel(void); diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 116dd92..28fc82d 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -30,8 +30,6 @@ * are employed: * - Chaining of tables that allow runtime tables to chain to compile-time * tables. - * - Notion of current device (device_t) being worked on. This allows for - * PCI config, io, and mmio on a particular device's resources. * * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push * and pop of the context. A chained reg_script inherits the previous @@ -87,13 +85,21 @@ union { uint32_t id; const struct reg_script *next; - device_t dev; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif unsigned int res_index; }; }; struct reg_script_context { - device_t dev; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif struct resource *res; const struct reg_script *step; uint8_t display_state; /* Only modified by reg_script_run_step */ @@ -437,6 +443,10 @@ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) void reg_script_run(const struct reg_script *script); -void reg_script_run_on_dev(device_t dev, const struct reg_script *step); +#ifdef __SIMPLE_DEVICE__ +void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step); +#else +void reg_script_run_on_dev(struct device *dev, const struct reg_script *step); +#endif #endif /* REG_SCRIPT_H */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e84c137..926a659 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -40,8 +40,13 @@ #define EMPTY_DEV NULL #endif +#ifdef __SIMPLE_DEVICE__ static inline void reg_script_set_dev(struct reg_script_context *ctx, - device_t dev) + pci_devfn_t dev) +#else +static inline void reg_script_set_dev(struct reg_script_context *ctx, + struct device *dev) +#endif { ctx->dev = dev; ctx->res = NULL; @@ -677,7 +682,11 @@ reg_script_run_with_context(&ctx); } -void reg_script_run_on_dev(device_t dev, const struct reg_script *step) +#ifdef __SIMPLE_DEVICE__ +void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step) +#else +void reg_script_run_on_dev(struct device *dev, const struct reg_script *step) +#endif { struct reg_script_context ctx; -- To view, visit https://review.coreboot.org/c/coreboot/+/30047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f Gerrit-Change-Number: 30047 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/northbridge: Get rid of device_t
by HAOUAS Elyes (Code Review) 05 Dec '18

05 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30046 Change subject: src/northbridge: Get rid of device_t ...................................................................... src/northbridge: Get rid of device_t Use of device_t is deprecated. Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/via/vx900/pci_util.c 2 files changed, 54 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30046/1 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index eb39c81..46bfdd0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -67,7 +67,14 @@ return s3nv_region.region.offset; } -static uint32_t read_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t reg) { +#ifdef __SIMPLE_DEVICE__ +static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, + uint32_t reg) +#else +static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct, + uint32_t reg) +#endif +{ if (is_fam15h()) { uint32_t dword; #ifdef __PRE_RAM__ @@ -89,7 +96,14 @@ return pci_read_config32(dev, reg); } -static void write_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) { +#ifdef __SIMPLE_DEVICE__ +static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, + uint32_t reg, uint32_t value) +#else +static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct, + uint32_t reg, uint32_t value) +#endif +{ if (is_fam15h()) { uint32_t dword; #ifdef __PRE_RAM__ @@ -111,7 +125,13 @@ pci_write_config32(dev, reg, value); } -static uint32_t read_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index) +#ifdef __SIMPLE_DEVICE__ +static uint32_t read_amd_dct_index_register(pci_devfn_t dev, + uint32_t index_ctl_reg, uint32_t index) +#else +static uint32_t read_amd_dct_index_register(struct device *dev, + uint32_t index_ctl_reg, uint32_t index) +#endif { uint32_t dword; @@ -125,7 +145,13 @@ return dword; } -static uint32_t read_amd_dct_index_register_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index) +#ifdef __SIMPLE_DEVICE__ +static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, + uint8_t dct, uint32_t index_ctl_reg, uint32_t index) +#else +static uint32_t read_amd_dct_index_register_dct(struct device *dev, uint8_t node, + uint8_t dct, uint32_t index_ctl_reg, uint32_t index) +#endif { if (is_fam15h()) { uint32_t dword; diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 1674e85..08e2b54 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -16,7 +16,11 @@ #include "vx900.h" -void dump_pci_device(device_t dev) +#ifdef __SIMPLE_DEVICE__ +void dump_pci_device(pci_devfn_t dev) +#else +void dump_pci_device(struct device *dev) +#endif { int i; for (i = 0; i <= 0xff; i++) { @@ -35,8 +39,13 @@ } } -void pci_mod_config8(device_t dev, unsigned int where, - uint8_t clr_mask, uint8_t set_mask) +#ifdef __SIMPLE_DEVICE__ +void pci_mod_config8(pci_devfn_t dev, unsigned int where, uint8_t clr_mask, + uint8_t set_mask) +#else +void pci_mod_config8(struct device *dev, unsigned int where, uint8_t clr_mask, + uint8_t set_mask) +#endif { uint8_t reg8 = pci_read_config8(dev, where); reg8 &= ~clr_mask; @@ -44,8 +53,13 @@ pci_write_config8(dev, where, reg8); } -void pci_mod_config16(device_t dev, unsigned int where, +#ifdef __SIMPLE_DEVICE__ +void pci_mod_config16(pci_devfn_t dev, unsigned int where, uint16_t clr_mask, uint16_t set_mask) +#else +void pci_mod_config16(struct device *dev, unsigned int where, + uint16_t clr_mask, uint16_t set_mask) +#endif { uint16_t reg16 = pci_read_config16(dev, where); reg16 &= ~clr_mask; @@ -53,8 +67,13 @@ pci_write_config16(dev, where, reg16); } -void pci_mod_config32(device_t dev, unsigned int where, +#ifdef __SIMPLE_DEVICE__ +void pci_mod_config32(pci_devfn_t dev, unsigned int where, uint32_t clr_mask, uint32_t set_mask) +#else +void pci_mod_config32(struct device *dev, unsigned int where, + uint32_t clr_mask, uint32_t set_mask) +#endif { uint32_t reg32 = pci_read_config32(dev, where); reg32 &= ~clr_mask; -- To view, visit https://review.coreboot.org/c/coreboot/+/30046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Gerrit-Change-Number: 30046 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/southbridge: Get rid of device_t
by HAOUAS Elyes (Code Review) 05 Dec '18

05 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30045 Change subject: src/southbridge: Get rid of device_t ...................................................................... src/southbridge: Get rid of device_t Use of device_t is deprecated. Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/sr5650/cmn.h M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/usb_xhci.c 4 files changed, 166 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30045/1 diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 859e15d..126b786 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,30 +34,54 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) +#else +static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) +#endif { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); } -static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, + u32 data) +#else +static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index, + u32 data) +#endif { pci_write_config32(dev, index_reg, index); pci_write_config32(dev, index_reg + 0x4, data); } -static inline u32 nbmisc_read_index(device_t nb_dev, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) +#else +static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) +#endif { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) +#else +static inline void nbmisc_write_index(struct device *nb_dev, u32 index, + u32 data) +#endif { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); @@ -68,28 +92,49 @@ } } -static inline u32 htiu_read_index(device_t nb_dev, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) +#else +static inline u32 htiu_read_index(struct device *nb_dev, u32 index) +#endif { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) +#else +static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) +#endif { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -static inline u32 nbmc_read_index(device_t nb_dev, u32 index) +#ifdef __SIMPLE_DEVICE__ +static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) +#else +static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) +#endif { return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +#ifdef __SIMPLE_DEVICE__ +static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) +#else +static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) +#endif { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = htiu_read_index(nb_dev, reg_pos); @@ -100,8 +145,13 @@ } } -static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = pci_read_config32(nb_dev, reg_pos); @@ -112,8 +162,13 @@ } } -static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, - u8 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, + u8 mask, u8 val) +#else +static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, + u8 mask, u8 val) +#endif { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); @@ -124,8 +179,13 @@ } } -static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, - u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, + u32 mask, u32 val) +#else +static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = nbmc_read_index(nb_dev, reg_pos); @@ -136,7 +196,13 @@ } } -static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) +#ifdef __SIMPLE_DEVICE__ +static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, + u32 val) +#else +static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos, + u32 mask, u32 val) +#endif { u32 reg_old, reg; reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 574a830..e31f2e8 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -52,12 +52,16 @@ [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); #endif /* MMIO base address for MEI interface */ static u32 *mei_base_address; -void intel_me_mbp_clear(device_t dev); +#ifdef __SIMPLE_DEVICE__ +void intel_me_mbp_clear(pci_devfn_t dev); +#else +void intel_me_mbp_clear(struct device *dev); +#endif #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -112,7 +116,11 @@ mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +#ifdef __SIMPLE_DEVICE__ +static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset) +#else +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +#endif { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -413,7 +421,11 @@ * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static void intel_me_mbp_give_up(pci_devfn_t dev) +#else +static void intel_me_mbp_give_up(struct device *dev) +#endif { struct mei_csr csr; @@ -429,7 +441,11 @@ * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +#ifdef __SIMPLE_DEVICE__ +void intel_me_mbp_clear(pci_devfn_t dev) +#else +void intel_me_mbp_clear(struct device *dev) +#endif { int count; struct me_hfs2 hfs2; @@ -657,7 +673,11 @@ } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static me_bios_path intel_me_path(pci_devfn_t dev) +#else +static me_bios_path intel_me_path(struct device *dev) +#endif { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -727,7 +747,11 @@ } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static int intel_mei_setup(pci_devfn_t dev) +#else +static int intel_mei_setup(struct device *dev) +#endif { struct resource *res; struct mei_csr host; @@ -757,7 +781,11 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static int intel_me_extend_valid(pci_devfn_t dev) +#else +static int intel_me_extend_valid(struct device *dev) +#endif { struct me_heres status; u32 extend[8] = {0}; @@ -804,7 +832,11 @@ } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static void intel_me_init(pci_devfn_t dev) +#else +static void intel_me_init(struct device *dev) +#endif { struct southbridge_intel_lynxpoint_config *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -857,7 +889,13 @@ */ } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +#ifdef __SIMPLE_DEVICE__ +static void set_subsystem(pci_devfn_t dev, unsigned int vendor, + unsigned int device) +#else +static void set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +#endif { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -872,7 +910,11 @@ .set_subsystem = set_subsystem, }; -static void intel_me_enable(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static void intel_me_enable(pci_devfn_t dev) +#else +static void intel_me_enable(struct device *dev) +#endif { /* Avoid talking to the device in S3 path */ if (acpi_is_wakeup_s3()) { @@ -939,7 +981,11 @@ * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +#ifdef __SIMPLE_DEVICE__ +static int intel_me_read_mbp(me_bios_payload *mbp_data, pci_devfn_t dev) +#else +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) +#endif { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cb01de7..6596aa2 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -23,14 +23,17 @@ #include <device/pci_def.h> #include "pch.h" -static device_t pch_get_lpc_device(void) +#ifdef __SIMPLE_DEVICE__ +static pci_devfn_t pch_get_lpc_device(void) { -#ifdef __SMM__ return PCI_DEV(0, 0x1f, 0); -#else - return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif } +#else +static struct device *pch_get_lpc_device(void) +{ + return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +} +#endif int pch_silicon_revision(void) { diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 186e3f9..03341da 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -23,7 +23,11 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static u8 *usb_xhci_mem_base(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static u8 *usb_xhci_mem_base(pci_devfn_t dev) +#else +static u8 *usb_xhci_mem_base(struct device *dev) +#endif { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -34,7 +38,11 @@ return (u8 *)(mem_base & ~0xf); } -static int usb_xhci_port_count_usb3(device_t dev) +#ifdef __SIMPLE_DEVICE__ +static int usb_xhci_port_count_usb3(pci_devfn_t dev) +#else +static int usb_xhci_port_count_usb3(struct device *dev) +#endif { if (pch_is_lp()) { /* LynxPoint-LP has 4 SS ports */ @@ -81,7 +89,11 @@ * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +#ifdef __SIMPLE_DEVICE__ +static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) +#else +static void usb_xhci_reset_usb3(struct device *dev, int all) +#endif { u32 status, port_disabled; int timeout, port; -- To view, visit https://review.coreboot.org/c/coreboot/+/30045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Gerrit-Change-Number: 30045 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/amd/stoneyridge: Get rid of device_t
by HAOUAS Elyes (Code Review) 05 Dec '18

05 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30044 Change subject: soc/amd/stoneyridge: Get rid of device_t ...................................................................... soc/amd/stoneyridge: Get rid of device_t Use of device_t is deprecated. Change-Id: I6d6dce29591f134f64983387c3b268019d52a602 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30044/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 32756cd..205d977 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -435,7 +435,11 @@ void configure_stoneyridge_i2c(void); void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); -void sb_enable(device_t dev); +#ifdef __SIMPLE_DEVICE__ +void sb_enable(pci_devfn_t dev); +#else +void sb_enable(struct device *dev); +#endif void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_lpc_port80(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index fa9e483..4412729 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -703,7 +703,11 @@ sb_print_pmxc0_status(); } -void sb_enable(device_t dev) +#ifdef __SIMPLE_DEVICE__ +void sb_enable(pci_devfn_t dev) +#else +void sb_enable(struct device *dev) +#endif { printk(BIOS_DEBUG, "%s\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6dce29591f134f64983387c3b268019d52a602 Gerrit-Change-Number: 30044 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/lenovo/t520/romstage: Remove unused includes
by Patrick Rudolph (Code Review) 05 Dec '18

05 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30043 ) Change subject: mb/lenovo/t520/romstage: Remove unused includes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82492c071ca760f0790b992acbdb86021f470cfe Gerrit-Change-Number: 30043 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Dec 2018 09:59:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src: Remove asterisks from variable name annotation
by build bot (Jenkins) (Code Review) 05 Dec '18

05 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29235 ) Change subject: src: Remove asterisks from variable name annotation ...................................................................... Patch Set 9: (22 comments) https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h File src/northbridge/amd/amdht/h3finit.h: https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 195: * @param[in] u8 node = The node on which this chain is located line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 229: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 230: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 231: * @param[in,out] u32 FreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 232: * @param[in,out] u32 FeatureCap = modify to change the link's feature capability line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 269: * @param[in,out] u8 ABLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 270: * @param[in,out] u8 BALinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 271: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 302: * @param[in,out] u8 DownstreamLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 303: * @param[in,out] u8 UpstreamLinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 304: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 328: * @param[in] u8 nodeA = One node on which this link is located line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 330: * @param[in] u8 nodeB = The other node on which this link is located line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 403: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 404: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 405: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 434: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 435: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 436: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3finit.h… PS9, Line 462: * @param[in] u8 pEventData0 = useful data associated with the event. line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c: https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3ncmn.c@… PS9, Line 1200: * @param[in] targetNode = The node that shall be the recipient of the traffic line over 80 characters https://review.coreboot.org/#/c/29235/9/src/northbridge/amd/amdht/h3ncmn.c@… PS9, Line 1201: * @param[in] targetLink = The link that shall be the recipient of the traffic line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 9 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Dec 2018 09:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/t520/romstage: Remove unused includes
by Peter Lemenkov (Code Review) 05 Dec '18

05 Dec '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30043 Change subject: mb/lenovo/t520/romstage: Remove unused includes ...................................................................... mb/lenovo/t520/romstage: Remove unused includes Tested - Lenovo t520 still builds fine with this patch. Change-Id: I82492c071ca760f0790b992acbdb86021f470cfe Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/romstage.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/30043/1 diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index d4c2f91..b7bdbbb 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -16,18 +16,12 @@ */ #include <stdint.h> -#include <string.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> #include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <device/device.h> #include <device/pci.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/30043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82492c071ca760f0790b992acbdb86021f470cfe Gerrit-Change-Number: 30043 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/kahlee/variants/liara: Update eDP power off timing sequence
by chris wang (Code Review) 05 Dec '18

05 Dec '18

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30042 to review the following change. Change subject: mb/google/kahlee/variants/liara: Update eDP power off timing sequence ...................................................................... mb/google/kahlee/variants/liara: Update eDP power off timing sequence The eDP power off sequence doesn't meet panel spec. To adjust the delay time from 20ms to 40ms. BUG=b:118011567 TEST=emerge-grunt coreboot Change-Id: I5540db34fa2d1fdea9326a2131c3ed50aacbaa9b Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/liara/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/30042/1 diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index eef984a..41505fa 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -21,7 +21,7 @@ register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms - register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms + register "lvds_poseq_blon_to_varybl" = "0xa" # in 4ms # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/30042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5540db34fa2d1fdea9326a2131c3ed50aacbaa9b Gerrit-Change-Number: 30042 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018