coreboot-gerrit December 2018

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Change in ...coreboot[master]: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
by Patrick Georgi (Code Review) 05 Dec '18

05 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30038 ) Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA ...................................................................... soc/amd/stoneyridge: Run romstage mainboard code before AGESA This is needed so the next patch can set up GPIOs before AGESA runs. BUG=b:120436919 TEST=Verified romstage mainboard code runs before AGESA Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/30038 Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Daniel Kurtz: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index ed83e1e..9314488 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -96,11 +96,10 @@ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1(); + mainboard_romstage_entry(s3_resume); bsp_agesa_call(); - mainboard_romstage_entry(s3_resume); - if (!s3_resume) { post_code(0x40); do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost"); -- To view, visit https://review.coreboot.org/c/coreboot/+/30038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b Gerrit-Change-Number: 30038 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: google/sarien: Increase BIOS region to 28MB
by Patrick Georgi (Code Review) 05 Dec '18

05 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29945 ) Change subject: google/sarien: Increase BIOS region to 28MB ...................................................................... google/sarien: Increase BIOS region to 28MB Platform have a 32MB SPI chip, so we can increase the bios region from 16MB to 28MB. BUG=b:119267832 TEST=Build and boot fine on sarien platform. Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/29945 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.fmd 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 6631769..ef97ab8 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -1,11 +1,11 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1000000 { + SI_ALL@0x0 0x400000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xefd000 + SI_ME@0x103000 0x2fd000 } - SI_BIOS@0x1000000 0x1000000 { + SI_BIOS@0x400000 0x1c00000 { RW_SECTION_A@0x0 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 @@ -30,8 +30,8 @@ RW_NVRAM@0x2a000 0x6000 } CONSOLE@0x530000 0x20000 - RW_LEGACY(CBFS)@0x550000 0x6b0000 - WP_RO@0xc00000 0x400000 { + RW_LEGACY(CBFS)@0x550000 0x12b0000 + WP_RO@0x1800000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/29945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524 Gerrit-Change-Number: 29945 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/amd/stoneyridge: Name IO061 in ASL appropriately
by Patrick Georgi (Code Review) 05 Dec '18

05 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30037 ) Change subject: soc/amd/stoneyridge: Name IO061 in ASL appropriately ...................................................................... soc/amd/stoneyridge: Name IO061 in ASL appropriately AMD traditionally claims the resource at I/O port 61 for the onboard PC-AT speaker. In later designs, the speaker may be omitted in favor of routing the SPKR signal to the codec. Some systems implement neither, and for those it is not correct to identify the resource as a speaker. Modify the EISAID reported to the OS depending on the system design. The default is that port 61 is reported as reserved. In order to report a speaker, add #define in mainboard//dsdt.asl. TEST=check /proc/ioports and iasl -d for both ways using a Grunt BUG=b:117818432 Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30037 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/amd/gardenia/dsdt.asl M src/soc/amd/stoneyridge/acpi/lpc.asl 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index f190b4e..52bd90b 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#define MAINBOARD_HAS_SPEAKER 1 + /* DefinitionBlock Statement */ #include <arch/acpi.h> DefinitionBlock ( diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl index a41357a..e24514c 100644 --- a/src/soc/amd/stoneyridge/acpi/lpc.asl +++ b/src/soc/amd/stoneyridge/acpi/lpc.asl @@ -13,6 +13,12 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(MAINBOARD_HAS_SPEAKER) +#define IO61_HID "PNP0800" /* AT style speaker */ +#else +#define IO61_HID "PNP0C02" /* reserved resource */ +#endif + /* 0:14.3 - LPC */ Device(LPCB) { Name(_ADR, 0x00140003) @@ -66,7 +72,7 @@ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_HID,EISAID(IO61_HID)) Name(_CRS, ResourceTemplate() { IO(Decode16, 0x0061, 0x0061, 0, 1) }) -- To view, visit https://review.coreboot.org/c/coreboot/+/30037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4 Gerrit-Change-Number: 30037 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/southbridge: Get rid of device_t
by Tristan Corrick (Code Review) 05 Dec '18

05 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30045 ) Change subject: src/southbridge: Get rid of device_t ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/30045/2/src/southbridge/intel/lynxpoint/me_… File src/southbridge/intel/lynxpoint/me_9.x.c: https://review.coreboot.org/#/c/30045/2/src/southbridge/intel/lynxpoint/me_… PS2, Line 626: #else /* !__SMM__ */ Everything below this line can just be `struct device *`. -- To view, visit https://review.coreboot.org/c/coreboot/+/30045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Gerrit-Change-Number: 30045 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Wed, 05 Dec 2018 13:56:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel: Fix pointer casts
by Patrick Georgi (Code Review) 05 Dec '18

05 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29875 ) Change subject: sb/intel: Fix pointer casts ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29875/2/src/southbridge/intel/i82801ix/lpc.c File src/southbridge/intel/i82801ix/lpc.c: https://review.coreboot.org/#/c/29875/2/src/southbridge/intel/i82801ix/lpc.… PS2, Line 556: acpigen_write_name_dword is this really writing out a 64bit pointer when compiled for 64bit? Or is this just enough to get things through the compiler? -- To view, visit https://review.coreboot.org/c/coreboot/+/29875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Gerrit-Change-Number: 29875 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 05 Dec 2018 13:50:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/i82801{g, j}x: Remove unused smi.c files
by Patrick Georgi (Code Review) 05 Dec '18

05 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30018 ) Change subject: sb/intel/i82801{g,j}x: Remove unused smi.c files ...................................................................... sb/intel/i82801{g,j}x: Remove unused smi.c files Now that all targets featuring these southbridges use SMM_TSEG these files are unused. Change-Id: Ic3a1d790f3595e98a8d33e6e8274cb72ad356a89 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30018 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/southbridge/intel/i82801gx/smi.c D src/southbridge/intel/i82801jx/smi.c 2 files changed, 0 insertions(+), 366 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c deleted file mode 100644 index 5618db7..0000000 --- a/src/southbridge/intel/i82801gx/smi.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <string.h> -#include <southbridge/intel/common/pmutil.h> -#include "i82801gx.h" - -/* I945 */ -#define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -extern uint8_t smm_relocation_start, smm_relocation_end; -static void *default_smm_area = NULL; - -static void smm_relocate(void) -{ - u32 smi_en; - u16 pm1_en; - - printk(BIOS_DEBUG, "Initializing SMM handler..."); - - pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - default_smm_area = backup_default_smm_area(); - - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - wbinvd(); - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - -#if 0 - smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; -#endif - smi_en |= TCO_EN; - smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif - smi_en |= SLP_SMI_EN; - smi_en |= BIOS_EN; - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -static int smm_handler_copied = 0; - -static void smm_install(void) -{ - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - - /* if we're resuming from S3, the SMM code is already in place, - * so don't copy it again to keep the current SMM state */ - - if (!acpi_is_wakeup_s3()) { - /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); - - /* copy the real SMM handler */ - memcpy((void *)0xa0000, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); - } - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) -{ - /* Put SMM code to 0xa0000 */ - smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_init_completion(void) -{ - restore_default_smm_area(default_smm_area); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/southbridge/intel/i82801jx/smi.c b/src/southbridge/intel/i82801jx/smi.c deleted file mode 100644 index 7ab5c28..0000000 --- a/src/southbridge/intel/i82801jx/smi.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <string.h> -#include <southbridge/intel/common/pmutil.h> -#include "i82801jx.h" - -/* I945/GM45 */ -#define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -static u16 pmbase = DEFAULT_PMBASE; - -extern uint8_t smm_relocation_start, smm_relocation_end; -static void *default_smm_area = NULL; - -static void smm_relocate(void) -{ - u32 smi_en; - u16 pm1_en; - - printk(BIOS_DEBUG, "Initializing SMM handler..."); - - pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - smi_en = inl(pmbase + SMI_EN); - if (smi_en & GBL_SMI_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - default_smm_area = backup_default_smm_area(); - - /* copy the SMM relocation code */ - memcpy((void *)0x38000, &smm_relocation_start, - &smm_relocation_end - &smm_relocation_start); - wbinvd(); - - printk(BIOS_DEBUG, "\n"); - dump_smi_status(reset_smi_status()); - dump_pm1_status(reset_pm1_status()); - dump_gpe0_status(reset_gpe0_status()); - dump_alt_gp_smi_status(reset_alt_gp_smi_status()); - dump_tco_status(reset_tco_status()); - - /* Enable SMI generation: - * - on TCO events - * - on APMC writes (io 0xb2) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - */ - - smi_en = 0; /* reset SMI enables */ - - smi_en |= TCO_EN; - smi_en |= APMC_EN; -#if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using - * periodic SMIs. - */ - smi_en |= PERIODIC_EN; -#endif - smi_en |= BIOS_EN; - - /* The following need to be on for SMIs to happen */ - smi_en |= EOS | GBL_SMI_EN; - - outl(smi_en, pmbase + SMI_EN); - - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -static int smm_handler_copied = 0; - -static void smm_install(void) -{ - /* The first CPU running this gets to copy the SMM handler. But not all - * of them. - */ - if (smm_handler_copied) - return; - smm_handler_copied = 1; - - - /* if we're resuming from S3, the SMM code is already in place, - * so don't copy it again to keep the current SMM state */ - - if (!acpi_is_wakeup_s3()) { - /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); - - /* copy the real SMM handler */ - memcpy((void *)0xa0000, _binary_smm_start, - _binary_smm_end - _binary_smm_start); - wbinvd(); - } - - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - G_SMRAME | C_BASE_SEG); -} - -void smm_init(void) -{ - /* Put SMM code to 0xa0000 */ - smm_install(); - - /* Put relocation code to 0x38000 and relocate SMBASE */ - smm_relocate(); - - /* We're done. Make sure SMIs can happen! */ - smi_set_eos(); -} - -void smm_init_completion(void) -{ - restore_default_smm_area(default_smm_area); -} - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1d790f3595e98a8d33e6e8274cb72ad356a89 Gerrit-Change-Number: 30018 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Select relocatable ramstage
by Patrick Rudolph (Code Review) 05 Dec '18

05 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29911 ) Change subject: [TESTME]soc/intel/fsp_broadwell_de: Select relocatable ramstage ...................................................................... Patch Set 1: Code-Review+1 Tested on wedge100s: Still boots to payload -- To view, visit https://review.coreboot.org/c/coreboot/+/29911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046 Gerrit-Change-Number: 29911 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 05 Dec 2018 11:54:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Mod...
by Lucas Chen (Code Review) 05 Dec '18

05 Dec '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30050 Change subject: google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update micron-MT40A512M16JY-083E-B.spd.hex SPD file Module Part Number Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B" from "4ATF51264HZ-2G3B2". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/30050/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex index 6f90d9b..3de5386 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16JY-083E-B.spd.hex @@ -19,9 +19,9 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 -36 34 48 5a 2d 32 47 33 42 32 20 20 00 32 80 2C -42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31 +32 4D 31 36 4A 59 2D 30 38 33 45 3A 42 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920 Gerrit-Change-Number: 30050 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/grunt: Update micron-MT40A1G16KNR-075-E.spd.hex SPD file Modul...
by Lucas Chen (Code Review) 05 Dec '18

05 Dec '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30049 Change subject: google/grunt: Update micron-MT40A1G16KNR-075-E.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update micron-MT40A1G16KNR-075-E.spd.hex SPD file Module Part Number Correct Ram_ID=0b0011 SPD Module Part Number to "MT40A1G16KNR-075:E" from "4ATS1G64HZ-2G6E1". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/30049/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex index 7e4888b..094a0f9 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A1G16KNR-075-E.spd.hex @@ -19,9 +19,9 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 2C 00 00 00 00 00 00 00 34 41 54 53 31 47 36 -34 48 5a 2d 32 47 36 45 31 20 20 20 00 31 80 2C -45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 4E 52 2D 30 37 35 3A 45 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff Gerrit-Change-Number: 30049 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Par...
by Lucas Chen (Code Review) 05 Dec '18

05 Dec '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30048 Change subject: google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update hynix-H5AN8G6NAFR-UH.spd.hex SPD file Module Part Number Correct Ram_ID=0b0000 SPD Module Part Number to "H5AN8G6NAFR-UH" from "HMA851S6AFR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30048/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex index fd5fe6f..b1d902f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NAFR-UH.spd.hex @@ -19,9 +19,9 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 -36 41 46 52 36 4E 2D 55 48 20 20 20 20 00 80 AD -FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 +4E 41 46 52 2D 55 48 20 20 20 20 20 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/30048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91 Gerrit-Change-Number: 30048 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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