coreboot-gerrit December 2018

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Change in ...coreboot[master]: cpu/via/nano: Implement POSTCAR stage
by Arthur Heymans (Code Review) 05 Dec '18

05 Dec '18

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30058 to look at the new patch set (#2). Change subject: cpu/via/nano: Implement POSTCAR stage ...................................................................... cpu/via/nano: Implement POSTCAR stage Use postcar frame functions to set up an environment that the relocatable ramstage can use. Untested Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/via/car/cache_as_ram.inc M src/cpu/via/nano/Kconfig M src/cpu/via/nano/Makefile.inc M src/mainboard/via/epia-m850/romstage.c M src/northbridge/via/vx900/Makefile.inc M src/northbridge/via/vx900/memmap.c M src/northbridge/via/vx900/vx900.h 7 files changed, 36 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30058/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db Gerrit-Change-Number: 30058 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Update GPIOs for next build
by Duncan Laurie (Code Review) 05 Dec '18

05 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30062 Change subject: mb/google/sarien: Update GPIOs for next build ...................................................................... mb/google/sarien: Update GPIOs for next build Update the GPIOs for the next board build. Mostly minor changes but the polarity change on GPP_E8/RECOVERY on sarien will result in it booting to recovery every time unless using new hardware. For this reason the recovery mode GPIO that is passed to vboot is commented out for sarien. It is only used for testing and currently it is useful to have an image that works on both board versions. Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 40 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30062/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 0ffd029..a29fd06 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -30,18 +30,23 @@ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), -/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), + /* ISH_LID_CL#_TAB */ +/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* SUSWARN# */ PAD_NC(GPP_A13, NONE), /* ESPI_RESET# */ /* SUSACK# */ PAD_NC(GPP_A15, NONE), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), -/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), -/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), + /* ISH_ACC1_INT# */ +/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* ISH_ACC2_INT# */ +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* ISH_GP2 */ PAD_NC(GPP_A20, NONE), /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), -/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), -/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), + /* ISH_NB_MODE */ +/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + /* ISH_LID_CL#_NB */ +/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* CORE_VID0 */ /* CORE_VID1 */ @@ -49,12 +54,17 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ + /* LAN_CLKREQ_CPU_N */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* CARD_CLKREQ_CPU_N */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* WWAN_CLKREQ_CPU_N */ /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */ /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), @@ -63,7 +73,7 @@ /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ /* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -112,8 +122,10 @@ /* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), /* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */ /* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE), -/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), -/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), + /* ISH_CPU_UART0_RX */ +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* ISH_CPU_UART0_TX */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ @@ -144,10 +156,10 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ -/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */ /* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), @@ -179,9 +191,9 @@ /* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */ -/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */ /* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */ -/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */ +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */ /* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */ /* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index a41d940..38d21c8 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -49,11 +49,11 @@ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */ /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), @@ -63,8 +63,7 @@ /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* HDD_FALL_INT */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), @@ -101,7 +100,7 @@ EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), -/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */ /* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), /* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), @@ -135,7 +134,7 @@ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ /* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */ @@ -143,8 +142,7 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* FFS_INT2 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), @@ -237,7 +235,7 @@ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ -/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ +/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ }; @@ -254,7 +252,10 @@ } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME), + /* + * TODO: re-enable recovery mode when boards are updated: + * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), + */ CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Gerrit-Change-Number: 30062 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix I2C clock input
by Duncan Laurie (Code Review) 05 Dec '18

05 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30061 Change subject: soc/intel/cannonlake: Fix I2C clock input ...................................................................... soc/intel/cannonlake: Fix I2C clock input The input clock for the I2C controllers was set at 133MHz but should really be 216MHz according to the kernel: https://patchwork.kernel.org/patch/10408729/ "Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C than Sunrisepoint which uses 120 MHz. Preliminary information was that both share the same clock rate but actual silicon implements elevated rate for better support for 3.4 MHz high-speed I2C." This change was tested on a sarien board where an I2C trackpad that was measuring ~700MHz on I2C and is now measuring ~380MHz. Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30061/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 78c6dfe..9e007b6 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -197,7 +197,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 216 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int -- To view, visit https://review.coreboot.org/c/coreboot/+/30061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70 Gerrit-Change-Number: 30061 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/lessons/lesson2.md: fix the git push command
by Michael Bacarella (Code Review) 05 Dec '18

05 Dec '18

Michael Bacarella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30054 ) Change subject: Documentation/lessons/lesson2.md: fix the git push command ...................................................................... Abandoned favor #30060 instead -- To view, visit https://review.coreboot.org/c/coreboot/+/30054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a7e58600bb1527c3e407921f7984bf94bff8d58 Gerrit-Change-Number: 30054 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: Documentation/lessons/lesson2.md: fix the git push command
by Michael Bacarella (Code Review) 05 Dec '18

05 Dec '18

Michael Bacarella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30054 ) Change subject: Documentation/lessons/lesson2.md: fix the git push command ...................................................................... Patch Set 4: > Patch Set 4: > > (2 comments) Oh. Well that explains why this has been so confusing, I misunderstood that section. I propose change #30060 to clear up the language around running make gitconfig (and keep the blurb about running Gerrit). I'll abandon this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/30054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a7e58600bb1527c3e407921f7984bf94bff8d58 Gerrit-Change-Number: 30054 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Dec 2018 20:44:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/lessons/lesson2.md: clear up confusing language around ...
by Michael Bacarella (Code Review) 05 Dec '18

05 Dec '18

Michael Bacarella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30060 Change subject: Documentation/lessons/lesson2.md: clear up confusing language around running gitconfig ...................................................................... Documentation/lessons/lesson2.md: clear up confusing language around running gitconfig It's easy to misinterpret or miss altogether the instruction to run 'make gitconfig', which will cause strange problems a few commands later. Revise the docuentation to make it clearer. Also adds a blurb further down with a link to find Gerrit workflow docs. Change-Id: I49734c724c4d6da716a358cd849938ef14dab3b1 Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> --- M Documentation/lessons/lesson2.md 1 file changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30060/1 diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index a95dd80..5b774cd 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -71,14 +71,18 @@ If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" and run the command that appears -After it finishes cloning, "cd coreboot" will take you into the local -git repository. Run "make gitconfig" to set up the hooks and configurations. -For example, you will be asked to run the following commands to set your -username and email. +Now is a good time to configure your global git identity, if you haven't +already. git config --global user.name "Your Name" git config --global user.email "Your Email" +Finally, enter the local git repository and set up repository specific hooks +and other configurations. + + cd coreboot + make gitconfig + ## Part 4: Submit a commit An easy first commit to make is fixing existing checkpatch errors and warnings @@ -208,6 +212,12 @@ Submitting as a draft means that your commit will be on coreboot.org, but is only visible to those you add as reviewers. +This has been a quick primer on how to submit a change to Gerrit for review +using git. You may wish to review the Gerrit code review workflow +documentation, especially if you plan to work on multiple changes at the same +time. See +https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review + ## Part 5: Getting your commit reviewed Your commits can now be seen on review.coreboot.org if you select “Your” -- To view, visit https://review.coreboot.org/c/coreboot/+/30060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49734c724c4d6da716a358cd849938ef14dab3b1 Gerrit-Change-Number: 30060 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/via: Remove unused smbus_delay() function
by HAOUAS Elyes (Code Review) 05 Dec '18

05 Dec '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30059 ) Change subject: sb/via: Remove unused smbus_delay() function ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa2aed4f1e1014989aaad4a4abcc10d00f6db12 Gerrit-Change-Number: 30059 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/via: Remove unused smbus_delay() function
by HAOUAS Elyes (Code Review) 05 Dec '18

05 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30059 Change subject: sb/via: Remove unused smbus_delay() function ...................................................................... sb/via: Remove unused smbus_delay() function Change-Id: I1fa2aed4f1e1014989aaad4a4abcc10d00f6db12 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/via/vx900/Makefile.inc D src/southbridge/via/common/early_smbus_delay.c 2 files changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/30059/1 diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index bbfe63b..111bd89 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -23,7 +23,6 @@ romstage-y += raminit_ddr3.c romstage-y += memmap.c romstage-y += ./../../../device/dram/ddr3.c -romstage-y += ./../../../southbridge/via/common/early_smbus_delay.c romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c diff --git a/src/southbridge/via/common/early_smbus_delay.c b/src/southbridge/via/common/early_smbus_delay.c deleted file mode 100644 index 0c04112..0000000 --- a/src/southbridge/via/common/early_smbus_delay.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "via_early_smbus.h" - -/** - * \brief Brief delay for SMBus transactions - */ -void smbus_delay(void) -{ - inb(0x80); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/30059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa2aed4f1e1014989aaad4a4abcc10d00f6db12 Gerrit-Change-Number: 30059 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/via/nano: Implement POSTCAR stage
by Arthur Heymans (Code Review) 05 Dec '18

05 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30058 Change subject: cpu/via/nano: Implement POSTCAR stage ...................................................................... cpu/via/nano: Implement POSTCAR stage Use postcar frame functions to set up an environment that the relocatable ramstage can use. Untested Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/via/car/cache_as_ram.inc M src/cpu/via/nano/Kconfig M src/cpu/via/nano/Makefile.inc M src/mainboard/via/epia-m850/romstage.c M src/northbridge/via/vx900/Makefile.inc M src/northbridge/via/vx900/memmap.c M src/northbridge/via/vx900/vx900.h 7 files changed, 36 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/30058/1 diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index b7803d8..cd27539 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -169,69 +169,9 @@ pushl %eax /* BIST */ call main - /* - * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we - * get STACK up, we restore that. It is only needed if we - * want to go back. - */ - - /* We don't need CAR from now on. */ - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - /* Set the default memory type and enable variable MTRRs. */ - /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRR_DEF_TYPE_MSR, %ecx - xorl %edx, %edx - movl $(MTRR_DEF_TYPE_EN), %eax - wrmsr - - /* Enable caching for 0..CACHE_TMP_RAMTOP. */ - movl $MTRR_PHYS_BASE(0), %ecx - xorl %edx, %edx - movl $(0x0 | MTRR_TYPE_WRBACK), %eax - wrmsr - - movl $MTRR_PHYS_MASK(0), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Cache XIP_ROM area to speedup coreboot code. */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ - movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRR_PHYS_MASK(1), %ecx - xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr - - /* Enable cache. */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - movl %eax, %cr0 - invd - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl $CONFIG_RAMTOP, %esp - movl %esp, %ebp - call copy_and_run + /* Should never see this postcode */ + post_code(POST_DEAD_CODE) .Lhlt: - post_code(POST_DEAD_CODE) hlt jmp .Lhlt diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index c7e7060..b789e45 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -29,6 +29,8 @@ select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + select POSTCAR_STAGE + select POSTCAR_CONSOLE config DCACHE_RAM_BASE hex diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc index 43d0352..2a865ac 100644 --- a/src/cpu/via/nano/Makefile.inc +++ b/src/cpu/via/nano/Makefile.inc @@ -26,3 +26,5 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/via/nano/microcode.bin cpu_incs-y += $(src)/cpu/via/car/cache_as_ram.inc + +postcar-y += ../car/exit_car.S \ No newline at end of file diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index dd303b7..7709709 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -98,4 +98,6 @@ /* FIXME: See if this is needed or take this out please */ /* Disable Memcard and SDIO */ pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4)); + + platform_enter_postcar(); } diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index bbfe63b..ec9edf3 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -48,4 +48,6 @@ bootblock-y += romstrap.ld bootblock-y += romstrap.S +postcar-y += memmap.c + endif diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c index 8cc7607..82aedbf 100644 --- a/src/northbridge/via/vx900/memmap.c +++ b/src/northbridge/via/vx900/memmap.c @@ -19,6 +19,7 @@ #include "vx900.h" +#include <cpu/x86/mtrr.h> #include <device/pci.h> #include <cbmem.h> @@ -27,6 +28,8 @@ #define CHROME_9_HD_MIN_FB_SIZE 8 #define CHROME_9_HD_MAX_FB_SIZE 512 +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + /* Helper to determine the framebuffer size */ void vx900_set_chrome9hd_fb_size(u32 size_mb) { @@ -126,3 +129,25 @@ return (void *)((tolm - fb_size) << 20); } + +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index a2a360a..9153fe2 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -37,6 +37,7 @@ u32 vx900_get_chrome9hd_fb_size(void); u8 vx900_int15_get_5f18_bl(void); uint64_t get_uma_memory_base(void); +void platform_enter_postcar(void); /* We use these throughout the code. They really belong in a generic part of * coreboot, but until bureaucracy gets them there, we still need them */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d792f5d9e5109956945bf6bd783d887dd7bb5db Gerrit-Change-Number: 30058 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/via/vx900: Select relocatable ramstage
by Arthur Heymans (Code Review) 05 Dec '18

05 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30057 Change subject: nb/via/vx900: Select relocatable ramstage ...................................................................... nb/via/vx900: Select relocatable ramstage There could be some performance loss due to not setting up MTRR's to cache cbmem. This resolved in a follow-up patch implementing postcar stage. Change-Id: I53412ebc1a4169487e1234b0bf025714b5e8318f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/via/vx900/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30057/1 diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 8d95942..98f57e4 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -21,7 +21,6 @@ select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_CF9_RESET - select NO_RELOCATABLE_RAMSTAGE if NORTHBRIDGE_VIA_VX900 -- To view, visit https://review.coreboot.org/c/coreboot/+/30057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53412ebc1a4169487e1234b0bf025714b5e8318f Gerrit-Change-Number: 30057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018