coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Enable melf touchscreen
by Chris Zhou (Code Review) 06 Dec '18

06 Dec '18

Chris Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 ) Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/devicetree.cb: https://review.coreboot.org/#/c/29830/2/src/mainboard/google/sarien/variant… PS2, Line 124: > > Does it work to just leave out the reset_gpio settings? […] Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/29830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Gerrit-Change-Number: 29830 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 06 Dec 2018 01:25:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/amd/pi/hudson: Fix UART address math
by Marshall Dawson (Code Review) 06 Dec '18

06 Dec '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30072 Change subject: sb/amd/pi/hudson: Fix UART address math ...................................................................... sb/amd/pi/hudson: Fix UART address math Correct a build error that occurs when HUDSON_UART is selected. Replace sizeof() of a nonexistent variable with the intended type. This was introduced in bd48b23 "southbridge//hudson: Get rid of void pointer math". BUG=b:118484178 TEST=Build Bettong with Chipset/"UART controller for Kern" Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/southbridge/amd/pi/hudson/early_setup.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30072/1 diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 07c4519..3b91f9b 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -36,10 +36,10 @@ u8 byte; byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(word))); + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(word)), byte); + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); byte |= 1 << 3; write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); -- To view, visit https://review.coreboot.org/c/coreboot/+/30072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284 Gerrit-Change-Number: 30072 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Enable ISH on arcada, disable on sarien
by Li1 Feng (Code Review) 06 Dec '18

06 Dec '18

Li1 Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30070 ) Change subject: mb/google/sarien: Enable ISH on arcada, disable on sarien ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Gerrit-Change-Number: 30070 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Dec 2018 00:04:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGE
by Arthur Heymans (Code Review) 06 Dec '18

06 Dec '18

Hello Patrick Rudolph, York Yang, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29911 to look at the new patch set (#2). Change subject: soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGE ...................................................................... soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGE Tested on wedge100s. Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/fsp_broadwell_de/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/29911/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046 Gerrit-Change-Number: 29911 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/fsp_baytrail: Select RELOCATABLE_RAMSTAGE
by Arthur Heymans (Code Review) 06 Dec '18

06 Dec '18

Hello Patrick Rudolph, Huang Jin, York Yang, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29910 to look at the new patch set (#2). Change subject: soc/intel/fsp_baytrail: Select RELOCATABLE_RAMSTAGE ...................................................................... soc/intel/fsp_baytrail: Select RELOCATABLE_RAMSTAGE Change-Id: I206f879f1d944c0a5e4e62ac4d2328889bc2b4ce Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/fsp_baytrail/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/29910/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I206f879f1d944c0a5e4e62ac4d2328889bc2b4ce Gerrit-Change-Number: 29910 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/sarien: Enable ISH on arcada, disable on sarien
by Duncan Laurie (Code Review) 05 Dec '18

05 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30070 Change subject: mb/google/sarien: Enable ISH on arcada, disable on sarien ...................................................................... mb/google/sarien: Enable ISH on arcada, disable on sarien The Intel Sensor Hub was enabled on the wrong variant so this change moves the enable from sarien to arcada. Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30070/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 54308e1..93e0af9 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -113,6 +113,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 + device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e1f2512..975382e 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -113,7 +113,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 13.0 on end # Integrated Sensor Hub + device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/30070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Gerrit-Change-Number: 30070 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Get rid of "#define __SIMPLE_DEVICE__"
by Arthur Heymans (Code Review) 05 Dec '18

05 Dec '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30040 ) Change subject: src: Get rid of "#define __SIMPLE_DEVICE__" ...................................................................... Patch Set 2: Defining __SIMPLE_DEVICE__ is useful if you want to reuse code. Removing it only makes sense on files where __SIMPLE_DEVICES__ is already defined on all stages in which the code is linked. -- To view, visit https://review.coreboot.org/c/coreboot/+/30040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dd770fcddf44aeec847d3651ec281af5f91fbf0 Gerrit-Change-Number: 30040 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 05 Dec 2018 23:51:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Enable melf touchscreen
by Duncan Laurie (Code Review) 05 Dec '18

05 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29830 ) Change subject: mb/google/sarien/variants/sarien: Enable melf touchscreen ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Gerrit-Change-Number: 29830 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Dec 2018 23:48:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Set initial I2C bus rise/fall times
by Duncan Laurie (Code Review) 05 Dec '18

05 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30069 Change subject: mb/google/sarien: Set initial I2C bus rise/fall times ...................................................................... mb/google/sarien: Set initial I2C bus rise/fall times Provide rise/fall times as measured on existing boards. This will need adjusted for new boards but provides a starting point that makes I2C clocks look reasonable. Tested by measuring I2C bus speed and rise/fall times with a scope. Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30069/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f487979..54308e1 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -67,10 +67,14 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 216, + .fall_time_ns = 28, }, .i2c[4] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 452, + .fall_time_ns = 110, }, }" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 991e9640..e1f2512 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -67,10 +67,14 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 290, + .fall_time_ns = 110, }, .i2c[4] = { .early_init = 1, .speed = I2C_SPEED_FAST, + .rise_time_ns = 280, + .fall_time_ns = 90, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/30069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b Gerrit-Change-Number: 30069 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/i2c/designware: Add soc_clock entry for 216MHz
by Duncan Laurie (Code Review) 05 Dec '18

05 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30068 Change subject: drivers/i2c/designware: Add soc_clock entry for 216MHz ...................................................................... drivers/i2c/designware: Add soc_clock entry for 216MHz Add an entry to the soc_clock table for a 216MHz clock so that the I2C controller clock is calculated correctly when the I2C bus is used in coreboot. This was tested by measuring the I2C clock speed on H1 I2C bus on a sarien board in coreboot and ensuring it is ~400KHz. Change-Id: I6c3cacdad318a5ce41bc41e3ac81385c2d4f396c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30068/1 diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index d190d86..46df7b1 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -217,6 +217,13 @@ .ns = 3000, }, }, + { + .clk_speed_mhz = 216, + .freq = { + .ticks = 1080, + .ns = 5000, + }, + }, }; static const struct i2c_descriptor *get_bus_descriptor(enum i2c_speed speed) -- To view, visit https://review.coreboot.org/c/coreboot/+/30068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c3cacdad318a5ce41bc41e3ac81385c2d4f396c Gerrit-Change-Number: 30068 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018