coreboot-gerrit December 2018

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Change in ...coreboot[master]: 3rdparty/blobs: Update for current Intel microcode
by Nico Huber (Code Review) 06 Dec '18

06 Dec '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30081 Change subject: 3rdparty/blobs: Update for current Intel microcode ...................................................................... 3rdparty/blobs: Update for current Intel microcode The microcode included for `model_6xx` was for a 660, that path has changed. Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M 3rdparty/blobs M src/cpu/intel/model_6xx/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/30081/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index be390ff..f53429b 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit be390ffb5b2cce76a563f4516c58a49f1af90229 +Subproject commit f53429bdadddb1db8cd0ea35a1aa117515130bf7 diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 1ac799e..3ac510f 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1,3 +1,3 @@ ramstage-y += model_6xx_init.c -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6xx/microcode.bin +cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_66x/microcode.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/30081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73 Gerrit-Change-Number: 30081 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer for boards I've ported
by Patrick Georgi (Code Review) 06 Dec '18

06 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30075 ) Change subject: MAINTAINERS: Add myself as a maintainer for boards I've ported ...................................................................... MAINTAINERS: Add myself as a maintainer for boards I've ported Change-Id: I41363685bb5c84ce15698f96e58f6a5da9bd2ba2 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30075 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 0dab855..f90315e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,6 +324,11 @@ S: Maintained F: src/mainboard/asrock/g41c-gs/ +ASROCK H81M-HDS MAINBOARD +M: Tristan Corrick <tristan(a)corrick.kiwi> +S: Maintained +F: src/mainboard/asrock/h81m-hds/ + ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Supported @@ -340,11 +345,21 @@ S: Supported F: src/mainboard/asus/kgpe-d16/ +ASUS MAXIMUS IV GENE-Z MAINBOARD +M: Tristan Corrick <tristan(a)corrick.kiwi> +S: Maintained +F: src/mainboard/asus/maximus_iv_gene-z/ + ASUS P5QC PRO MAINBOARD & VARIANTS M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained F: src/mainboard/asus/p5qc/ +ASUS P8H61-M LX MAINBOARD +M: Tristan Corrick <tristan(a)corrick.kiwi> +S: Maintained +F: src/mainboard/asus/p8h61-m_lx/ + ASUS P8H61-M PRO MAINBOARD M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/30075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41363685bb5c84ce15698f96e58f6a5da9bd2ba2 Gerrit-Change-Number: 30075 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer for boards I've ported
by Patrick Georgi (Code Review) 06 Dec '18

06 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30075 ) Change subject: MAINTAINERS: Add myself as a maintainer for boards I've ported ...................................................................... Patch Set 1: > Patch Set 1: > > Could I also please be given the ability to give +2 code reviews? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41363685bb5c84ce15698f96e58f6a5da9bd2ba2 Gerrit-Change-Number: 30075 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Dec 2018 11:26:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/variants/fleex: Update Charger throttling settings
by Sumeet R Pawnikar (Code Review) 06 Dec '18

06 Dec '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30080 Change subject: mb/google/octopus/variants/fleex: Update Charger throttling settings ...................................................................... mb/google/octopus/variants/fleex: Update Charger throttling settings Update dptf settings for Charger throttling. Also, update Power Limit1 minimum value setting from 4.5W to 3W. BUG=b:112448519 BRANCH=octopus TEST=Built and tested on Fleex system Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/30080/1 diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl index d5943c7..5f35c33 100644 --- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl @@ -26,6 +26,8 @@ #define DPTF_TSR2_PASSIVE 53 #define DPTF_TSR2_CRITICAL 127 +#define DPTF_ENABLE_CHARGER + /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ @@ -42,8 +44,10 @@ /* CPU Effect on Temp Sensor 1 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, +#endif }) Name (MPPC, Package () @@ -51,7 +55,7 @@ 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 4500, /* PowerLimitMinimum */ + 3000, /* PowerLimitMinimum */ 10000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2a796ff28254ebef28ed5745b344f925d6e649 Gerrit-Change-Number: 30080 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer for boards I've ported
by Angel Pons (Code Review) 06 Dec '18

06 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30075 ) Change subject: MAINTAINERS: Add myself as a maintainer for boards I've ported ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41363685bb5c84ce15698f96e58f6a5da9bd2ba2 Gerrit-Change-Number: 30075 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Dec 2018 10:50:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment
by Angel Pons (Code Review) 06 Dec '18

06 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30078 ) Change subject: sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e Gerrit-Change-Number: 30078 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Dec 2018 10:48:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers
by Tristan Corrick (Code Review) 06 Dec '18

06 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30079 Change subject: sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers ...................................................................... sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointers If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL. The existing Lynx Point systems probably don't end up dereferencing NULL pointers this way. However, it might occur on a system using Flexible I/O to remap PCIe root ports to other functions. Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues presented themselves. Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 29 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30079/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 231f3e7..695abf2 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <assert.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -22,6 +24,8 @@ #include <device/pci_ops.h> #include "pch.h" #include <southbridge/intel/common/gpio.h> +#include <stddef.h> +#include <stdint.h> #define MAX_NUM_ROOT_PORTS 8 @@ -68,6 +72,16 @@ return PCI_FUNC(dev->path.pci.devfn) + 1; } +static bool is_rp_enabled(int rp) +{ + ASSERT(rp > 0 && rp <= ARRAY_SIZE(rpc.ports)); + + if (rpc.ports[rp - 1] == NULL) + return false; + + return rpc.ports[rp - 1]->enabled; +} + static void root_port_config_update_gbe_port(void) { /* Is the Gbe Port enabled? */ @@ -163,7 +177,7 @@ /* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, pci_func); - if (dev->path.pci.devfn != new_devfn) { + if (dev && dev->path.pci.devfn != new_devfn) { printk(BIOS_DEBUG, "PCH: PCIe map %02x.%1x -> %02x.%1x\n", PCI_SLOT(dev->path.pci.devfn), @@ -188,9 +202,12 @@ int rp; dev = rpc.ports[i]; + if (!dev) + continue; + rp = root_port_number(dev); - if (!dev->enabled) { + if (!is_rp_enabled(rp)) { static const uint32_t high_bit = (1UL << 31); /* Configure shared resource clock gating. */ @@ -198,17 +215,13 @@ pci_update_config8(dev, 0xe1, 0xc3, 0x3c); if (!is_lp) { - if (rp == 1 && !rpc.ports[1]->enabled && - !rpc.ports[2]->enabled && - !rpc.ports[3]->enabled) { + if (rp == 1 && !is_rp_enabled(2) && + !is_rp_enabled(3) && !is_rp_enabled(4)) { pci_update_config8(dev, 0xe2, ~1, 1); pci_update_config8(dev, 0xe1, 0x7f, 0x80); } - if (rp == 5 && !rpc.ports[5]->enabled && - (rpc.ports[6] == NULL || - !rpc.ports[6]->enabled) && - (rpc.ports[7] == NULL || - !rpc.ports[7]->enabled)) { + if (rp == 5 && !is_rp_enabled(6) && + !is_rp_enabled(7) && !is_rp_enabled(8)) { pci_update_config8(dev, 0xe2, ~1, 1); pci_update_config8(dev, 0xe1, 0x7f, 0x80); } @@ -223,8 +236,8 @@ pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ - if (rp == 1 && !rpc.ports[1]->enabled && - !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { + if (rp == 1 && !is_rp_enabled(2) && + !is_rp_enabled(3) && !is_rp_enabled(4)) { pci_update_config8(dev, 0xe2, ~1, 1); pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { @@ -258,7 +271,7 @@ pci_update_config8(dev, 0xe1, 0xc3, 0x3c); } - if (!enabled_ports && is_lp) + if (!enabled_ports && is_lp && rpc.ports[0]) pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } @@ -267,7 +280,7 @@ int i; /* If the first root port is disabled the coalesce ports. */ - if (!rpc.ports[0]->enabled) + if (!is_rp_enabled(1)) rpc.coalesce = 1; /* Perform clock gating configuration. */ @@ -307,7 +320,7 @@ * function numbers. */ current_func = 0; for (i = 0; i < rpc.num_ports; i++) { - if (!rpc.ports[i]->enabled) + if (!is_rp_enabled(i + 1)) continue; pch_pcie_device_set_func(i, current_func); current_func++; @@ -315,7 +328,7 @@ /* Allocate the disabled devices' PCI function number. */ for (i = 0; i < rpc.num_ports; i++) { - if (rpc.ports[i]->enabled) + if (is_rp_enabled(i + 1)) continue; pch_pcie_device_set_func(i, current_func); current_func++; -- To view, visit https://review.coreboot.org/c/coreboot/+/30079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Gerrit-Change-Number: 30079 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment
by Tristan Corrick (Code Review) 06 Dec '18

06 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30078 Change subject: sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment ...................................................................... sb/intel/lynxpoint/pcie.c: Fix a mistake in a comment The code annotated by the comment is dealing with root port 7, so update the comment to reflect that. It looks like the comment was copied from the root port 3 case, but not updated. Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30078/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index ca76aae..231f3e7 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -394,7 +394,7 @@ case 7: if (is_lp) break; - /* Root Port 3 is disabled in config 11b (1x4 links). */ + /* Root Port 7 is disabled in config 11b (1x4 links). */ if (((rpc.strpfusecfg2 >> 14) & 0x3) == 0x3) { root_port_mark_disable(dev); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/30078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e Gerrit-Change-Number: 30078 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports
by Tristan Corrick (Code Review) 06 Dec '18

06 Dec '18

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30077 Change subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports ...................................................................... sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/include/device/pci_ids.h M src/mainboard/asrock/h81m-hds/devicetree.cb M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c 5 files changed, 38 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30077/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b9c9152..751cca0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2661,11 +2661,26 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 -/* Intel Lynx Point Device IDS */ -#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN 0x8c41 -#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX 0x8c4f - /* Intel LPC device ids */ +#define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 +#define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 +#define PCI_DEVICE_ID_INTEL_LPT_Z87 0x8c44 +#define PCI_DEVICE_ID_INTEL_LPT_Z85 0x8c46 +#define PCI_DEVICE_ID_INTEL_LPT_HM86 0x8c49 +#define PCI_DEVICE_ID_INTEL_LPT_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_LPT_HM87 0x8c4b +#define PCI_DEVICE_ID_INTEL_LPT_Q85 0x8c4c +#define PCI_DEVICE_ID_INTEL_LPT_Q87 0x8c4e +#define PCI_DEVICE_ID_INTEL_LPT_QM87 0x8c4f +#define PCI_DEVICE_ID_INTEL_LPT_B85 0x8c50 +#define PCI_DEVICE_ID_INTEL_LPT_C222 0x8c52 +#define PCI_DEVICE_ID_INTEL_LPT_C224 0x8c54 +#define PCI_DEVICE_ID_INTEL_LPT_C226 0x8c56 +#define PCI_DEVICE_ID_INTEL_LPT_H81 0x8c5c +#define PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE 0x9c41 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM 0x9c43 +#define PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM 0x9c45 +#define PCI_DEVICE_ID_INTEL_LPT_LP_VALUE 0x9c47 #define PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE 0x9d41 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 32b5978..58a319d 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -102,8 +102,6 @@ device pci 1c.5 on # PCIe 1x slot subsystemid 0x1849 0x8c1a end - device pci 1c.6 off end # PCIe port #7 - device pci 1c.7 off end # PCIe port #8 device pci 1d.0 on # EHCI controller #1 subsystemid 0x1849 0x8c26 end diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index cb01de7..0821a17 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -42,6 +42,16 @@ return pch_revision_id; } +int pch_silicon_id(void) +{ + static int pch_id = -1; + + if (pch_id < 0) + pch_id = pci_read_config16(pch_get_lpc_device(), PCI_DEVICE_ID); + + return pch_id; +} + int pch_silicon_type(void) { static int pch_type = -1; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a28d703..ee041d9 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -141,6 +141,7 @@ #if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); +int pch_silicon_id(void); int pch_silicon_type(void); int pch_is_lp(void); u16 get_pmbase(void); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a7966f1..ca76aae 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -23,10 +23,7 @@ #include "pch.h" #include <southbridge/intel/common/gpio.h> -/* LynxPoint-LP has 6 root ports while non-LP has 8. */ #define MAX_NUM_ROOT_PORTS 8 -#define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS -#define LP_NUM_ROOT_PORTS (MAX_NUM_ROOT_PORTS - 2) struct root_port_config { /* RPFN is a write-once register so keep a copy until it is written */ @@ -49,10 +46,10 @@ static inline int max_root_ports(void) { - if (pch_is_lp()) - return LP_NUM_ROOT_PORTS; - else - return H_NUM_ROOT_PORTS; + if (pch_is_lp() || pch_silicon_id() == PCI_DEVICE_ID_INTEL_LPT_H81) + return 6; + + return 8; } static inline int root_port_is_first(struct device *dev) @@ -208,8 +205,10 @@ pci_update_config8(dev, 0xe1, 0x7f, 0x80); } if (rp == 5 && !rpc.ports[5]->enabled && - !rpc.ports[6]->enabled && - !rpc.ports[7]->enabled) { + (rpc.ports[6] == NULL || + !rpc.ports[6]->enabled) && + (rpc.ports[7] == NULL || + !rpc.ports[7]->enabled)) { pci_update_config8(dev, 0xe2, ~1, 1); pci_update_config8(dev, 0xe1, 0x7f, 0x80); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Gerrit-Change-Number: 30077 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Get rid of "#define __SIMPLE_DEVICE__"
by HAOUAS Elyes (Code Review) 06 Dec '18

06 Dec '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30040 ) Change subject: src: Get rid of "#define __SIMPLE_DEVICE__" ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dd770fcddf44aeec847d3651ec281af5f91fbf0 Gerrit-Change-Number: 30040 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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