Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29434
to look at the new patch set (#9).
Change subject: mb/lenovo/x220: Add x1 as a variant
......................................................................
mb/lenovo/x220: Add x1 as a variant
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220), and a powered ESATA port wired to ata4 (Linux' annotation).
Documentation added.
Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)
Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M Documentation/mainboard/index.md
M Documentation/mainboard/lenovo/t4xx_series.md
A Documentation/mainboard/lenovo/thinkpad_hmm.md
A Documentation/mainboard/lenovo/x1.md
A Documentation/mainboard/lenovo/x1_flash_ic.png
A Documentation/mainboard/lenovo/x2xx_series.md
M src/mainboard/lenovo/x220/Kconfig
M src/mainboard/lenovo/x220/Kconfig.name
M src/mainboard/lenovo/x220/Makefile.inc
M src/mainboard/lenovo/x220/devicetree.cb
M src/mainboard/lenovo/x220/romstage.c
A src/mainboard/lenovo/x220/variants/x1/data.vbt
A src/mainboard/lenovo/x220/variants/x1/gpio.c
A src/mainboard/lenovo/x220/variants/x1/overridetree.cb
A src/mainboard/lenovo/x220/variants/x1/romstage.c
R src/mainboard/lenovo/x220/variants/x220/data.vbt
R src/mainboard/lenovo/x220/variants/x220/gpio.c
A src/mainboard/lenovo/x220/variants/x220/overridetree.cb
A src/mainboard/lenovo/x220/variants/x220/romstage.c
19 files changed, 459 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29434/9
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Gerrit-Change-Number: 29434
Gerrit-PatchSet: 9
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30038 )
Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
......................................................................
Patch Set 2: Code-Review+2
Seems like by virtue of its name, it ought to run before AGESA. Good job getting rid of that blank line, BTW. That's been bugging me but wasn't worth a patch.
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Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30038 )
Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
......................................................................
Patch Set 2: Code-Review+2
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Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30039 )
Change subject: mainboard/google/kahlee: Add romstage GPIO initialization
......................................................................
Patch Set 1: Code-Review+2
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30038 )
Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/30038/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/30038/1//COMMIT_MSG@7
PS1, Line 7: stoneyridge
> Can you add a comment describing why it needs to move?
Done
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Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org>
Gerrit-MessageType: comment
Hello Simon Glass, Marshall Dawson, build bot (Jenkins), Raul Rangel, Daniel Kurtz,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30038
to look at the new patch set (#2).
Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
......................................................................
soc/amd/stoneyridge: Run romstage mainboard code before AGESA
This is needed so the next patch can set up GPIOs before
AGESA runs.
BUG=b:120436919
TEST=Verified romstage mainboard code runs before AGESA
Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
---
M src/soc/amd/stoneyridge/romstage.c
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/30038/2
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Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29945 )
Change subject: google/sarien: Increase BIOS region to 28MB
......................................................................
Patch Set 2:
It might be a good idea to restructure chromeos.fmd to move the legacy region to the bottom of the RW region in flash since it is not important to boot speed. We can do that in a separate CL though, I need to make some other changes to the layout to add the PDR region.
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