coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

1 participants
1832 discussions

Change in ...coreboot[master]: mb/google/sarien: Enable DPTF
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29762 ) Change subject: mb/google/sarien: Enable DPTF ...................................................................... mb/google/sarien: Enable DPTF Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29762 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/sarien/variants/arcada/devicetree.cb A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/arcada/include/variant/ec.h M src/mainboard/google/sarien/variants/sarien/devicetree.cb A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h 7 files changed, 137 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index bed06fe..7f46e4f 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -64,4 +64,15 @@ #include <ec/google/wilco/acpi/ec.asl> } #endif + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include <variant/acpi/dptf.asl> + /* Include soc specific DPTF changes */ + #include <soc/intel/cannonlake/acpi/dptf.asl> + /* Include common dptf ASL files */ + #include <soc/intel/common/acpi/dptf/dptf.asl> + } } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ee1cca0..4bd2d90 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -30,6 +30,7 @@ register "speed_shift_enable" = "1" register "s0ix_enable" = "1" + register "dptf_enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2d35878 --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + + /* CPU Effect on Board */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h index cb73092..01a17b5 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ec.h @@ -28,4 +28,7 @@ /* Enable PS/2 keyboard */ #define SIO_EC_ENABLE_PS2K +/* Enable DPTF */ +#define EC_ENABLE_DPTF + #endif diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b33c923..66f1711 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,7 @@ register "speed_shift_enable" = "1" register "s0ix_enable" = "1" + register "dptf_enable" = "1" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2d35878 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 100 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Thermal 1" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Thermal 2" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 80 + +#undef DPTF_ENABLE_FAN_CONTROL +#undef DPTF_ENABLE_CHARGER + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + + /* CPU Effect on Board */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h index cb73092..01a17b5 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ec.h @@ -28,4 +28,7 @@ /* Enable PS/2 keyboard */ #define SIO_EC_ENABLE_PS2K +/* Enable DPTF */ +#define EC_ENABLE_DPTF + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Gerrit-Change-Number: 29762 Gerrit-PatchSet: 6 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: ec/google/wilco: Guard DTPF with ifdef
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30036 ) Change subject: ec/google/wilco: Guard DTPF with ifdef ...................................................................... ec/google/wilco: Guard DTPF with ifdef There is a dependency issue with the EC DPTF code accessing methods that are external, but once the mainboard includes the relevant code they become internal and the current version of IASL used by jenkins will fail to compile it. Until the new IASL is deployed everywhere wrap the EC DPTF code and expect that the mainboard will explicitly enable it. Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/30036 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/event.asl 3 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index f5545d0..0f1663f 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -18,10 +18,6 @@ * Dynamic Platform Thermal Framework support */ -External (\_SB.DPTF.CTOK, MethodObj) -External (\_SB.DPTF.KTOC, MethodObj) -External (\_SB.DPTF.TEVT, MethodObj) - /* Mutex for EC PAT interface */ Mutex (PATM, 1) diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index ff8fccc..f9b16b5 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -147,5 +147,7 @@ #include "event.asl" #include "lid.asl" #include "platform.asl" +#ifdef EC_ENABLE_DPTF #include "dptf.asl" +#endif } diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 21721f2..4a3394f 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -88,10 +88,12 @@ { Printf ("EVT3: %o", Arg0) +#ifdef EC_ENABLE_DPTF /* Theraml Events */ If (EBIT (E3TH, Arg0)) { ^PATX () } +#endif } /* Handle events in PmEv4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Gerrit-Change-Number: 30036 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
by Raul Rangel (Code Review) 04 Dec '18

04 Dec '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30038 ) Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30038/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30038/1//COMMIT_MSG@7 PS1, Line 7: stoneyridge Can you add a comment describing why it needs to move? -- To view, visit https://review.coreboot.org/c/coreboot/+/30038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b Gerrit-Change-Number: 30038 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/google/kahlee: Add romstage GPIO initialization
by Martin Roth (Code Review) 04 Dec '18

04 Dec '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30039 Change subject: mainboard/google/kahlee: Add romstage GPIO initialization ...................................................................... mainboard/google/kahlee: Add romstage GPIO initialization Move the backlight initialization from bootblock to romstage BUG=b:120436919 TEST=Careena backlight is enabled Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h 3 files changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/30039/1 diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 5ec5c25..32f8356 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -15,6 +15,7 @@ #include <amdblocks/dimm_spd.h> #include <baseboard/variants.h> +#include <soc/gpio.h> #include <soc/romstage.h> int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) @@ -29,5 +30,11 @@ void mainboard_romstage_entry(int s3_resume) { + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_romstage_gpio_table(&num_gpios); + sb_program_gpios(gpios, num_gpios); + variant_romstage_entry(s3_resume); } diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 7922ea5..e9ae28c 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -77,9 +77,6 @@ /* GPIO_132 - CONFIG_STRAP4 */ PAD_GPI(GPIO_132, PULL_NONE), - /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ - PAD_GPO(GPIO_133, HIGH), - /* GPIO_136 - UART_PCH_RX_DEBUG_TX */ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), @@ -93,6 +90,11 @@ PAD_GPI(GPIO_142, PULL_NONE), }; +static const struct soc_amd_gpio gpio_set_stage_rom[] = { + /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ + PAD_GPO(GPIO_133, HIGH), +}; + static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), @@ -259,6 +261,13 @@ } const __weak +struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_rom); + return gpio_set_stage_rom; +} + +const __weak struct soc_amd_gpio *variant_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_ram); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 6e89105..da65bd8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -28,6 +28,7 @@ int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size); void variant_romstage_entry(int s3_resume); #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -- To view, visit https://review.coreboot.org/c/coreboot/+/30039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d Gerrit-Change-Number: 30039 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/amd/stoneyridge: Run romstage mainboard code before AGESA
by Martin Roth (Code Review) 04 Dec '18

04 Dec '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30038 Change subject: soc/amd/stoneyridge: Run romstage mainboard code before AGESA ...................................................................... soc/amd/stoneyridge: Run romstage mainboard code before AGESA BUG=b:120436919 TEST=Verified romstage mainboard code runs before AGESA Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/soc/amd/stoneyridge/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/30038/1 diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index ed83e1e..9314488 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -96,11 +96,10 @@ if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1(); + mainboard_romstage_entry(s3_resume); bsp_agesa_call(); - mainboard_romstage_entry(s3_resume); - if (!s3_resume) { post_code(0x40); do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost"); -- To view, visit https://review.coreboot.org/c/coreboot/+/30038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b Gerrit-Change-Number: 30038 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Furquan Shaikh (Code Review) 04 Dec '18

04 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:15:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Nick Vaccaro (Code Review) 04 Dec '18

04 Dec '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: Code-Review+1 > > So, the results look positive? "We ran memtester/fishtank with the bios that has the final CLs at 35C in a chamber on the following skus: DVT Main3, Main5, Main6, Main10, Main11, Mini, Main 3, Main 4, Main 6, Main 11 and EVT2 Main 9. with some VDDQ at default, VDDQ+3% and VDDQ -3%. The units were in the chamber running these tests overnight and in most cases over the weekend as well for almost 2 weeks now. In all the above, the units passed." -- To view, visit https://review.coreboot.org/c/coreboot/+/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:13:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Furquan Shaikh (Code Review) 04 Dec '18

04 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: > Patch Set 1: Code-Review+1 So, the results look positive? -- To view, visit https://review.coreboot.org/c/coreboot/+/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:12:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Nick Vaccaro (Code Review) 04 Dec '18

04 Dec '18

1 0

Change in ...coreboot[master]: mb/google/sarien: Enable DPTF
by Furquan Shaikh (Code Review) 04 Dec '18

04 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29762 ) Change subject: mb/google/sarien: Enable DPTF ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Gerrit-Change-Number: 29762 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 21:31:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2018